Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118026

1

T4

6

T5

1

T6

261

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	140618	1			T4	8		T5	2		T6	390
values[0x0]	65463	1			T4	3		T6	61		T23	1
values[0x1]	66122	1			T4	4		T6	60		T25	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124475	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147728

1

T4

8

T5

1

T6

307

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1193	1			T6	2		T1	2		T2	1
valid_sources[0x01]	1028	1			T6	1		T1	2		T2	3
valid_sources[0x02]	975	1			T6	1		T1	3		T2	1
valid_sources[0x03]	821	1			T14	1		T2	1		T3	5
valid_sources[0x04]	834	1			T23	1		T1	2		T2	2
valid_sources[0x05]	1819	1			T6	2		T14	2		T18	1
valid_sources[0x06]	826	1			T6	3		T1	3		T18	9
valid_sources[0x07]	913	1			T6	5		T1	1		T14	1
valid_sources[0x08]	914	1			T6	1		T20	1		T2	2
valid_sources[0x09]	1018	1			T6	3		T2	3		T3	9
valid_sources[0x0a]	1178	1			T6	1		T1	3		T19	1
valid_sources[0x0b]	1689	1			T6	1		T18	4		T2	5
valid_sources[0x0c]	1339	1			T1	4		T2	1		T3	2
valid_sources[0x0d]	1019	1			T6	1		T1	2		T14	1
valid_sources[0x0e]	943	1			T6	2		T1	4		T3	4
valid_sources[0x0f]	1139	1			T6	3		T1	1		T20	1
valid_sources[0x10]	732	1			T6	4		T1	4		T2	2
valid_sources[0x11]	1158	1			T6	1		T1	2		T2	2
valid_sources[0x12]	2034	1			T6	5		T20	2		T2	2
valid_sources[0x13]	768	1			T6	3		T18	20		T2	2
valid_sources[0x14]	1114	1			T6	2		T1	2		T3	6
valid_sources[0x15]	1279	1			T6	3		T1	1		T14	2
valid_sources[0x16]	891	1			T1	1		T2	2		T3	1
valid_sources[0x17]	859	1			T6	2		T1	1		T2	2
valid_sources[0x18]	845	1			T6	1		T14	1		T2	1
valid_sources[0x19]	832	1			T5	1		T6	2		T1	2
valid_sources[0x1a]	825	1			T6	1		T1	1		T2	5
valid_sources[0x1b]	816	1			T6	2		T1	1		T2	4
valid_sources[0x1c]	829	1			T6	2		T1	2		T2	1
valid_sources[0x1d]	972	1			T6	4		T1	5		T21	4
valid_sources[0x1e]	1009	1			T6	1		T2	2		T3	3
valid_sources[0x1f]	1002	1			T6	3		T1	1		T2	6
valid_sources[0x20]	1226	1			T6	1		T1	1		T2	4
valid_sources[0x21]	909	1			T6	3		T1	2		T47	3
valid_sources[0x22]	1946	1			T6	1		T20	2		T2	2
valid_sources[0x23]	730	1			T6	1		T1	1		T7	1
valid_sources[0x24]	1046	1			T6	3		T14	1		T2	1
valid_sources[0x25]	783	1			T6	5		T1	1		T14	1
valid_sources[0x26]	966	1			T6	1		T1	2		T2	2
valid_sources[0x27]	775	1			T6	2		T1	2		T2	4
valid_sources[0x28]	937	1			T6	2		T20	1		T2	1
valid_sources[0x29]	898	1			T6	5		T1	5		T2	1
valid_sources[0x2a]	890	1			T6	1		T2	2		T7	7
valid_sources[0x2b]	1344	1			T5	1		T6	2		T23	1
valid_sources[0x2c]	969	1			T6	3		T2	1		T3	3
valid_sources[0x2d]	1202	1			T6	2		T1	1		T2	3
valid_sources[0x2e]	1095	1			T6	3		T2	4		T3	2
valid_sources[0x2f]	795	1			T6	1		T2	1		T7	8
valid_sources[0x30]	1208	1			T6	2		T2	6		T3	6
valid_sources[0x31]	739	1			T6	1		T14	1		T2	1
valid_sources[0x32]	700	1			T6	4		T2	4		T47	1
valid_sources[0x33]	1371	1			T6	1		T1	1		T2	8
valid_sources[0x34]	952	1			T6	2		T14	1		T2	1
valid_sources[0x35]	865	1			T6	6		T1	4		T20	1
valid_sources[0x36]	980	1			T6	2		T1	1		T2	4
valid_sources[0x37]	757	1			T6	3		T1	1		T2	4
valid_sources[0x38]	758	1			T6	3		T1	2		T2	7
valid_sources[0x39]	766	1			T6	3		T1	2		T2	2
valid_sources[0x3a]	892	1			T6	1		T2	2		T7	3
valid_sources[0x3b]	761	1			T6	1		T1	1		T2	1
valid_sources[0x3c]	2486	1			T6	5		T14	1		T20	2
valid_sources[0x3d]	817	1			T6	5		T1	5		T2	2
valid_sources[0x3e]	1161	1			T6	8		T1	1		T2	6
valid_sources[0x3f]	961	1			T6	1		T23	1		T1	2
valid_sources[0x40]	795	1			T6	2		T1	1		T14	2
valid_sources[0x41]	870	1			T6	1		T1	2		T3	3
valid_sources[0x42]	1890	1			T6	3		T2	1		T3	3
valid_sources[0x43]	983	1			T6	2		T1	3		T2	1
valid_sources[0x44]	1204	1			T6	6		T1	3		T3	2
valid_sources[0x45]	1460	1			T6	3		T1	2		T19	2
valid_sources[0x46]	868	1			T6	2		T2	3		T3	2
valid_sources[0x47]	1439	1			T6	2		T1	2		T3	4
valid_sources[0x48]	1197	1			T6	5		T1	2		T2	4
valid_sources[0x49]	1121	1			T6	1		T20	1		T3	1
valid_sources[0x4a]	681	1			T23	1		T1	2		T14	1
valid_sources[0x4b]	845	1			T6	1		T23	1		T1	2
valid_sources[0x4c]	1319	1			T6	3		T1	1		T14	2
valid_sources[0x4d]	1239	1			T6	4		T1	2		T2	1
valid_sources[0x4e]	792	1			T1	1		T2	1		T3	3
valid_sources[0x4f]	1395	1			T6	1		T23	1		T1	3
valid_sources[0x50]	1060	1			T6	1		T1	3		T14	1
valid_sources[0x51]	778	1			T6	1		T1	2		T3	3
valid_sources[0x52]	808	1			T1	2		T18	1		T20	1
valid_sources[0x53]	906	1			T6	3		T2	4		T7	2
valid_sources[0x54]	1062	1			T4	2		T6	1		T1	2
valid_sources[0x55]	936	1			T6	1		T1	1		T2	3
valid_sources[0x56]	895	1			T6	2		T1	1		T2	4
valid_sources[0x57]	1617	1			T6	2		T1	1		T21	1
valid_sources[0x58]	1713	1			T6	2		T1	5		T14	1
valid_sources[0x59]	1029	1			T6	1		T23	1		T1	6
valid_sources[0x5a]	971	1			T6	1		T25	45		T1	1
valid_sources[0x5b]	789	1			T6	2		T1	2		T2	1
valid_sources[0x5c]	1655	1			T6	3		T23	1		T1	3
valid_sources[0x5d]	1324	1			T6	1		T1	2		T14	1
valid_sources[0x5e]	998	1			T6	2		T1	2		T2	2
valid_sources[0x5f]	815	1			T6	3		T1	2		T20	1
valid_sources[0x60]	822	1			T6	2		T1	2		T2	2
valid_sources[0x61]	748	1			T6	5		T1	2		T2	3
valid_sources[0x62]	1037	1			T6	1		T1	2		T16	1
valid_sources[0x63]	881	1			T6	4		T2	7		T3	2
valid_sources[0x64]	823	1			T6	1		T1	1		T14	1
valid_sources[0x65]	826	1			T6	1		T2	1		T3	4
valid_sources[0x66]	1922	1			T22	1		T2	1		T3	5
valid_sources[0x67]	1347	1			T6	2		T1	1		T19	4
valid_sources[0x68]	668	1			T6	4		T1	1		T2	2
valid_sources[0x69]	961	1			T6	2		T1	1		T20	1
valid_sources[0x6a]	865	1			T6	3		T2	5		T7	1
valid_sources[0x6b]	2075	1			T1	2		T19	2		T2	3
valid_sources[0x6c]	845	1			T6	6		T1	2		T2	3
valid_sources[0x6d]	779	1			T19	1		T2	5		T3	2
valid_sources[0x6e]	865	1			T1	3		T2	4		T3	1
valid_sources[0x6f]	1857	1			T6	2		T1	2		T2	2
valid_sources[0x70]	879	1			T6	2		T2	2		T3	2
valid_sources[0x71]	782	1			T6	1		T1	2		T2	3
valid_sources[0x72]	766	1			T6	1		T1	4		T2	5
valid_sources[0x73]	928	1			T4	1		T23	1		T1	1
valid_sources[0x74]	1119	1			T6	1		T1	1		T2	4
valid_sources[0x75]	715	1			T6	2		T1	4		T2	6
valid_sources[0x76]	827	1			T6	2		T22	2		T1	2
valid_sources[0x77]	1008	1			T4	1		T6	6		T1	7
valid_sources[0x78]	941	1			T6	2		T1	2		T3	4
valid_sources[0x79]	862	1			T6	1		T1	2		T14	2
valid_sources[0x7a]	909	1			T1	2		T14	1		T2	1
valid_sources[0x7b]	890	1			T6	5		T23	1		T1	7
valid_sources[0x7c]	932	1			T6	2		T1	3		T20	1
valid_sources[0x7d]	1133	1			T6	3		T1	1		T2	4
valid_sources[0x7e]	900	1			T6	2		T1	2		T14	1
valid_sources[0x7f]	1099	1			T1	4		T20	1		T2	1
valid_sources[0x80]	774	1			T1	1		T20	2		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63138

1

T4

3

T5

1

T6

203

values[0x0]

all_enables

biggest_size

32106

1

T4

3

T6

25

T23

1

values[0x1]

all_enables

biggest_size

22782

1

T6

33

T25

3

T1

9