Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T17,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T4,T17,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T17,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T17,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T17,T19
0	1	Covered	T78,T79,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T17,T19
0	1	Covered	T4,T17,T19
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T17,T19
1	-	Covered	T4,T17,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T17,T19
DetectSt	168	Covered	T4,T17,T19
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T4,T17,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T17,T19
DebounceSt->IdleSt	163	Covered	T8,T52,T54
DetectSt->IdleSt	186	Covered	T78,T79,T96
DetectSt->StableSt	191	Covered	T4,T17,T19
IdleSt->DebounceSt	148	Covered	T4,T17,T19
StableSt->IdleSt	206	Covered	T4,T17,T19

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T17,T19
0	1	Covered	T4,T17,T19
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T17,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T17,T19
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T17,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T52,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T17,T19
DetectSt	-	-	-	-	1	-	-	Covered	T78,T79,T96
DetectSt	-	-	-	-	0	1	-	Covered	T4,T17,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T17,T19
StableSt	-	-	-	-	-	-	0	Covered	T4,T17,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	323	0	0
CntIncr_A	6273387	151228	0	0
CntNoWrap_A	6273387	5593272	0	0
DetectStDropOut_A	6273387	5	0	0
DetectedOut_A	6273387	923	0	0
DetectedPulseOut_A	6273387	148	0	0
DisabledIdleSt_A	6273387	5435198	0	0
DisabledNoDetection_A	6273387	5437469	0	0
EnterDebounceSt_A	6273387	173	0	0
EnterDetectSt_A	6273387	153	0	0
EnterStableSt_A	6273387	148	0	0
PulseIsPulse_A	6273387	148	0	0
StayInStableSt	6273387	775	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6273387	6780	0	0
gen_low_level_sva.LowLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	148	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	323	0	0
T1	8415	0	0	0
T4	639	2	0	0
T5	423	0	0	0
T6	19504	0	0	0
T8	0	11	0	0
T14	522	0	0	0
T15	502	0	0	0
T17	0	4	0	0
T19	0	2	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	4	0	0
T47	0	4	0	0
T51	0	4	0	0
T52	0	3	0	0
T54	0	3	0	0
T72	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	151228	0	0
T1	8415	0	0	0
T4	639	52	0	0
T5	423	0	0	0
T6	19504	0	0	0
T8	0	278	0	0
T14	522	0	0	0
T15	502	0	0	0
T17	0	121	0	0
T19	0	79	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	121	0	0
T47	0	172	0	0
T51	0	77	0	0
T52	0	60	0	0
T54	0	95	0	0
T72	0	87	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593272	0	0
T1	8415	8012	0	0
T4	639	236	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5	0	0
T78	34491	1	0	0
T79	733	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	23465	0	0	0
T100	649	0	0	0
T101	402	0	0	0
T102	4424	0	0	0
T103	664	0	0	0
T104	1716	0	0	0
T105	424	0	0	0
T106	2396	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	923	0	0
T1	8415	0	0	0
T4	639	2	0	0
T5	423	0	0	0
T6	19504	0	0	0
T8	0	36	0	0
T14	522	0	0	0
T15	502	0	0	0
T17	0	16	0	0
T19	0	11	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	12	0	0
T47	0	13	0	0
T51	0	19	0	0
T52	0	4	0	0
T54	0	4	0	0
T72	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	148	0	0
T1	8415	0	0	0
T4	639	1	0	0
T5	423	0	0	0
T6	19504	0	0	0
T8	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T17	0	2	0	0
T19	0	1	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T54	0	1	0	0
T72	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5435198	0	0
T1	8415	8012	0	0
T4	639	142	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5437469	0	0
T1	8415	8014	0	0
T4	639	142	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	173	0	0
T1	8415	0	0	0
T4	639	1	0	0
T5	423	0	0	0
T6	19504	0	0	0
T8	0	6	0	0
T14	522	0	0	0
T15	502	0	0	0
T17	0	2	0	0
T19	0	1	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T72	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	153	0	0
T1	8415	0	0	0
T4	639	1	0	0
T5	423	0	0	0
T6	19504	0	0	0
T8	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T17	0	2	0	0
T19	0	1	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T54	0	1	0	0
T72	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	148	0	0
T1	8415	0	0	0
T4	639	1	0	0
T5	423	0	0	0
T6	19504	0	0	0
T8	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T17	0	2	0	0
T19	0	1	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T54	0	1	0	0
T72	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	148	0	0
T1	8415	0	0	0
T4	639	1	0	0
T5	423	0	0	0
T6	19504	0	0	0
T8	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T17	0	2	0	0
T19	0	1	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T54	0	1	0	0
T72	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	775	0	0
T1	8415	0	0	0
T4	639	1	0	0
T5	423	0	0	0
T6	19504	0	0	0
T8	0	31	0	0
T14	522	0	0	0
T15	502	0	0	0
T17	0	14	0	0
T19	0	10	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	10	0	0
T47	0	11	0	0
T51	0	17	0	0
T52	0	3	0	0
T54	0	3	0	0
T72	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	6780	0	0
T1	8415	14	0	0
T4	639	3	0	0
T5	423	3	0	0
T6	19504	13	0	0
T14	522	4	0	0
T15	502	6	0	0
T16	0	2	0	0
T22	403	0	0	0
T23	427	3	0	0
T24	421	3	0	0
T25	491	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	148	0	0
T1	8415	0	0	0
T4	639	1	0	0
T5	423	0	0	0
T6	19504	0	0	0
T8	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T17	0	2	0	0
T19	0	1	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T54	0	1	0	0
T72	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T11,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T11,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T13
0	1	Covered	T62,T73,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T13
0	1	Unreachable
1	0	Covered	T8,T11,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T13
DetectSt	168	Covered	T8,T11,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T11,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T13
DebounceSt->IdleSt	163	Covered	T60,T73,T58
DetectSt->IdleSt	186	Covered	T62,T73,T87
DetectSt->StableSt	191	Covered	T8,T11,T13
IdleSt->DebounceSt	148	Covered	T8,T11,T13
StableSt->IdleSt	206	Covered	T8,T11,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T13
0	1	Covered	T8,T11,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T60,T73,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T13
DetectSt	-	-	-	-	1	-	-	Covered	T62,T73,T87
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T13
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	198	0	0
CntIncr_A	6273387	10231	0	0
CntNoWrap_A	6273387	5593397	0	0
DetectStDropOut_A	6273387	11	0	0
DetectedOut_A	6273387	17287	0	0
DetectedPulseOut_A	6273387	52	0	0
DisabledIdleSt_A	6273387	4588437	0	0
DisabledNoDetection_A	6273387	4590765	0	0
EnterDebounceSt_A	6273387	136	0	0
EnterDetectSt_A	6273387	63	0	0
EnterStableSt_A	6273387	52	0	0
PulseIsPulse_A	6273387	52	0	0
StayInStableSt	6273387	17235	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6273387	6780	0	0
gen_low_level_sva.LowLevelEvent_A	6273387	5595925	0	0
gen_sticky_sva.StableStDropOut_A	6273387	798055	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	198	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T13	0	4	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T60	0	5	0	0
T62	0	2	0	0
T70	570	0	0	0
T72	0	2	0	0
T73	0	8	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	10231	0	0
T8	303659	29	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	92	0	0
T13	0	154	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	59	0	0
T60	0	255	0	0
T62	0	29	0	0
T70	570	0	0	0
T72	0	60	0	0
T73	0	440	0	0
T74	0	38	0	0
T75	0	65	0	0
T76	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593397	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	11	0	0
T62	11979	1	0	0
T63	2609	0	0	0
T73	0	3	0	0
T87	0	1	0	0
T108	0	3	0	0
T112	0	1	0	0
T113	0	2	0	0
T114	493	0	0	0
T115	505	0	0	0
T116	492	0	0	0
T117	424	0	0	0
T118	495	0	0	0
T119	425	0	0	0
T120	496	0	0	0
T121	1123	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	17287	0	0
T8	303659	198	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	345	0	0
T13	0	941	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T72	0	51	0	0
T74	0	76	0	0
T75	0	171	0	0
T76	406	0	0	0
T78	0	47	0	0
T107	0	61	0	0
T109	0	36	0	0
T110	0	587	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	52	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T72	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0
T78	0	1	0	0
T107	0	2	0	0
T109	0	1	0	0
T110	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	4588437	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	4590765	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	136	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T60	0	5	0	0
T62	0	1	0	0
T70	570	0	0	0
T72	0	1	0	0
T73	0	5	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	63	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T62	0	1	0	0
T70	570	0	0	0
T72	0	1	0	0
T73	0	3	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0
T87	0	1	0	0
T107	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	52	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T72	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0
T78	0	1	0	0
T107	0	2	0	0
T109	0	1	0	0
T110	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	52	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T72	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0
T78	0	1	0	0
T107	0	2	0	0
T109	0	1	0	0
T110	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	17235	0	0
T8	303659	197	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	344	0	0
T13	0	939	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T72	0	50	0	0
T74	0	75	0	0
T75	0	170	0	0
T76	406	0	0	0
T78	0	46	0	0
T107	0	59	0	0
T109	0	35	0	0
T110	0	585	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	6780	0	0
T1	8415	14	0	0
T4	639	3	0	0
T5	423	3	0	0
T6	19504	13	0	0
T14	522	4	0	0
T15	502	6	0	0
T16	0	2	0	0
T22	403	0	0	0
T23	427	3	0	0
T24	421	3	0	0
T25	491	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	798055	0	0
T8	303659	431	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	68	0	0
T13	0	292652	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T72	0	72	0	0
T74	0	72	0	0
T75	0	100	0	0
T76	406	0	0	0
T78	0	51	0	0
T107	0	305	0	0
T109	0	322	0	0
T110	0	587	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T22,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T22,T23
1	1	Covered	T5,T22,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T11,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T13
1	0	Covered	T5,T22,T23
1	1	Covered	T8,T11,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T60
0	1	Covered	T80,T85,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T60
0	1	Unreachable
1	0	Covered	T8,T11,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T13
DetectSt	168	Covered	T8,T11,T60
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T11,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T60
DebounceSt->IdleSt	163	Covered	T13,T72,T58
DetectSt->IdleSt	186	Covered	T80,T85,T86
DetectSt->StableSt	191	Covered	T8,T11,T60
IdleSt->DebounceSt	148	Covered	T8,T11,T13
StableSt->IdleSt	206	Covered	T8,T11,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T13
0	1	Covered	T8,T11,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T13
IdleSt	0	-	-	-	-	-	-	Covered	T5,T22,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T72,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T13
DetectSt	-	-	-	-	1	-	-	Covered	T80,T85,T86
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T60
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	210	0	0
CntIncr_A	6273387	299641	0	0
CntNoWrap_A	6273387	5593385	0	0
DetectStDropOut_A	6273387	21	0	0
DetectedOut_A	6273387	10724	0	0
DetectedPulseOut_A	6273387	58	0	0
DisabledIdleSt_A	6273387	4588437	0	0
DisabledNoDetection_A	6273387	4590765	0	0
EnterDebounceSt_A	6273387	132	0	0
EnterDetectSt_A	6273387	79	0	0
EnterStableSt_A	6273387	58	0	0
PulseIsPulse_A	6273387	58	0	0
StayInStableSt	6273387	10666	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_sticky_sva.StableStDropOut_A	6273387	307770	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	210	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T13	0	10	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T60	0	4	0	0
T62	0	2	0	0
T70	570	0	0	0
T72	0	1	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	299641	0	0
T8	303659	98	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	29	0	0
T13	0	293620	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	60	0	0
T60	0	108	0	0
T62	0	18	0	0
T70	570	0	0	0
T72	0	79	0	0
T73	0	158	0	0
T74	0	50	0	0
T75	0	58	0	0
T76	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593385	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	21	0	0
T80	23083	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T92	11482	0	0	0
T122	0	2	0	0
T123	0	1	0	0
T124	0	4	0	0
T125	0	7	0	0
T126	0	1	0	0
T127	12446	0	0	0
T128	502	0	0	0
T129	999	0	0	0
T130	4516	0	0	0
T131	431	0	0	0
T132	4720	0	0	0
T133	506	0	0	0
T134	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	10724	0	0
T8	303659	400	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	192	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T60	0	231	0	0
T62	0	11	0	0
T70	570	0	0	0
T73	0	513	0	0
T74	0	102	0	0
T75	0	69	0	0
T76	406	0	0	0
T87	0	79	0	0
T107	0	138	0	0
T108	0	146	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	58	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T60	0	2	0	0
T62	0	1	0	0
T70	570	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0
T87	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	4588437	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	4590765	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	132	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T13	0	10	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T60	0	2	0	0
T62	0	1	0	0
T70	570	0	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	79	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T60	0	2	0	0
T62	0	1	0	0
T70	570	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0
T87	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	58	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T60	0	2	0	0
T62	0	1	0	0
T70	570	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0
T87	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	58	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T60	0	2	0	0
T62	0	1	0	0
T70	570	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0
T87	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	10666	0	0
T8	303659	399	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	191	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T60	0	229	0	0
T62	0	10	0	0
T70	570	0	0	0
T73	0	511	0	0
T74	0	101	0	0
T75	0	68	0	0
T76	406	0	0	0
T87	0	78	0	0
T107	0	136	0	0
T108	0	145	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	307770	0	0
T8	303659	166	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	439	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T60	0	332	0	0
T62	0	23	0	0
T70	570	0	0	0
T73	0	94	0	0
T74	0	42	0	0
T75	0	196	0	0
T76	406	0	0	0
T87	0	8691	0	0
T107	0	132	0	0
T108	0	366	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T11,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T13,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T13
1	0	Covered	T5,T6,T23
1	1	Covered	T8,T11,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T60,T62
0	1	Covered	T11,T13,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T60,T62
0	1	Unreachable
1	0	Covered	T11,T60,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T13
DetectSt	168	Covered	T11,T13,T60
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T60,T62

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T13,T60
DebounceSt->IdleSt	163	Covered	T8,T11,T13
DetectSt->IdleSt	186	Covered	T11,T13,T83
DetectSt->StableSt	191	Covered	T11,T60,T62
IdleSt->DebounceSt	148	Covered	T8,T11,T13
StableSt->IdleSt	206	Covered	T11,T60,T62

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T13
0	1	Covered	T8,T11,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T13,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T13
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T13,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T11,T13
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T13
DetectSt	-	-	-	-	1	-	-	Covered	T11,T13,T83
DetectSt	-	-	-	-	0	1	-	Covered	T11,T60,T62
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T60,T62
StableSt	-	-	-	-	-	-	0	Covered	T11,T60,T62
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	191	0	0
CntIncr_A	6273387	221144	0	0
CntNoWrap_A	6273387	5593404	0	0
DetectStDropOut_A	6273387	8	0	0
DetectedOut_A	6273387	463889	0	0
DetectedPulseOut_A	6273387	57	0	0
DisabledIdleSt_A	6273387	4588437	0	0
DisabledNoDetection_A	6273387	4590765	0	0
EnterDebounceSt_A	6273387	127	0	0
EnterDetectSt_A	6273387	65	0	0
EnterStableSt_A	6273387	57	0	0
PulseIsPulse_A	6273387	57	0	0
StayInStableSt	6273387	463832	0	0
gen_high_event_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_sticky_sva.StableStDropOut_A	6273387	11566	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	191	0	0
T8	303659	5	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	6	0	0
T13	0	11	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T60	0	4	0	0
T62	0	2	0	0
T70	570	0	0	0
T72	0	1	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	221144	0	0
T8	303659	100	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	84	0	0
T13	0	200	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	62	0	0
T60	0	20	0	0
T62	0	27	0	0
T70	570	0	0	0
T72	0	48	0	0
T73	0	36	0	0
T74	0	18	0	0
T75	0	85	0	0
T76	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593404	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	8	0	0
T11	4766	1	0	0
T12	669	0	0	0
T13	294246	1	0	0
T35	29289	0	0	0
T41	545	0	0	0
T44	853	0	0	0
T51	626	0	0	0
T64	498	0	0	0
T65	494	0	0	0
T83	0	1	0	0
T111	421	0	0	0
T122	0	1	0	0
T124	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	463889	0	0
T11	4766	1	0	0
T12	669	0	0	0
T13	294246	0	0	0
T35	29289	0	0	0
T41	545	0	0	0
T44	853	0	0	0
T51	626	0	0	0
T60	0	55	0	0
T62	0	4	0	0
T64	498	0	0	0
T65	494	0	0	0
T73	0	72	0	0
T74	0	51	0	0
T75	0	226	0	0
T78	0	41	0	0
T87	0	1	0	0
T107	0	270	0	0
T108	0	421	0	0
T111	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	57	0	0
T11	4766	1	0	0
T12	669	0	0	0
T13	294246	0	0	0
T35	29289	0	0	0
T41	545	0	0	0
T44	853	0	0	0
T51	626	0	0	0
T60	0	2	0	0
T62	0	1	0	0
T64	498	0	0	0
T65	494	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T87	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0
T111	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	4588437	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	4590765	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	127	0	0
T8	303659	5	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	4	0	0
T13	0	10	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T60	0	2	0	0
T62	0	1	0	0
T70	570	0	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	65	0	0
T11	4766	2	0	0
T12	669	0	0	0
T13	294246	1	0	0
T35	29289	0	0	0
T41	545	0	0	0
T44	853	0	0	0
T51	626	0	0	0
T60	0	2	0	0
T62	0	1	0	0
T64	498	0	0	0
T65	494	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T87	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0
T111	421	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	57	0	0
T11	4766	1	0	0
T12	669	0	0	0
T13	294246	0	0	0
T35	29289	0	0	0
T41	545	0	0	0
T44	853	0	0	0
T51	626	0	0	0
T60	0	2	0	0
T62	0	1	0	0
T64	498	0	0	0
T65	494	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T87	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0
T111	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	57	0	0
T11	4766	1	0	0
T12	669	0	0	0
T13	294246	0	0	0
T35	29289	0	0	0
T41	545	0	0	0
T44	853	0	0	0
T51	626	0	0	0
T60	0	2	0	0
T62	0	1	0	0
T64	498	0	0	0
T65	494	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T87	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0
T111	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	463832	0	0
T37	32959	0	0	0
T45	11084	0	0	0
T60	1169	53	0	0
T62	0	3	0	0
T73	0	70	0	0
T74	0	50	0	0
T75	0	225	0	0
T78	0	40	0	0
T107	0	268	0	0
T108	0	420	0	0
T109	0	74	0	0
T110	0	195	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T141	522	0	0	0
T142	535	0	0	0
T143	648	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	11566	0	0
T11	4766	168	0	0
T12	669	0	0	0
T13	294246	0	0	0
T35	29289	0	0	0
T41	545	0	0	0
T44	853	0	0	0
T51	626	0	0	0
T60	0	623	0	0
T62	0	33	0	0
T64	498	0	0	0
T65	494	0	0	0
T73	0	675	0	0
T74	0	127	0	0
T75	0	32	0	0
T78	0	57	0	0
T87	0	28	0	0
T107	0	62	0	0
T108	0	50	0	0
T111	421	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T11,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T11,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T36
0	1	Covered	T11,T36,T43
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T36
1	-	Covered	T11,T36,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T36
DetectSt	168	Covered	T9,T11,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T11,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T36
DebounceSt->IdleSt	163	Covered	T95,T144,T145
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T11,T36
IdleSt->DebounceSt	148	Covered	T9,T11,T36
StableSt->IdleSt	206	Covered	T11,T36,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T36
0	1	Covered	T9,T11,T36
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T95,T144,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T36,T43
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	89	0	0
CntIncr_A	6273387	1854	0	0
CntNoWrap_A	6273387	5593506	0	0
DetectStDropOut_A	6273387	0	0	0
DetectedOut_A	6273387	2946	0	0
DetectedPulseOut_A	6273387	43	0	0
DisabledIdleSt_A	6273387	5577940	0	0
DisabledNoDetection_A	6273387	5580219	0	0
EnterDebounceSt_A	6273387	46	0	0
EnterDetectSt_A	6273387	43	0	0
EnterStableSt_A	6273387	43	0	0
PulseIsPulse_A	6273387	43	0	0
StayInStableSt	6273387	2890	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	89	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	2	0	0
T12	669	0	0	0
T36	0	4	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T62	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1854	0	0
T9	713	25	0	0
T10	512	0	0	0
T11	4766	54	0	0
T12	669	0	0	0
T36	0	26	0	0
T43	0	39	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T62	0	37	0	0
T70	570	0	0	0
T76	406	0	0	0
T146	0	13	0	0
T147	0	29	0	0
T148	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593506	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2946	0	0
T9	713	264	0	0
T10	512	0	0	0
T11	4766	14	0	0
T12	669	0	0	0
T36	0	67	0	0
T43	0	82	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	9	0	0
T62	0	77	0	0
T70	570	0	0	0
T76	406	0	0	0
T146	0	61	0	0
T147	0	43	0	0
T148	0	73	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	43	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	4766	1	0	0
T12	669	0	0	0
T36	0	2	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5577940	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5580219	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	46	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	4766	1	0	0
T12	669	0	0	0
T36	0	2	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	43	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	4766	1	0	0
T12	669	0	0	0
T36	0	2	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	43	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	4766	1	0	0
T12	669	0	0	0
T36	0	2	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	43	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	4766	1	0	0
T12	669	0	0	0
T36	0	2	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2890	0	0
T9	713	262	0	0
T10	512	0	0	0
T11	4766	13	0	0
T12	669	0	0	0
T36	0	65	0	0
T43	0	81	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	4	0	0
T59	0	8	0	0
T62	0	76	0	0
T70	570	0	0	0
T76	406	0	0	0
T146	0	59	0	0
T147	0	41	0	0
T148	0	72	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	28	0	0
T11	4766	1	0	0
T12	669	0	0	0
T13	294246	0	0	0
T35	29289	0	0	0
T36	0	2	0	0
T41	545	0	0	0
T43	0	1	0	0
T44	853	0	0	0
T51	626	0	0	0
T62	0	1	0	0
T64	498	0	0	0
T65	494	0	0	0
T111	421	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T5,T6,T23
1	1	Covered	T3,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T154,T155
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T3,T11,T40
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T12
1	-	Covered	T3,T11,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T12
DetectSt	168	Covered	T3,T11,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T12
DebounceSt->IdleSt	163	Covered	T80,T156,T157
DetectSt->IdleSt	186	Covered	T154,T155
DetectSt->StableSt	191	Covered	T3,T11,T12
IdleSt->DebounceSt	148	Covered	T3,T11,T12
StableSt->IdleSt	206	Covered	T3,T11,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T12
0	1	Covered	T3,T11,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T157,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T154,T155
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T40
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	152	0	0
CntIncr_A	6273387	7679	0	0
CntNoWrap_A	6273387	5593443	0	0
DetectStDropOut_A	6273387	2	0	0
DetectedOut_A	6273387	6118	0	0
DetectedPulseOut_A	6273387	72	0	0
DisabledIdleSt_A	6273387	5570744	0	0
DisabledNoDetection_A	6273387	5573021	0	0
EnterDebounceSt_A	6273387	79	0	0
EnterDetectSt_A	6273387	74	0	0
EnterStableSt_A	6273387	72	0	0
PulseIsPulse_A	6273387	72	0	0
StayInStableSt	6273387	6013	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6273387	2686	0	0
gen_low_level_sva.LowLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	152	0	0
T3	9905	2	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	4	0	0
T12	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T62	0	4	0	0
T63	0	2	0	0
T159	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	7679	0	0
T3	9905	41	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	194	0	0
T12	0	76	0	0
T40	0	82	0	0
T41	0	19	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T62	0	74	0	0
T63	0	11	0	0
T159	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593443	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2	0	0
T81	18054	0	0	0
T149	761	0	0	0
T154	833	1	0	0
T155	0	1	0	0
T160	598	0	0	0
T161	16546	0	0	0
T162	11012	0	0	0
T163	419	0	0	0
T164	17305	0	0	0
T165	888	0	0	0
T166	2426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	6118	0	0
T3	9905	40	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	82	0	0
T12	0	37	0	0
T40	0	228	0	0
T41	0	48	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	3	0	0
T59	0	9	0	0
T62	0	62	0	0
T63	0	60	0	0
T159	0	198	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	72	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T159	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5570744	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5573021	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	79	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T159	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	74	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T159	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	72	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T159	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	72	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T159	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	6013	0	0
T3	9905	39	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	80	0	0
T12	0	35	0	0
T40	0	227	0	0
T41	0	46	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	2	0	0
T59	0	8	0	0
T62	0	59	0	0
T63	0	58	0	0
T159	0	196	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2686	0	0
T1	8415	0	0	0
T5	423	2	0	0
T6	19504	0	0	0
T14	522	6	0	0
T15	502	5	0	0
T16	421	4	0	0
T18	0	5	0	0
T20	0	6	0	0
T21	0	2	0	0
T22	403	0	0	0
T23	427	3	0	0
T24	421	2	0	0
T25	491	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	37	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T40	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T62	0	1	0	0
T95	0	1	0	0
T159	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	2	0	0
T170	0	1	0	0