Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T11,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T11,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T36
0	1	Covered	T158
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T36
0	1	Covered	T9,T11,T36
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T36
1	-	Covered	T9,T11,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T36
DetectSt	168	Covered	T9,T11,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T11,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T36
DebounceSt->IdleSt	163	Covered	T144
DetectSt->IdleSt	186	Covered	T158
DetectSt->StableSt	191	Covered	T9,T11,T36
IdleSt->DebounceSt	148	Covered	T9,T11,T36
StableSt->IdleSt	206	Covered	T9,T11,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T36
0	1	Covered	T9,T11,T36
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T144
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T36
DetectSt	-	-	-	-	1	-	-	Covered	T158
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T36
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	97	0	0
CntIncr_A	6273387	2532	0	0
CntNoWrap_A	6273387	5593498	0	0
DetectStDropOut_A	6273387	1	0	0
DetectedOut_A	6273387	3763	0	0
DetectedPulseOut_A	6273387	47	0	0
DisabledIdleSt_A	6273387	5573956	0	0
DisabledNoDetection_A	6273387	5576233	0	0
EnterDebounceSt_A	6273387	49	0	0
EnterDetectSt_A	6273387	48	0	0
EnterStableSt_A	6273387	47	0	0
PulseIsPulse_A	6273387	47	0	0
StayInStableSt	6273387	3692	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	97	0	0
T9	713	4	0	0
T10	512	0	0	0
T11	4766	6	0	0
T12	669	0	0	0
T36	0	4	0	0
T40	0	4	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	2	0	0
T106	0	2	0	0
T167	0	2	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2532	0	0
T9	713	50	0	0
T10	512	0	0	0
T11	4766	230	0	0
T12	669	0	0	0
T36	0	91	0	0
T40	0	164	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	95	0	0
T106	0	29	0	0
T167	0	37	0	0
T171	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593498	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1	0	0
T158	11361	1	0	0
T172	4766	0	0	0
T173	494	0	0	0
T174	35040	0	0	0
T175	494	0	0	0
T176	16916	0	0	0
T177	406	0	0	0
T178	495	0	0	0
T179	12549	0	0	0
T180	15137	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	3763	0	0
T9	713	168	0	0
T10	512	0	0	0
T11	4766	133	0	0
T12	669	0	0	0
T36	0	56	0	0
T40	0	139	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	3	0	0
T59	0	7	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	39	0	0
T106	0	38	0	0
T167	0	41	0	0
T171	0	120	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	47	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T36	0	2	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	1	0	0
T106	0	1	0	0
T167	0	1	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5573956	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5576233	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	49	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T36	0	2	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	1	0	0
T106	0	1	0	0
T167	0	1	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	48	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T36	0	2	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	1	0	0
T106	0	1	0	0
T167	0	1	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	47	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T36	0	2	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	1	0	0
T106	0	1	0	0
T167	0	1	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	47	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T36	0	2	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	1	0	0
T106	0	1	0	0
T167	0	1	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	3692	0	0
T9	713	165	0	0
T10	512	0	0	0
T11	4766	129	0	0
T12	669	0	0	0
T36	0	53	0	0
T40	0	136	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	6	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	37	0	0
T106	0	36	0	0
T167	0	40	0	0
T171	0	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	21	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	4766	2	0	0
T12	669	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T76	406	0	0	0
T95	0	1	0	0
T164	0	1	0	0
T167	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T11
1	0	Covered	T5,T6,T23
1	1	Covered	T3,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T184,T185,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T9,T11,T36
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T11
1	-	Covered	T9,T11,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T11
DetectSt	168	Covered	T3,T9,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T11
DebounceSt->IdleSt	163	Covered	T9,T11,T41
DetectSt->IdleSt	186	Covered	T184,T185,T95
DetectSt->StableSt	191	Covered	T3,T9,T11
IdleSt->DebounceSt	148	Covered	T3,T9,T11
StableSt->IdleSt	206	Covered	T3,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T11,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T184,T185,T95
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T36
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	155	0	0
CntIncr_A	6273387	77350	0	0
CntNoWrap_A	6273387	5593440	0	0
DetectStDropOut_A	6273387	4	0	0
DetectedOut_A	6273387	152194	0	0
DetectedPulseOut_A	6273387	71	0	0
DisabledIdleSt_A	6273387	5300149	0	0
DisabledNoDetection_A	6273387	5302420	0	0
EnterDebounceSt_A	6273387	81	0	0
EnterDetectSt_A	6273387	75	0	0
EnterStableSt_A	6273387	71	0	0
PulseIsPulse_A	6273387	71	0	0
StayInStableSt	6273387	152092	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6273387	3077	0	0
gen_low_level_sva.LowLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	155	0	0
T3	9905	2	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	3	0	0
T10	512	0	0	0
T11	0	11	0	0
T36	0	4	0	0
T41	0	3	0	0
T43	0	4	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T62	0	2	0	0
T159	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	77350	0	0
T3	9905	41	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	50	0	0
T10	512	0	0	0
T11	0	374	0	0
T36	0	26	0	0
T41	0	38	0	0
T43	0	78	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T62	0	37	0	0
T159	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593440	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	4	0	0
T95	0	1	0	0
T110	2294	0	0	0
T158	0	1	0	0
T184	478	1	0	0
T185	0	1	0	0
T186	402	0	0	0
T187	504	0	0	0
T188	3875	0	0	0
T189	610	0	0	0
T190	16858	0	0	0
T191	5469	0	0	0
T192	422	0	0	0
T193	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	152194	0	0
T3	9905	256	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	43	0	0
T10	512	0	0	0
T11	0	573	0	0
T36	0	160	0	0
T41	0	38	0	0
T43	0	83	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	4	0	0
T59	0	9	0	0
T62	0	38	0	0
T159	0	215	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	71	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	0	5	0	0
T36	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T159	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5300149	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5302420	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	81	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	0	6	0	0
T36	0	2	0	0
T41	0	2	0	0
T43	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T159	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	75	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	0	5	0	0
T36	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T159	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	71	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	0	5	0	0
T36	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T159	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	71	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	0	5	0	0
T36	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T159	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	152092	0	0
T3	9905	254	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	42	0	0
T10	512	0	0	0
T11	0	566	0	0
T36	0	157	0	0
T41	0	36	0	0
T43	0	80	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	3	0	0
T59	0	8	0	0
T62	0	36	0	0
T159	0	212	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	3077	0	0
T1	8415	0	0	0
T5	423	3	0	0
T6	19504	0	0	0
T14	522	5	0	0
T15	502	6	0	0
T16	421	2	0	0
T18	0	4	0	0
T20	0	4	0	0
T21	0	3	0	0
T22	403	0	0	0
T23	427	2	0	0
T24	421	2	0	0
T25	491	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	38	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T36	0	1	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	1	0	0
T129	0	1	0	0
T156	0	1	0	0
T159	0	1	0	0
T181	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T23
1	1	Covered	T5,T6,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T35
1	0	Covered	T5,T6,T23
1	1	Covered	T3,T8,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T44
0	1	Covered	T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T44
0	1	Covered	T3,T8,T44
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T44
1	-	Covered	T3,T8,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T44
DetectSt	168	Covered	T3,T8,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T44
DebounceSt->IdleSt	163	Covered	T185,T182,T195
DetectSt->IdleSt	186	Covered	T154
DetectSt->StableSt	191	Covered	T3,T8,T44
IdleSt->DebounceSt	148	Covered	T3,T8,T44
StableSt->IdleSt	206	Covered	T3,T8,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T44
0	1	Covered	T3,T8,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T44
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T23
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T185,T182,T195
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T44
DetectSt	-	-	-	-	1	-	-	Covered	T154
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T44
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	141	0	0
CntIncr_A	6273387	99342	0	0
CntNoWrap_A	6273387	5593454	0	0
DetectStDropOut_A	6273387	1	0	0
DetectedOut_A	6273387	53643	0	0
DetectedPulseOut_A	6273387	68	0	0
DisabledIdleSt_A	6273387	5290339	0	0
DisabledNoDetection_A	6273387	5292612	0	0
EnterDebounceSt_A	6273387	72	0	0
EnterDetectSt_A	6273387	69	0	0
EnterStableSt_A	6273387	68	0	0
PulseIsPulse_A	6273387	68	0	0
StayInStableSt	6273387	53552	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	141	0	0
T3	9905	2	0	0
T7	12899	0	0	0
T8	303659	4	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	2	0	0
T44	0	4	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T62	0	2	0	0
T89	0	2	0	0
T159	0	4	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	99342	0	0
T3	9905	41	0	0
T7	12899	0	0	0
T8	303659	95956	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	84	0	0
T44	0	146	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T62	0	37	0	0
T89	0	31	0	0
T159	0	64	0	0
T171	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593454	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1	0	0
T81	18054	0	0	0
T149	761	0	0	0
T154	833	1	0	0
T160	598	0	0	0
T161	16546	0	0	0
T162	11012	0	0	0
T163	419	0	0	0
T164	17305	0	0	0
T165	888	0	0	0
T166	2426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	53643	0	0
T3	9905	40	0	0
T7	12899	0	0	0
T8	303659	48066	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	391	0	0
T44	0	203	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	5	0	0
T59	0	8	0	0
T62	0	99	0	0
T89	0	41	0	0
T159	0	45	0	0
T171	0	325	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	68	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	1	0	0
T44	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T89	0	1	0	0
T159	0	2	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5290339	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5292612	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	72	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	1	0	0
T44	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T89	0	1	0	0
T159	0	2	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	69	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	1	0	0
T44	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T89	0	1	0	0
T159	0	2	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	68	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	1	0	0
T44	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T89	0	1	0	0
T159	0	2	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	68	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	1	0	0
T44	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T89	0	1	0	0
T159	0	2	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	53552	0	0
T3	9905	39	0	0
T7	12899	0	0	0
T8	303659	48064	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	389	0	0
T44	0	200	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	4	0	0
T59	0	7	0	0
T62	0	98	0	0
T89	0	40	0	0
T159	0	43	0	0
T171	0	323	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	43	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T44	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T62	0	1	0	0
T80	0	1	0	0
T89	0	1	0	0
T147	0	1	0	0
T159	0	2	0	0
T167	0	1	0	0
T188	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T11,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T11
1	0	Covered	T5,T6,T23
1	1	Covered	T8,T11,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T41
0	1	Covered	T8,T11,T40
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T41
1	-	Covered	T8,T11,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T41
DetectSt	168	Covered	T8,T11,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T11,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T41
DebounceSt->IdleSt	163	Covered	T11,T148,T149
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T11,T41
IdleSt->DebounceSt	148	Covered	T8,T11,T41
StableSt->IdleSt	206	Covered	T8,T11,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T41
0	1	Covered	T8,T11,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T148,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T40
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	134	0	0
CntIncr_A	6273387	38372	0	0
CntNoWrap_A	6273387	5593461	0	0
DetectStDropOut_A	6273387	0	0	0
DetectedOut_A	6273387	23612	0	0
DetectedPulseOut_A	6273387	64	0	0
DisabledIdleSt_A	6273387	5294105	0	0
DisabledNoDetection_A	6273387	5296358	0	0
EnterDebounceSt_A	6273387	70	0	0
EnterDetectSt_A	6273387	64	0	0
EnterStableSt_A	6273387	64	0	0
PulseIsPulse_A	6273387	64	0	0
StayInStableSt	6273387	23514	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6273387	6498	0	0
gen_low_level_sva.LowLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	134	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	5	0	0
T40	0	6	0	0
T41	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	4	0	0
T89	0	2	0	0
T159	0	4	0	0
T167	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	38372	0	0
T8	303659	32	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	230	0	0
T40	0	246	0	0
T41	0	19	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	146	0	0
T89	0	31	0	0
T159	0	64	0	0
T167	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593461	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	23612	0	0
T8	303659	4	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	196	0	0
T40	0	120	0	0
T41	0	48	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	4	0	0
T59	0	8	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	117	0	0
T89	0	103	0	0
T159	0	216	0	0
T167	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	64	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T40	0	3	0	0
T41	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	2	0	0
T89	0	1	0	0
T159	0	2	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5294105	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5296358	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	70	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	3	0	0
T40	0	3	0	0
T41	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	2	0	0
T89	0	1	0	0
T159	0	2	0	0
T167	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	64	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T40	0	3	0	0
T41	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	2	0	0
T89	0	1	0	0
T159	0	2	0	0
T167	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	64	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T40	0	3	0	0
T41	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	2	0	0
T89	0	1	0	0
T159	0	2	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	64	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T40	0	3	0	0
T41	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	2	0	0
T89	0	1	0	0
T159	0	2	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	23514	0	0
T8	303659	3	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	193	0	0
T40	0	116	0	0
T41	0	46	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	3	0	0
T59	0	7	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	115	0	0
T89	0	101	0	0
T159	0	213	0	0
T167	0	45	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	6498	0	0
T1	8415	11	0	0
T5	423	2	0	0
T6	19504	14	0	0
T14	522	4	0	0
T15	502	5	0	0
T16	421	2	0	0
T18	0	5	0	0
T22	403	0	0	0
T23	427	2	0	0
T24	421	4	0	0
T25	491	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	28	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	2	0	0
T95	0	1	0	0
T154	0	1	0	0
T159	0	1	0	0
T181	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T22

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T22
1	1	Covered	T5,T6,T22

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T36,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T36,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T36,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T35,T44
1	0	Covered	T5,T6,T22
1	1	Covered	T8,T36,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T36,T43
0	1	Covered	T84,T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T36,T43
0	1	Covered	T8,T36,T43
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T36,T43
1	-	Covered	T8,T36,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T36,T43
DetectSt	168	Covered	T8,T36,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T36,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T36,T43
DebounceSt->IdleSt	163	Covered	T80,T122,T198
DetectSt->IdleSt	186	Covered	T84,T154
DetectSt->StableSt	191	Covered	T8,T36,T43
IdleSt->DebounceSt	148	Covered	T8,T36,T43
StableSt->IdleSt	206	Covered	T8,T36,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T36,T43
0	1	Covered	T8,T36,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T36,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T36,T43
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T22
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T36,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T122,T198
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T36,T43
DetectSt	-	-	-	-	1	-	-	Covered	T84,T154
DetectSt	-	-	-	-	0	1	-	Covered	T8,T36,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T36,T43
StableSt	-	-	-	-	-	-	0	Covered	T8,T36,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	144	0	0
CntIncr_A	6273387	73647	0	0
CntNoWrap_A	6273387	5593451	0	0
DetectStDropOut_A	6273387	2	0	0
DetectedOut_A	6273387	48875	0	0
DetectedPulseOut_A	6273387	68	0	0
DisabledIdleSt_A	6273387	5301934	0	0
DisabledNoDetection_A	6273387	5304212	0	0
EnterDebounceSt_A	6273387	74	0	0
EnterDetectSt_A	6273387	70	0	0
EnterStableSt_A	6273387	68	0	0
PulseIsPulse_A	6273387	68	0	0
StayInStableSt	6273387	48777	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	144	0	0
T8	303659	4	0	0
T9	713	0	0	0
T10	512	0	0	0
T36	0	4	0	0
T43	0	4	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T62	0	4	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	4	0	0
T80	0	7	0	0
T83	0	2	0	0
T146	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	73647	0	0
T8	303659	52	0	0
T9	713	0	0	0
T10	512	0	0	0
T36	0	26	0	0
T43	0	78	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T62	0	74	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	32	0	0
T80	0	292	0	0
T83	0	55	0	0
T146	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593451	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2	0	0
T84	1006	1	0	0
T154	0	1	0	0
T199	426	0	0	0
T200	522	0	0	0
T201	5367	0	0	0
T202	672	0	0	0
T203	1796	0	0	0
T204	508	0	0	0
T205	527	0	0	0
T206	420	0	0	0
T207	13414	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	48875	0	0
T8	303659	39	0	0
T9	713	0	0	0
T10	512	0	0	0
T36	0	73	0	0
T43	0	78	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	4	0	0
T59	0	7	0	0
T62	0	139	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	6	0	0
T80	0	330	0	0
T83	0	46	0	0
T146	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	68	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T36	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	3	0	0
T83	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5301934	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5304212	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	74	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T36	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	4	0	0
T83	0	1	0	0
T146	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	70	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T36	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	3	0	0
T83	0	1	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	68	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T36	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	3	0	0
T83	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	68	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T36	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	3	0	0
T83	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	48777	0	0
T8	303659	36	0	0
T9	713	0	0	0
T10	512	0	0	0
T36	0	71	0	0
T43	0	75	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	3	0	0
T59	0	6	0	0
T62	0	136	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	4	0	0
T80	0	327	0	0
T83	0	44	0	0
T146	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	36	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T36	0	2	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	3	0	0
T146	0	1	0	0
T148	0	1	0	0
T181	0	1	0	0
T208	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T22
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T11,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T11
1	0	Covered	T5,T6,T23
1	1	Covered	T9,T11,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T41
0	1	Covered	T122
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T41
0	1	Covered	T9,T11,T43
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T41
1	-	Covered	T9,T11,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T41
DetectSt	168	Covered	T9,T11,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T11,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T41
DebounceSt->IdleSt	163	Covered	T62,T95,T149
DetectSt->IdleSt	186	Covered	T122
DetectSt->StableSt	191	Covered	T9,T11,T41
IdleSt->DebounceSt	148	Covered	T9,T11,T41
StableSt->IdleSt	206	Covered	T9,T11,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T41
0	1	Covered	T9,T11,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T62,T95,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T41
DetectSt	-	-	-	-	1	-	-	Covered	T122
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T43
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	97	0	0
CntIncr_A	6273387	2381	0	0
CntNoWrap_A	6273387	5593498	0	0
DetectStDropOut_A	6273387	1	0	0
DetectedOut_A	6273387	3507	0	0
DetectedPulseOut_A	6273387	44	0	0
DisabledIdleSt_A	6273387	5573221	0	0
DisabledNoDetection_A	6273387	5575491	0	0
EnterDebounceSt_A	6273387	52	0	0
EnterDetectSt_A	6273387	45	0	0
EnterStableSt_A	6273387	44	0	0
PulseIsPulse_A	6273387	44	0	0
StayInStableSt	6273387	3442	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6273387	6128	0	0
gen_low_level_sva.LowLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	97	0	0
T9	713	4	0	0
T10	512	0	0	0
T11	4766	6	0	0
T12	669	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T146	0	2	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2381	0	0
T9	713	50	0	0
T10	512	0	0	0
T11	4766	126	0	0
T12	669	0	0	0
T41	0	19	0	0
T43	0	39	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T62	0	37	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	31	0	0
T146	0	13	0	0
T159	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593498	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1	0	0
T122	15871	1	0	0
T182	940	0	0	0
T209	424	0	0	0
T210	5716	0	0	0
T211	899	0	0	0
T212	421	0	0	0
T213	19032	0	0	0
T214	1011	0	0	0
T215	12291	0	0	0
T216	7117	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	3507	0	0
T9	713	200	0	0
T10	512	0	0	0
T11	4766	230	0	0
T12	669	0	0	0
T41	0	47	0	0
T43	0	82	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	4	0	0
T59	0	9	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	236	0	0
T89	0	27	0	0
T146	0	61	0	0
T159	0	95	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	44	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	4	0	0
T89	0	1	0	0
T146	0	1	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5573221	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5575491	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	52	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	1	0	0
T146	0	1	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	45	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	4	0	0
T89	0	1	0	0
T146	0	1	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	44	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	4	0	0
T89	0	1	0	0
T146	0	1	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	44	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	4	0	0
T89	0	1	0	0
T146	0	1	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	3442	0	0
T9	713	197	0	0
T10	512	0	0	0
T11	4766	226	0	0
T12	669	0	0	0
T41	0	45	0	0
T43	0	81	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	3	0	0
T59	0	8	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	230	0	0
T89	0	26	0	0
T146	0	59	0	0
T159	0	94	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	6128	0	0
T1	8415	13	0	0
T5	423	1	0	0
T6	19504	15	0	0
T14	522	4	0	0
T15	502	5	0	0
T16	421	4	0	0
T18	0	7	0	0
T20	0	6	0	0
T22	403	0	0	0
T23	427	4	0	0
T24	421	0	0	0
T25	491	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	21	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	4766	2	0	0
T12	669	0	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	2	0	0
T89	0	1	0	0
T154	0	1	0	0
T159	0	1	0	0
T181	0	1	0	0
T196	0	1	0	0
T208	0	1	0	0