Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T23
1	1	Covered	T5,T6,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T11,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T11,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T41
1	0	Covered	T5,T6,T23
1	1	Covered	T8,T11,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T36
0	1	Covered	T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T36
0	1	Covered	T8,T11,T39
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T36
1	-	Covered	T8,T11,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T36
DetectSt	168	Covered	T8,T11,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T11,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T36
DebounceSt->IdleSt	163	Covered	T11,T214,T217
DetectSt->IdleSt	186	Covered	T95
DetectSt->StableSt	191	Covered	T8,T11,T36
IdleSt->DebounceSt	148	Covered	T8,T11,T36
StableSt->IdleSt	206	Covered	T8,T11,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T36
0	1	Covered	T8,T11,T36
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T23
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T214,T217
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T36
DetectSt	-	-	-	-	1	-	-	Covered	T95
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T39
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	151	0	0
CntIncr_A	6273387	3925	0	0
CntNoWrap_A	6273387	5593444	0	0
DetectStDropOut_A	6273387	1	0	0
DetectedOut_A	6273387	6082	0	0
DetectedPulseOut_A	6273387	71	0	0
DisabledIdleSt_A	6273387	5574634	0	0
DisabledNoDetection_A	6273387	5576911	0	0
EnterDebounceSt_A	6273387	79	0	0
EnterDetectSt_A	6273387	72	0	0
EnterStableSt_A	6273387	71	0	0
PulseIsPulse_A	6273387	71	0	0
StayInStableSt	6273387	5986	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	44	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	151	0	0
T8	303659	4	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	11	0	0
T36	0	2	0	0
T39	0	4	0	0
T43	0	4	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T62	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	4	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	3925	0	0
T8	303659	52	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	374	0	0
T36	0	78	0	0
T39	0	168	0	0
T43	0	78	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T62	0	37	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	62	0	0
T171	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593444	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1	0	0
T95	32522	1	0	0
T218	19100	0	0	0
T219	15410	0	0	0
T220	507	0	0	0
T221	505	0	0	0
T222	521	0	0	0
T223	632	0	0	0
T224	1977	0	0	0
T225	495	0	0	0
T226	118235	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	6082	0	0
T8	303659	233	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	339	0	0
T36	0	245	0	0
T39	0	82	0	0
T43	0	159	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	4	0	0
T59	0	7	0	0
T62	0	21	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	84	0	0
T171	0	118	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	71	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	5	0	0
T36	0	1	0	0
T39	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5574634	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5576911	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	79	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	6	0	0
T36	0	1	0	0
T39	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	72	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	5	0	0
T36	0	1	0	0
T39	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	71	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	5	0	0
T36	0	1	0	0
T39	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	71	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	5	0	0
T36	0	1	0	0
T39	0	2	0	0
T43	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5986	0	0
T8	303659	231	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	332	0	0
T36	0	243	0	0
T39	0	79	0	0
T43	0	156	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	3	0	0
T59	0	6	0	0
T62	0	20	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	82	0	0
T171	0	117	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	44	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	3	0	0
T39	0	1	0	0
T43	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T80	0	1	0	0
T89	0	2	0	0
T106	0	1	0	0
T167	0	2	0	0
T171	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T11
1	0	Covered	T5,T6,T23
1	1	Covered	T8,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Covered	T155
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Covered	T9,T11,T39
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T11
1	-	Covered	T9,T11,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T11
DetectSt	168	Covered	T8,T9,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T11
DebounceSt->IdleSt	163	Covered	T148,T151
DetectSt->IdleSt	186	Covered	T155
DetectSt->StableSt	191	Covered	T8,T9,T11
IdleSt->DebounceSt	148	Covered	T8,T9,T11
StableSt->IdleSt	206	Covered	T8,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T11
0	1	Covered	T8,T9,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T148,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T155
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T39
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	88	0	0
CntIncr_A	6273387	37093	0	0
CntNoWrap_A	6273387	5593507	0	0
DetectStDropOut_A	6273387	1	0	0
DetectedOut_A	6273387	26810	0	0
DetectedPulseOut_A	6273387	42	0	0
DisabledIdleSt_A	6273387	5302463	0	0
DisabledNoDetection_A	6273387	5304743	0	0
EnterDebounceSt_A	6273387	45	0	0
EnterDetectSt_A	6273387	43	0	0
EnterStableSt_A	6273387	42	0	0
PulseIsPulse_A	6273387	42	0	0
StayInStableSt	6273387	26748	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6273387	6046	0	0
gen_low_level_sva.LowLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	88	0	0
T8	303659	4	0	0
T9	713	4	0	0
T10	512	0	0	0
T11	0	4	0	0
T39	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	4	0	0
T146	0	2	0	0
T167	0	4	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	37093	0	0
T8	303659	52	0	0
T9	713	50	0	0
T10	512	0	0	0
T11	0	108	0	0
T39	0	84	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	62	0	0
T146	0	13	0	0
T167	0	74	0	0
T171	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593507	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1	0	0
T155	612	1	0	0
T227	758	0	0	0
T228	522	0	0	0
T229	19048	0	0	0
T230	26588	0	0	0
T231	402	0	0	0
T232	708	0	0	0
T233	479	0	0	0
T234	527	0	0	0
T235	499	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	26810	0	0
T8	303659	76	0	0
T9	713	29	0	0
T10	512	0	0	0
T11	0	161	0	0
T39	0	36	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	3	0	0
T59	0	9	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	122	0	0
T146	0	116	0	0
T167	0	218	0	0
T171	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	42	0	0
T8	303659	2	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	0	2	0	0
T39	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T146	0	1	0	0
T167	0	2	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5302463	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5304743	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	45	0	0
T8	303659	2	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	0	2	0	0
T39	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T146	0	1	0	0
T167	0	2	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	43	0	0
T8	303659	2	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	0	2	0	0
T39	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T146	0	1	0	0
T167	0	2	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	42	0	0
T8	303659	2	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	0	2	0	0
T39	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T146	0	1	0	0
T167	0	2	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	42	0	0
T8	303659	2	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	0	2	0	0
T39	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	2	0	0
T146	0	1	0	0
T167	0	2	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	26748	0	0
T8	303659	72	0	0
T9	713	27	0	0
T10	512	0	0	0
T11	0	158	0	0
T39	0	35	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	8	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	119	0	0
T146	0	114	0	0
T167	0	215	0	0
T171	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	6046	0	0
T1	8415	9	0	0
T5	423	2	0	0
T6	19504	12	0	0
T14	522	4	0	0
T15	502	5	0	0
T16	421	3	0	0
T18	0	5	0	0
T22	403	0	0	0
T23	427	4	0	0
T24	421	2	0	0
T25	491	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	20	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	4766	1	0	0
T12	669	0	0	0
T39	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	1	0	0
T148	0	1	0	0
T167	0	1	0	0
T170	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T208	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T23
1	1	Covered	T5,T6,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T39,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T36,T39,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T39,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T35,T36
1	0	Covered	T5,T6,T23
1	1	Covered	T36,T39,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T39,T42
0	1	Covered	T236
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T39,T42
0	1	Covered	T36,T39,T42
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T39,T42
1	-	Covered	T36,T39,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T39,T42
DetectSt	168	Covered	T36,T39,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T36,T39,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T39,T42
DebounceSt->IdleSt	163	Covered	T122,T214,T153
DetectSt->IdleSt	186	Covered	T236
DetectSt->StableSt	191	Covered	T36,T39,T42
IdleSt->DebounceSt	148	Covered	T36,T39,T42
StableSt->IdleSt	206	Covered	T36,T39,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T39,T42
0	1	Covered	T36,T39,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T39,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T39,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T23
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T39,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T122,T214,T153
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T39,T42
DetectSt	-	-	-	-	1	-	-	Covered	T236
DetectSt	-	-	-	-	0	1	-	Covered	T36,T39,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T39,T42
StableSt	-	-	-	-	-	-	0	Covered	T36,T39,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	124	0	0
CntIncr_A	6273387	108065	0	0
CntNoWrap_A	6273387	5593471	0	0
DetectStDropOut_A	6273387	1	0	0
DetectedOut_A	6273387	21614	0	0
DetectedPulseOut_A	6273387	59	0	0
DisabledIdleSt_A	6273387	5304334	0	0
DisabledNoDetection_A	6273387	5306619	0	0
EnterDebounceSt_A	6273387	64	0	0
EnterDetectSt_A	6273387	60	0	0
EnterStableSt_A	6273387	59	0	0
PulseIsPulse_A	6273387	59	0	0
StayInStableSt	6273387	21531	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	124	0	0
T36	14253	6	0	0
T37	32959	0	0	0
T39	884	2	0	0
T42	0	2	0	0
T45	11084	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T60	1169	0	0	0
T80	0	8	0	0
T89	0	4	0	0
T104	0	2	0	0
T129	0	4	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T159	0	4	0	0
T237	521	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	108065	0	0
T36	14253	39	0	0
T37	32959	0	0	0
T39	884	84	0	0
T42	0	62	0	0
T45	11084	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T60	1169	0	0	0
T80	0	248	0	0
T89	0	62	0	0
T104	0	31	0	0
T129	0	200	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T159	0	64	0	0
T237	521	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593471	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1	0	0
T217	1055	0	0	0
T236	862	1	0	0
T238	402	0	0	0
T239	4366	0	0	0
T240	1014	0	0	0
T241	502	0	0	0
T242	26504	0	0	0
T243	422	0	0	0
T244	832	0	0	0
T245	20759	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	21614	0	0
T36	14253	129	0	0
T37	32959	0	0	0
T39	884	161	0	0
T42	0	223	0	0
T45	11084	0	0	0
T58	0	4	0	0
T59	0	8	0	0
T60	1169	0	0	0
T80	0	423	0	0
T89	0	187	0	0
T104	0	80	0	0
T129	0	117	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T159	0	65	0	0
T237	521	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	59	0	0
T36	14253	3	0	0
T37	32959	0	0	0
T39	884	1	0	0
T42	0	1	0	0
T45	11084	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1169	0	0	0
T80	0	4	0	0
T89	0	2	0	0
T104	0	1	0	0
T129	0	2	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T159	0	2	0	0
T237	521	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5304334	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5306619	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	64	0	0
T36	14253	3	0	0
T37	32959	0	0	0
T39	884	1	0	0
T42	0	1	0	0
T45	11084	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1169	0	0	0
T80	0	4	0	0
T89	0	2	0	0
T104	0	1	0	0
T129	0	2	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T159	0	2	0	0
T237	521	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	60	0	0
T36	14253	3	0	0
T37	32959	0	0	0
T39	884	1	0	0
T42	0	1	0	0
T45	11084	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1169	0	0	0
T80	0	4	0	0
T89	0	2	0	0
T104	0	1	0	0
T129	0	2	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T159	0	2	0	0
T237	521	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	59	0	0
T36	14253	3	0	0
T37	32959	0	0	0
T39	884	1	0	0
T42	0	1	0	0
T45	11084	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1169	0	0	0
T80	0	4	0	0
T89	0	2	0	0
T104	0	1	0	0
T129	0	2	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T159	0	2	0	0
T237	521	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	59	0	0
T36	14253	3	0	0
T37	32959	0	0	0
T39	884	1	0	0
T42	0	1	0	0
T45	11084	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1169	0	0	0
T80	0	4	0	0
T89	0	2	0	0
T104	0	1	0	0
T129	0	2	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T159	0	2	0	0
T237	521	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	21531	0	0
T36	14253	125	0	0
T37	32959	0	0	0
T39	884	160	0	0
T42	0	222	0	0
T45	11084	0	0	0
T58	0	3	0	0
T59	0	7	0	0
T60	1169	0	0	0
T80	0	418	0	0
T89	0	185	0	0
T104	0	78	0	0
T129	0	114	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T159	0	62	0	0
T237	521	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	33	0	0
T36	14253	2	0	0
T37	32959	0	0	0
T39	884	1	0	0
T42	0	1	0	0
T45	11084	0	0	0
T60	1169	0	0	0
T80	0	3	0	0
T89	0	2	0	0
T129	0	1	0	0
T137	422	0	0	0
T138	502	0	0	0
T139	420	0	0	0
T140	431	0	0	0
T148	0	1	0	0
T159	0	1	0	0
T181	0	2	0	0
T188	0	2	0	0
T237	521	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T44
1	0	Covered	T5,T6,T23
1	1	Covered	T8,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T39,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T39,T40
0	1	Covered	T8,T40,T89
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T39,T40
1	-	Covered	T8,T40,T89

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T39,T40
DetectSt	168	Covered	T8,T39,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T39,T40
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T39,T40
IdleSt->DebounceSt	148	Covered	T8,T39,T40
StableSt->IdleSt	206	Covered	T8,T40,T62

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T39,T40
0	1	Covered	T8,T39,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T39,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T39,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T39,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T40,T58
StableSt	-	-	-	-	-	-	0	Covered	T8,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	92	0	0
CntIncr_A	6273387	168232	0	0
CntNoWrap_A	6273387	5593503	0	0
DetectStDropOut_A	6273387	0	0	0
DetectedOut_A	6273387	126005	0	0
DetectedPulseOut_A	6273387	46	0	0
DisabledIdleSt_A	6273387	5018083	0	0
DisabledNoDetection_A	6273387	5020360	0	0
EnterDebounceSt_A	6273387	46	0	0
EnterDetectSt_A	6273387	46	0	0
EnterStableSt_A	6273387	46	0	0
PulseIsPulse_A	6273387	46	0	0
StayInStableSt	6273387	125942	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6273387	6162	0	0
gen_low_level_sva.LowLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	92	0	0
T8	303659	4	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T62	0	2	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	4	0	0
T80	0	4	0	0
T89	0	4	0	0
T167	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	168232	0	0
T8	303659	95956	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	84	0	0
T40	0	164	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T62	0	37	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	32	0	0
T80	0	102	0	0
T89	0	62	0	0
T167	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593503	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	126005	0	0
T8	303659	44250	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	42	0	0
T40	0	138	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	3	0	0
T59	0	7	0	0
T62	0	39	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	103	0	0
T80	0	83	0	0
T89	0	65	0	0
T167	0	114	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	46	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	2	0	0
T89	0	2	0	0
T167	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5018083	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5020360	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	46	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	2	0	0
T89	0	2	0	0
T167	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	46	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	2	0	0
T89	0	2	0	0
T167	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	46	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	2	0	0
T89	0	2	0	0
T167	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	46	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	2	0	0
T89	0	2	0	0
T167	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	125942	0	0
T8	303659	44248	0	0
T9	713	0	0	0
T10	512	0	0	0
T39	0	40	0	0
T40	0	135	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	2	0	0
T59	0	6	0	0
T62	0	37	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	101	0	0
T80	0	81	0	0
T89	0	62	0	0
T167	0	111	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	6162	0	0
T1	8415	14	0	0
T5	423	3	0	0
T6	19504	11	0	0
T14	522	4	0	0
T15	502	4	0	0
T16	421	2	0	0
T18	0	6	0	0
T22	403	0	0	0
T23	427	2	0	0
T24	421	1	0	0
T25	491	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	27	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T40	0	1	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	2	0	0
T80	0	2	0	0
T89	0	1	0	0
T129	0	1	0	0
T148	0	1	0	0
T167	0	1	0	0
T181	0	2	0	0
T188	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T8,T78,T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T11
1	-	Covered	T3,T8,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T11
DetectSt	168	Covered	T3,T8,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T11
DebounceSt->IdleSt	163	Covered	T8,T122,T195
DetectSt->IdleSt	186	Covered	T8,T78,T151
DetectSt->StableSt	191	Covered	T3,T8,T11
IdleSt->DebounceSt	148	Covered	T3,T8,T11
StableSt->IdleSt	206	Covered	T3,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T122,T195
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T8,T78,T151
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	149	0	0
CntIncr_A	6273387	181971	0	0
CntNoWrap_A	6273387	5593446	0	0
DetectStDropOut_A	6273387	4	0	0
DetectedOut_A	6273387	123229	0	0
DetectedPulseOut_A	6273387	68	0	0
DisabledIdleSt_A	6273387	5019020	0	0
DisabledNoDetection_A	6273387	5021291	0	0
EnterDebounceSt_A	6273387	77	0	0
EnterDetectSt_A	6273387	72	0	0
EnterStableSt_A	6273387	68	0	0
PulseIsPulse_A	6273387	68	0	0
StayInStableSt	6273387	123131	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	149	0	0
T3	9905	2	0	0
T7	12899	0	0	0
T8	303659	11	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	4	0	0
T36	0	8	0	0
T42	0	2	0	0
T44	0	4	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T62	0	2	0	0
T63	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	181971	0	0
T3	9905	41	0	0
T7	12899	0	0	0
T8	303659	144006	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	194	0	0
T36	0	182	0	0
T42	0	62	0	0
T44	0	146	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T62	0	37	0	0
T63	0	11	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593446	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	4	0	0
T8	303659	1	0	0
T9	713	0	0	0
T10	512	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	1	0	0
T151	0	1	0	0
T246	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	123229	0	0
T3	9905	18	0	0
T7	12899	0	0	0
T8	303659	64129	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	421	0	0
T36	0	197	0	0
T42	0	44	0	0
T44	0	202	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	4	0	0
T59	0	8	0	0
T62	0	155	0	0
T63	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	68	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	4	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T36	0	4	0	0
T42	0	1	0	0
T44	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5019020	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5021291	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	77	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	6	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T36	0	4	0	0
T42	0	1	0	0
T44	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	72	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	5	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T36	0	4	0	0
T42	0	1	0	0
T44	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	68	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	4	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T36	0	4	0	0
T42	0	1	0	0
T44	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	68	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	4	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	2	0	0
T36	0	4	0	0
T42	0	1	0	0
T44	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	123131	0	0
T3	9905	17	0	0
T7	12899	0	0	0
T8	303659	64123	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	418	0	0
T36	0	191	0	0
T42	0	43	0	0
T44	0	199	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	3	0	0
T59	0	7	0	0
T62	0	153	0	0
T63	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	35	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	2	0	0
T9	713	0	0	0
T10	512	0	0	0
T11	0	1	0	0
T36	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T146	0	1	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T9,T11,T89
1	0	Covered	T58,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T9
1	-	Covered	T9,T11,T89

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T9
DetectSt	168	Covered	T3,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T9
DebounceSt->IdleSt	163	Covered	T148,T95,T240
DetectSt->IdleSt	186	Covered	T80
DetectSt->StableSt	191	Covered	T3,T8,T9
IdleSt->DebounceSt	148	Covered	T3,T8,T9
StableSt->IdleSt	206	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T148,T95,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T80
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T58
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	103	0	0
CntIncr_A	6273387	37620	0	0
CntNoWrap_A	6273387	5593492	0	0
DetectStDropOut_A	6273387	1	0	0
DetectedOut_A	6273387	97840	0	0
DetectedPulseOut_A	6273387	49	0	0
DisabledIdleSt_A	6273387	5303602	0	0
DisabledNoDetection_A	6273387	5305875	0	0
EnterDebounceSt_A	6273387	53	0	0
EnterDetectSt_A	6273387	50	0	0
EnterStableSt_A	6273387	49	0	0
PulseIsPulse_A	6273387	49	0	0
StayInStableSt	6273387	97762	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6273387	6780	0	0
gen_low_level_sva.LowLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	103	0	0
T3	9905	2	0	0
T7	12899	0	0	0
T8	303659	2	0	0
T9	713	2	0	0
T10	512	0	0	0
T11	0	8	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	2	0	0
T59	0	2	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	37620	0	0
T3	9905	41	0	0
T7	12899	0	0	0
T8	303659	32	0	0
T9	713	25	0	0
T10	512	0	0	0
T11	0	205	0	0
T39	0	84	0	0
T41	0	19	0	0
T42	0	62	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	20	0	0
T59	0	28	0	0
T159	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5593492	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1	0	0
T80	23083	1	0	0
T92	11482	0	0	0
T127	12446	0	0	0
T128	502	0	0	0
T129	999	0	0	0
T130	4516	0	0	0
T131	431	0	0	0
T132	4720	0	0	0
T133	506	0	0	0
T134	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	97840	0	0
T3	9905	196	0	0
T7	12899	0	0	0
T8	303659	76	0	0
T9	713	85	0	0
T10	512	0	0	0
T11	0	163	0	0
T39	0	42	0	0
T41	0	38	0	0
T42	0	221	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	4	0	0
T59	0	9	0	0
T159	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	49	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	1	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	0	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5303602	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5305875	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	53	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	1	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	0	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	50	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	1	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	0	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	49	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	1	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	0	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	49	0	0
T3	9905	1	0	0
T7	12899	0	0	0
T8	303659	1	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	0	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	97762	0	0
T3	9905	194	0	0
T7	12899	0	0	0
T8	303659	74	0	0
T9	713	84	0	0
T10	512	0	0	0
T11	0	158	0	0
T39	0	40	0	0
T41	0	36	0	0
T42	0	219	0	0
T48	15575	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T58	0	3	0	0
T59	0	8	0	0
T159	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	6780	0	0
T1	8415	14	0	0
T4	639	3	0	0
T5	423	3	0	0
T6	19504	13	0	0
T14	522	4	0	0
T15	502	6	0	0
T16	0	2	0	0
T22	403	0	0	0
T23	427	3	0	0
T24	421	3	0	0
T25	491	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	18	0	0
T9	713	1	0	0
T10	512	0	0	0
T11	4766	3	0	0
T12	669	0	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T70	570	0	0	0
T76	406	0	0	0
T89	0	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T170	0	1	0	0
T183	0	1	0	0
T214	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0