Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T31,T32
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T31,T32
1	0	Covered	T7,T45,T38
1	1	Covered	T7,T10,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T31
0	1	Covered	T31,T32,T45
1	0	Covered	T45,T58,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T38
0	1	Covered	T7,T38,T46
1	0	Covered	T58,T249

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T38
1	-	Covered	T7,T38,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T31
DetectSt	168	Covered	T7,T10,T31
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T10,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T31
DebounceSt->IdleSt	163	Covered	T69,T58,T59
DetectSt->IdleSt	186	Covered	T31,T32,T45
DetectSt->StableSt	191	Covered	T7,T10,T38
IdleSt->DebounceSt	148	Covered	T7,T10,T31
StableSt->IdleSt	206	Covered	T7,T38,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T10,T31
0	1	Covered	T7,T10,T31
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T31
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T31
IdleSt	0	-	-	-	-	-	-	Covered	T7,T31,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T58,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T31
DetectSt	-	-	-	-	1	-	-	Covered	T31,T32,T45
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T38
DetectSt	-	-	-	-	0	0	-	Covered	T7,T10,T31
StableSt	-	-	-	-	-	-	1	Covered	T7,T38,T46
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	2967	0	0
CntIncr_A	6273387	102524	0	0
CntNoWrap_A	6273387	5590628	0	0
DetectStDropOut_A	6273387	394	0	0
DetectedOut_A	6273387	78575	0	0
DetectedPulseOut_A	6273387	904	0	0
DisabledIdleSt_A	6273387	5179582	0	0
DisabledNoDetection_A	6273387	5181701	0	0
EnterDebounceSt_A	6273387	1498	0	0
EnterDetectSt_A	6273387	1470	0	0
EnterStableSt_A	6273387	904	0	0
PulseIsPulse_A	6273387	904	0	0
StayInStableSt	6273387	77547	0	0
gen_high_event_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	767	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2967	0	0
T7	12899	34	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	2	0	0
T31	0	48	0	0
T32	0	24	0	0
T38	0	8	0	0
T45	0	14	0	0
T46	0	30	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	58	0	0
T68	0	14	0	0
T69	0	14	0	0
T70	570	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	102524	0	0
T7	12899	1207	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	21	0	0
T31	0	1250	0	0
T32	0	653	0	0
T38	0	252	0	0
T45	0	415	0	0
T46	0	1005	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	1769	0	0
T68	0	199	0	0
T69	0	1833	0	0
T70	570	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5590628	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	394	0	0
T31	5219	24	0	0
T32	5367	12	0	0
T36	14253	0	0	0
T39	884	0	0	0
T45	0	3	0	0
T52	598	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1169	0	0	0
T61	648	0	0	0
T68	0	7	0	0
T69	0	2	0	0
T90	0	11	0	0
T130	0	25	0	0
T191	0	31	0	0
T237	521	0	0	0
T250	437	0	0	0
T251	411	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	78575	0	0
T7	12899	785	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	87	0	0
T38	0	128	0	0
T46	0	1754	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	322	0	0
T59	0	458	0	0
T67	0	1967	0	0
T70	570	0	0	0
T71	0	1209	0	0
T252	0	91	0	0
T253	0	1445	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	904	0	0
T7	12899	17	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	1	0	0
T38	0	4	0	0
T46	0	15	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T67	0	29	0	0
T70	570	0	0	0
T71	0	29	0	0
T252	0	1	0	0
T253	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5179582	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5181701	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1498	0	0
T7	12899	17	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	1	0	0
T31	0	24	0	0
T32	0	12	0	0
T38	0	4	0	0
T45	0	7	0	0
T46	0	15	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	29	0	0
T68	0	7	0	0
T69	0	12	0	0
T70	570	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1470	0	0
T7	12899	17	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	1	0	0
T31	0	24	0	0
T32	0	12	0	0
T38	0	4	0	0
T45	0	7	0	0
T46	0	15	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	29	0	0
T68	0	7	0	0
T69	0	2	0	0
T70	570	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	904	0	0
T7	12899	17	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	1	0	0
T38	0	4	0	0
T46	0	15	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T67	0	29	0	0
T70	570	0	0	0
T71	0	29	0	0
T252	0	1	0	0
T253	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	904	0	0
T7	12899	17	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	1	0	0
T38	0	4	0	0
T46	0	15	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T67	0	29	0	0
T70	570	0	0	0
T71	0	29	0	0
T252	0	1	0	0
T253	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	77547	0	0
T7	12899	766	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	85	0	0
T38	0	124	0	0
T46	0	1738	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	317	0	0
T59	0	453	0	0
T67	0	1935	0	0
T70	570	0	0	0
T71	0	1179	0	0
T252	0	89	0	0
T253	0	1419	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	767	0	0
T7	12899	15	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	4	0	0
T46	0	14	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	4	0	0
T59	0	5	0	0
T67	0	26	0	0
T70	570	0	0	0
T71	0	28	0	0
T253	0	22	0	0
T254	0	6	0	0
T255	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T6,T1,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T49,T88,T58
1	0	Covered	T58,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T1,T2
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T1,T2
1	-	Covered	T6,T1,T2

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T1,T2
DetectSt	168	Covered	T6,T1,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T6,T1,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T1,T2
DebounceSt->IdleSt	163	Covered	T6,T1,T48
DetectSt->IdleSt	186	Covered	T49,T88,T58
DetectSt->StableSt	191	Covered	T6,T1,T2
IdleSt->DebounceSt	148	Covered	T6,T1,T2
StableSt->IdleSt	206	Covered	T6,T1,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T1,T2
0	1	Covered	T6,T1,T2
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T1,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T1,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T1,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T1,T2
DetectSt	-	-	-	-	1	-	-	Covered	T49,T88,T58
DetectSt	-	-	-	-	0	1	-	Covered	T6,T1,T2
DetectSt	-	-	-	-	0	0	-	Covered	T6,T1,T2
StableSt	-	-	-	-	-	-	1	Covered	T6,T1,T2
StableSt	-	-	-	-	-	-	0	Covered	T6,T1,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	965	0	0
CntIncr_A	6273387	49955	0	0
CntNoWrap_A	6273387	5592630	0	0
DetectStDropOut_A	6273387	95	0	0
DetectedOut_A	6273387	13266	0	0
DetectedPulseOut_A	6273387	341	0	0
DisabledIdleSt_A	6273387	5239183	0	0
DisabledNoDetection_A	6273387	5240852	0	0
EnterDebounceSt_A	6273387	527	0	0
EnterDetectSt_A	6273387	441	0	0
EnterStableSt_A	6273387	341	0	0
PulseIsPulse_A	6273387	341	0	0
StayInStableSt	6273387	12886	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	300	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	965	0	0
T1	8415	3	0	0
T2	0	10	0	0
T3	0	2	0	0
T6	19504	15	0	0
T7	0	4	0	0
T10	0	2	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	3	0	0
T48	0	12	0	0
T49	0	2	0	0
T50	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	49955	0	0
T1	8415	156	0	0
T2	0	650	0	0
T3	0	25	0	0
T6	19504	598	0	0
T7	0	134	0	0
T10	0	25	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	45	0	0
T48	0	538	0	0
T49	0	109	0	0
T50	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5592630	0	0
T1	8415	8009	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19074	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	95	0	0
T10	512	0	0	0
T11	4766	0	0	0
T12	669	0	0	0
T13	294246	0	0	0
T49	7347	1	0	0
T50	6532	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T70	570	0	0	0
T76	406	0	0	0
T78	0	6	0	0
T88	0	10	0	0
T89	0	3	0	0
T91	0	8	0	0
T92	0	1	0	0
T93	0	7	0	0
T94	0	5	0	0
T95	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	13266	0	0
T1	8415	11	0	0
T2	0	306	0	0
T3	0	4	0	0
T6	19504	30	0	0
T7	0	89	0	0
T10	0	3	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	3	0	0
T36	0	49	0	0
T37	0	117	0	0
T48	0	27	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	341	0	0
T1	8415	1	0	0
T2	0	5	0	0
T3	0	1	0	0
T6	19504	7	0	0
T7	0	2	0	0
T10	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	7	0	0
T48	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5239183	0	0
T1	8415	4029	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	16114	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5240852	0	0
T1	8415	4029	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	16114	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	527	0	0
T1	8415	2	0	0
T2	0	5	0	0
T3	0	1	0	0
T6	19504	8	0	0
T7	0	2	0	0
T10	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	2	0	0
T48	0	7	0	0
T49	0	1	0	0
T50	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	441	0	0
T1	8415	1	0	0
T2	0	5	0	0
T3	0	1	0	0
T6	19504	7	0	0
T7	0	2	0	0
T10	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T48	0	5	0	0
T49	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	341	0	0
T1	8415	1	0	0
T2	0	5	0	0
T3	0	1	0	0
T6	19504	7	0	0
T7	0	2	0	0
T10	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	7	0	0
T48	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	341	0	0
T1	8415	1	0	0
T2	0	5	0	0
T3	0	1	0	0
T6	19504	7	0	0
T7	0	2	0	0
T10	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	7	0	0
T48	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	12886	0	0
T1	8415	10	0	0
T2	0	301	0	0
T3	0	3	0	0
T6	19504	23	0	0
T7	0	86	0	0
T10	0	2	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	2	0	0
T36	0	48	0	0
T37	0	110	0	0
T48	0	22	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	300	0	0
T1	8415	1	0	0
T2	0	5	0	0
T3	0	1	0	0
T6	19504	7	0	0
T7	0	1	0	0
T10	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	7	0	0
T48	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T31,T32
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T31,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T31,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T31,T32
1	0	Covered	T7,T45,T38
1	1	Covered	T7,T31,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T32
0	1	Covered	T31,T32,T68
1	0	Covered	T67,T58,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T38
0	1	Covered	T7,T45,T38
1	0	Covered	T81,T82

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T45,T38
1	-	Covered	T7,T45,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T31,T32
DetectSt	168	Covered	T7,T31,T32
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T45,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T31,T32
DebounceSt->IdleSt	163	Covered	T69,T58,T59
DetectSt->IdleSt	186	Covered	T31,T32,T67
DetectSt->StableSt	191	Covered	T7,T45,T38
IdleSt->DebounceSt	148	Covered	T7,T31,T32
StableSt->IdleSt	206	Covered	T7,T45,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T31,T32
0	1	Covered	T7,T31,T32
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T31,T32
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T31,T32
IdleSt	0	-	-	-	-	-	-	Covered	T7,T31,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T58,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T31,T32
DetectSt	-	-	-	-	1	-	-	Covered	T31,T32,T67
DetectSt	-	-	-	-	0	1	-	Covered	T7,T45,T38
DetectSt	-	-	-	-	0	0	-	Covered	T7,T31,T32
StableSt	-	-	-	-	-	-	1	Covered	T7,T45,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T45,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	2857	0	0
CntIncr_A	6273387	91204	0	0
CntNoWrap_A	6273387	5590738	0	0
DetectStDropOut_A	6273387	402	0	0
DetectedOut_A	6273387	66681	0	0
DetectedPulseOut_A	6273387	873	0	0
DisabledIdleSt_A	6273387	5187938	0	0
DisabledNoDetection_A	6273387	5190084	0	0
EnterDebounceSt_A	6273387	1442	0	0
EnterDetectSt_A	6273387	1416	0	0
EnterStableSt_A	6273387	873	0	0
PulseIsPulse_A	6273387	873	0	0
StayInStableSt	6273387	65711	0	0
gen_high_event_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	761	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2857	0	0
T7	12899	50	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	46	0	0
T32	0	24	0	0
T38	0	4	0	0
T45	0	12	0	0
T46	0	38	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	16	0	0
T67	0	42	0	0
T68	0	24	0	0
T69	0	5	0	0
T70	570	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	91204	0	0
T7	12899	1750	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	1190	0	0
T32	0	655	0	0
T38	0	128	0	0
T45	0	240	0	0
T46	0	1596	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	294	0	0
T67	0	1463	0	0
T68	0	342	0	0
T69	0	867	0	0
T70	570	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5590738	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	402	0	0
T31	5219	23	0	0
T32	5367	12	0	0
T36	14253	0	0	0
T39	884	0	0	0
T52	598	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1169	0	0	0
T61	648	0	0	0
T68	0	12	0	0
T90	0	28	0	0
T130	0	6	0	0
T191	0	10	0	0
T237	521	0	0	0
T250	437	0	0	0
T251	411	0	0	0
T256	0	12	0	0
T257	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	66681	0	0
T7	12899	1873	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	62	0	0
T45	0	128	0	0
T46	0	1673	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	280	0	0
T59	0	425	0	0
T70	570	0	0	0
T253	0	1377	0	0
T254	0	1757	0	0
T255	0	2573	0	0
T258	0	1618	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	873	0	0
T7	12899	25	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	2	0	0
T45	0	6	0	0
T46	0	19	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T70	570	0	0	0
T253	0	21	0	0
T254	0	13	0	0
T255	0	23	0	0
T258	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5187938	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5190084	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1442	0	0
T7	12899	25	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	23	0	0
T32	0	12	0	0
T38	0	2	0	0
T45	0	6	0	0
T46	0	19	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	9	0	0
T67	0	21	0	0
T68	0	12	0	0
T69	0	6	0	0
T70	570	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1416	0	0
T7	12899	25	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	23	0	0
T32	0	12	0	0
T38	0	2	0	0
T45	0	6	0	0
T46	0	19	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	7	0	0
T59	0	7	0	0
T67	0	21	0	0
T68	0	12	0	0
T70	570	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	873	0	0
T7	12899	25	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	2	0	0
T45	0	6	0	0
T46	0	19	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T70	570	0	0	0
T253	0	21	0	0
T254	0	13	0	0
T255	0	23	0	0
T258	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	873	0	0
T7	12899	25	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	2	0	0
T45	0	6	0	0
T46	0	19	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T70	570	0	0	0
T253	0	21	0	0
T254	0	13	0	0
T255	0	23	0	0
T258	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	65711	0	0
T7	12899	1847	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	60	0	0
T45	0	122	0	0
T46	0	1654	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	275	0	0
T59	0	420	0	0
T70	570	0	0	0
T253	0	1352	0	0
T254	0	1737	0	0
T255	0	2540	0	0
T258	0	1609	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	761	0	0
T7	12899	24	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	2	0	0
T45	0	6	0	0
T46	0	19	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T70	570	0	0	0
T253	0	17	0	0
T254	0	6	0	0
T255	0	13	0	0
T258	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T6,T1,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T259,T80
1	0	Covered	T58,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T48
0	1	Covered	T1,T2,T48
1	0	Covered	T59,T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T48
1	-	Covered	T1,T2,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T1,T2
DetectSt	168	Covered	T6,T1,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T1,T2
DebounceSt->IdleSt	163	Covered	T1,T2,T48
DetectSt->IdleSt	186	Covered	T6,T259,T58
DetectSt->StableSt	191	Covered	T1,T2,T48
IdleSt->DebounceSt	148	Covered	T6,T1,T2
StableSt->IdleSt	206	Covered	T1,T2,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T1,T2
0	1	Covered	T6,T1,T2
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T1,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T1,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T1,T2
DetectSt	-	-	-	-	1	-	-	Covered	T6,T259,T58
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T48
DetectSt	-	-	-	-	0	0	-	Covered	T6,T1,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T48
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	896	0	0
CntIncr_A	6273387	49646	0	0
CntNoWrap_A	6273387	5592699	0	0
DetectStDropOut_A	6273387	66	0	0
DetectedOut_A	6273387	14286	0	0
DetectedPulseOut_A	6273387	356	0	0
DisabledIdleSt_A	6273387	5259837	0	0
DisabledNoDetection_A	6273387	5261607	0	0
EnterDebounceSt_A	6273387	470	0	0
EnterDetectSt_A	6273387	428	0	0
EnterStableSt_A	6273387	356	0	0
PulseIsPulse_A	6273387	356	0	0
StayInStableSt	6273387	13895	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	317	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	896	0	0
T1	8415	27	0	0
T2	0	18	0	0
T6	19504	10	0	0
T7	0	10	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T37	0	15	0	0
T48	0	3	0	0
T49	0	2	0	0
T88	0	13	0	0
T260	0	2	0	0
T261	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	49646	0	0
T1	8415	1072	0	0
T2	0	1316	0	0
T6	19504	433	0	0
T7	0	385	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T37	0	632	0	0
T48	0	78	0	0
T49	0	105	0	0
T88	0	525	0	0
T260	0	73	0	0
T261	0	761	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5592699	0	0
T1	8415	7985	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19079	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	66	0	0
T1	8415	0	0	0
T6	19504	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T80	0	1	0	0
T93	0	2	0	0
T127	0	11	0	0
T156	0	12	0	0
T161	0	1	0	0
T259	0	9	0	0
T262	0	10	0	0
T263	0	2	0	0
T264	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	14286	0	0
T1	8415	575	0	0
T2	27976	388	0	0
T7	0	173	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T37	0	481	0	0
T48	0	43	0	0
T49	0	5	0	0
T88	0	53	0	0
T260	0	72	0	0
T261	0	193	0	0
T265	0	78	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	356	0	0
T1	8415	13	0	0
T2	27976	8	0	0
T7	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T37	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T88	0	5	0	0
T260	0	1	0	0
T261	0	5	0	0
T265	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5259837	0	0
T1	8415	4029	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	16114	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5261607	0	0
T1	8415	4029	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	16114	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	470	0	0
T1	8415	14	0	0
T2	0	10	0	0
T6	19504	5	0	0
T7	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T37	0	8	0	0
T48	0	2	0	0
T49	0	1	0	0
T88	0	8	0	0
T260	0	1	0	0
T261	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	428	0	0
T1	8415	13	0	0
T2	0	8	0	0
T6	19504	5	0	0
T7	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T37	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T88	0	5	0	0
T260	0	1	0	0
T261	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	356	0	0
T1	8415	13	0	0
T2	27976	8	0	0
T7	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T37	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T88	0	5	0	0
T260	0	1	0	0
T261	0	5	0	0
T265	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	356	0	0
T1	8415	13	0	0
T2	27976	8	0	0
T7	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T37	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T88	0	5	0	0
T260	0	1	0	0
T261	0	5	0	0
T265	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	13895	0	0
T1	8415	562	0	0
T2	27976	380	0	0
T7	0	168	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T37	0	474	0	0
T48	0	42	0	0
T49	0	4	0	0
T88	0	48	0	0
T260	0	71	0	0
T261	0	188	0	0
T265	0	77	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	317	0	0
T1	8415	13	0	0
T2	27976	8	0	0
T7	0	5	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T37	0	7	0	0
T48	0	1	0	0
T49	0	1	0	0
T88	0	5	0	0
T260	0	1	0	0
T261	0	5	0	0
T265	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T31,T32
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T31,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T31,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T31,T32
1	0	Covered	T7,T45,T38
1	1	Covered	T7,T31,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T32
0	1	Covered	T31,T32,T45
1	0	Covered	T45,T67,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T38,T46
0	1	Covered	T7,T38,T46
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T38,T46
1	-	Covered	T7,T38,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T31,T32
DetectSt	168	Covered	T7,T31,T32
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T38,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T31,T32
DebounceSt->IdleSt	163	Covered	T69,T58,T59
DetectSt->IdleSt	186	Covered	T31,T32,T45
DetectSt->StableSt	191	Covered	T7,T38,T46
IdleSt->DebounceSt	148	Covered	T7,T31,T32
StableSt->IdleSt	206	Covered	T7,T38,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T31,T32
0	1	Covered	T7,T31,T32
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T31,T32
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T31,T32
IdleSt	0	-	-	-	-	-	-	Covered	T7,T31,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T58,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T31,T32
DetectSt	-	-	-	-	1	-	-	Covered	T31,T32,T45
DetectSt	-	-	-	-	0	1	-	Covered	T7,T38,T46
DetectSt	-	-	-	-	0	0	-	Covered	T7,T31,T32
StableSt	-	-	-	-	-	-	1	Covered	T7,T38,T46
StableSt	-	-	-	-	-	-	0	Covered	T7,T38,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	2745	0	0
CntIncr_A	6273387	86182	0	0
CntNoWrap_A	6273387	5590850	0	0
DetectStDropOut_A	6273387	416	0	0
DetectedOut_A	6273387	52515	0	0
DetectedPulseOut_A	6273387	744	0	0
DisabledIdleSt_A	6273387	5201455	0	0
DisabledNoDetection_A	6273387	5203638	0	0
EnterDebounceSt_A	6273387	1384	0	0
EnterDetectSt_A	6273387	1361	0	0
EnterStableSt_A	6273387	744	0	0
PulseIsPulse_A	6273387	744	0	0
StayInStableSt	6273387	51712	0	0
gen_high_event_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	684	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2745	0	0
T7	12899	12	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	4	0	0
T32	0	22	0	0
T38	0	46	0	0
T45	0	56	0	0
T46	0	56	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	18	0	0
T68	0	48	0	0
T69	0	10	0	0
T70	570	0	0	0
T71	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	86182	0	0
T7	12899	354	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	105	0	0
T32	0	603	0	0
T38	0	1472	0	0
T45	0	1668	0	0
T46	0	2520	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	623	0	0
T68	0	693	0	0
T69	0	1363	0	0
T70	570	0	0	0
T71	0	1300	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5590850	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	416	0	0
T31	5219	2	0	0
T32	5367	11	0	0
T36	14253	0	0	0
T39	884	0	0	0
T45	0	11	0	0
T52	598	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1169	0	0	0
T61	648	0	0	0
T67	0	3	0	0
T68	0	24	0	0
T90	0	18	0	0
T130	0	25	0	0
T191	0	10	0	0
T237	521	0	0	0
T250	437	0	0	0
T251	411	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	52515	0	0
T7	12899	226	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	1826	0	0
T46	0	2588	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	372	0	0
T59	0	363	0	0
T69	0	3	0	0
T70	570	0	0	0
T71	0	1771	0	0
T253	0	1241	0	0
T254	0	788	0	0
T255	0	1051	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	744	0	0
T7	12899	6	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	23	0	0
T46	0	28	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T69	0	1	0	0
T70	570	0	0	0
T71	0	26	0	0
T253	0	15	0	0
T254	0	9	0	0
T255	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5201455	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5203638	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1384	0	0
T7	12899	6	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	2	0	0
T32	0	11	0	0
T38	0	23	0	0
T45	0	28	0	0
T46	0	28	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	9	0	0
T68	0	24	0	0
T69	0	9	0	0
T70	570	0	0	0
T71	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1361	0	0
T7	12899	6	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	2	0	0
T32	0	11	0	0
T38	0	23	0	0
T45	0	28	0	0
T46	0	28	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	9	0	0
T68	0	24	0	0
T69	0	1	0	0
T70	570	0	0	0
T71	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	744	0	0
T7	12899	6	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	23	0	0
T46	0	28	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T69	0	1	0	0
T70	570	0	0	0
T71	0	26	0	0
T253	0	15	0	0
T254	0	9	0	0
T255	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	744	0	0
T7	12899	6	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	23	0	0
T46	0	28	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T69	0	1	0	0
T70	570	0	0	0
T71	0	26	0	0
T253	0	15	0	0
T254	0	9	0	0
T255	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	51712	0	0
T7	12899	220	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	1800	0	0
T46	0	2559	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	367	0	0
T59	0	358	0	0
T69	0	2	0	0
T70	570	0	0	0
T71	0	1745	0	0
T253	0	1223	0	0
T254	0	776	0	0
T255	0	1039	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	684	0	0
T7	12899	6	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	20	0	0
T46	0	27	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	4	0	0
T59	0	5	0	0
T69	0	1	0	0
T70	570	0	0	0
T71	0	26	0	0
T253	0	12	0	0
T254	0	6	0	0
T255	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T6,T1,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T48,T49,T50
1	0	Covered	T58,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T1,T2
1	0	Covered	T58,T59,T266

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T1,T2
1	-	Covered	T6,T1,T2

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T1,T2
DetectSt	168	Covered	T6,T1,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T6,T1,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T1,T2
DebounceSt->IdleSt	163	Covered	T6,T1,T49
DetectSt->IdleSt	186	Covered	T48,T49,T50
DetectSt->StableSt	191	Covered	T6,T1,T2
IdleSt->DebounceSt	148	Covered	T6,T1,T2
StableSt->IdleSt	206	Covered	T6,T1,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T1,T2
0	1	Covered	T6,T1,T2
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T1,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T1,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T1,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T1,T2
DetectSt	-	-	-	-	1	-	-	Covered	T48,T49,T50
DetectSt	-	-	-	-	0	1	-	Covered	T6,T1,T2
DetectSt	-	-	-	-	0	0	-	Covered	T6,T1,T2
StableSt	-	-	-	-	-	-	1	Covered	T6,T1,T2
StableSt	-	-	-	-	-	-	0	Covered	T6,T1,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	778	0	0
CntIncr_A	6273387	46094	0	0
CntNoWrap_A	6273387	5592817	0	0
DetectStDropOut_A	6273387	63	0	0
DetectedOut_A	6273387	9800	0	0
DetectedPulseOut_A	6273387	296	0	0
DisabledIdleSt_A	6273387	5260898	0	0
DisabledNoDetection_A	6273387	5262666	0	0
EnterDebounceSt_A	6273387	416	0	0
EnterDetectSt_A	6273387	362	0	0
EnterStableSt_A	6273387	296	0	0
PulseIsPulse_A	6273387	296	0	0
StayInStableSt	6273387	9490	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	278	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	778	0	0
T1	8415	5	0	0
T2	0	10	0	0
T6	19504	27	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	5	0	0
T48	0	2	0	0
T49	0	16	0	0
T50	0	2	0	0
T260	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	46094	0	0
T1	8415	179	0	0
T2	0	935	0	0
T6	19504	791	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	194	0	0
T37	0	258	0	0
T38	0	205	0	0
T48	0	108	0	0
T49	0	849	0	0
T50	0	75	0	0
T260	0	192	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5592817	0	0
T1	8415	8007	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19062	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	63	0	0
T7	12899	0	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T48	15575	1	0	0
T49	7347	7	0	0
T50	6532	1	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	1	0	0
T78	0	2	0	0
T156	0	6	0	0
T181	0	2	0	0
T263	0	10	0	0
T267	0	12	0	0
T268	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	9800	0	0
T1	8415	110	0	0
T2	0	21	0	0
T6	19504	368	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	27	0	0
T37	0	8	0	0
T38	0	94	0	0
T88	0	25	0	0
T260	0	97	0	0
T261	0	34	0	0
T265	0	89	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	296	0	0
T1	8415	2	0	0
T2	0	5	0	0
T6	19504	13	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T88	0	6	0	0
T260	0	2	0	0
T261	0	4	0	0
T265	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5260898	0	0
T1	8415	4029	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	16114	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5262666	0	0
T1	8415	4029	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	16114	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	416	0	0
T1	8415	3	0	0
T2	0	5	0	0
T6	19504	14	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	3	0	0
T48	0	1	0	0
T49	0	9	0	0
T50	0	1	0	0
T260	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	362	0	0
T1	8415	2	0	0
T2	0	5	0	0
T6	19504	13	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T48	0	1	0	0
T49	0	7	0	0
T50	0	1	0	0
T260	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	296	0	0
T1	8415	2	0	0
T2	0	5	0	0
T6	19504	13	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T88	0	6	0	0
T260	0	2	0	0
T261	0	4	0	0
T265	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	296	0	0
T1	8415	2	0	0
T2	0	5	0	0
T6	19504	13	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T88	0	6	0	0
T260	0	2	0	0
T261	0	4	0	0
T265	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	9490	0	0
T1	8415	108	0	0
T2	0	16	0	0
T6	19504	355	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	26	0	0
T37	0	7	0	0
T38	0	92	0	0
T88	0	19	0	0
T260	0	95	0	0
T261	0	30	0	0
T265	0	79	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	278	0	0
T1	8415	2	0	0
T2	0	5	0	0
T6	19504	13	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T88	0	6	0	0
T260	0	2	0	0
T261	0	4	0	0
T265	0	10	0	0