Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T31,T32
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T31,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T31,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T31,T32
1	0	Covered	T7,T45,T38
1	1	Covered	T7,T31,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T32
0	1	Covered	T31,T32,T68
1	0	Covered	T58,T59,T269

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T38
0	1	Covered	T7,T45,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T45,T38
1	-	Covered	T7,T45,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T31,T32
DetectSt	168	Covered	T7,T31,T32
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T45,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T31,T32
DebounceSt->IdleSt	163	Covered	T69,T58,T59
DetectSt->IdleSt	186	Covered	T31,T32,T68
DetectSt->StableSt	191	Covered	T7,T45,T38
IdleSt->DebounceSt	148	Covered	T7,T31,T32
StableSt->IdleSt	206	Covered	T7,T45,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T31,T32
0	1	Covered	T7,T31,T32
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T31,T32
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T7,T31,T32
IdleSt	0	-	-	-	-	-	-	Covered	T7,T31,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T58,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T31,T32
DetectSt	-	-	-	-	1	-	-	Covered	T31,T32,T68
DetectSt	-	-	-	-	0	1	-	Covered	T7,T45,T38
DetectSt	-	-	-	-	0	0	-	Covered	T7,T31,T32
StableSt	-	-	-	-	-	-	1	Covered	T7,T45,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T45,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	2844	0	0
CntIncr_A	6273387	91758	0	0
CntNoWrap_A	6273387	5590751	0	0
DetectStDropOut_A	6273387	340	0	0
DetectedOut_A	6273387	72085	0	0
DetectedPulseOut_A	6273387	934	0	0
DisabledIdleSt_A	6273387	5188321	0	0
DisabledNoDetection_A	6273387	5190469	0	0
EnterDebounceSt_A	6273387	1438	0	0
EnterDetectSt_A	6273387	1407	0	0
EnterStableSt_A	6273387	934	0	0
PulseIsPulse_A	6273387	934	0	0
StayInStableSt	6273387	71056	0	0
gen_high_event_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	839	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	2844	0	0
T7	12899	26	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	36	0	0
T32	0	22	0	0
T38	0	26	0	0
T45	0	32	0	0
T46	0	36	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	42	0	0
T68	0	24	0	0
T69	0	19	0	0
T70	570	0	0	0
T71	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	91758	0	0
T7	12899	637	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	940	0	0
T32	0	603	0	0
T38	0	650	0	0
T45	0	816	0	0
T46	0	1512	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	1260	0	0
T68	0	342	0	0
T69	0	2437	0	0
T70	570	0	0	0
T71	0	1633	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5590751	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	340	0	0
T31	5219	18	0	0
T32	5367	11	0	0
T36	14253	0	0	0
T39	884	0	0	0
T52	598	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1169	0	0	0
T61	648	0	0	0
T68	0	12	0	0
T69	0	4	0	0
T90	0	25	0	0
T130	0	7	0	0
T191	0	25	0	0
T237	521	0	0	0
T250	437	0	0	0
T251	411	0	0	0
T256	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	72085	0	0
T7	12899	1319	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	1682	0	0
T45	0	1580	0	0
T46	0	1595	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	325	0	0
T59	0	407	0	0
T67	0	1154	0	0
T70	570	0	0	0
T71	0	771	0	0
T253	0	731	0	0
T254	0	3536	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	934	0	0
T7	12899	13	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	13	0	0
T45	0	16	0	0
T46	0	18	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T67	0	21	0	0
T70	570	0	0	0
T71	0	23	0	0
T253	0	26	0	0
T254	0	29	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5188321	0	0
T1	8415	8012	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19089	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5190469	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1438	0	0
T7	12899	13	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	18	0	0
T32	0	11	0	0
T38	0	13	0	0
T45	0	16	0	0
T46	0	18	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	21	0	0
T68	0	12	0	0
T69	0	16	0	0
T70	570	0	0	0
T71	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	1407	0	0
T7	12899	13	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T31	0	18	0	0
T32	0	11	0	0
T38	0	13	0	0
T45	0	16	0	0
T46	0	18	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T67	0	21	0	0
T68	0	12	0	0
T69	0	4	0	0
T70	570	0	0	0
T71	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	934	0	0
T7	12899	13	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	13	0	0
T45	0	16	0	0
T46	0	18	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T67	0	21	0	0
T70	570	0	0	0
T71	0	23	0	0
T253	0	26	0	0
T254	0	29	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	934	0	0
T7	12899	13	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	13	0	0
T45	0	16	0	0
T46	0	18	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T67	0	21	0	0
T70	570	0	0	0
T71	0	23	0	0
T253	0	26	0	0
T254	0	29	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	71056	0	0
T7	12899	1306	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	1666	0	0
T45	0	1562	0	0
T46	0	1575	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	320	0	0
T59	0	402	0	0
T67	0	1130	0	0
T70	570	0	0	0
T71	0	747	0	0
T253	0	702	0	0
T254	0	3496	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	839	0	0
T7	12899	13	0	0
T8	303659	0	0	0
T9	713	0	0	0
T10	512	0	0	0
T38	0	10	0	0
T45	0	14	0	0
T46	0	16	0	0
T49	7347	0	0	0
T50	6532	0	0	0
T55	406	0	0	0
T56	523	0	0	0
T57	499	0	0	0
T58	0	5	0	0
T59	0	5	0	0
T67	0	18	0	0
T70	570	0	0	0
T71	0	22	0	0
T253	0	23	0	0
T254	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T6,T1,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T48,T265
1	0	Covered	T58,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T1,T2
DetectSt	168	Covered	T6,T1,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T1,T2
DebounceSt->IdleSt	163	Covered	T2,T45,T37
DetectSt->IdleSt	186	Covered	T6,T48,T265
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T6,T1,T2
StableSt->IdleSt	206	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T1,T2
0	1	Covered	T6,T1,T2
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T1,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T58,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T1,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T45,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T1,T2
DetectSt	-	-	-	-	1	-	-	Covered	T6,T48,T265
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Covered	T6,T1,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6273387	735	0	0
CntIncr_A	6273387	40909	0	0
CntNoWrap_A	6273387	5592860	0	0
DetectStDropOut_A	6273387	83	0	0
DetectedOut_A	6273387	12238	0	0
DetectedPulseOut_A	6273387	256	0	0
DisabledIdleSt_A	6273387	5234401	0	0
DisabledNoDetection_A	6273387	5236125	0	0
EnterDebounceSt_A	6273387	392	0	0
EnterDetectSt_A	6273387	346	0	0
EnterStableSt_A	6273387	256	0	0
PulseIsPulse_A	6273387	256	0	0
StayInStableSt	6273387	11963	0	0
gen_high_level_sva.HighLevelEvent_A	6273387	5595925	0	0
gen_not_sticky_sva.StableStDropOut_A	6273387	235	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	735	0	0
T1	8415	2	0	0
T2	0	9	0	0
T6	19504	6	0	0
T7	0	2	0	0
T8	0	2	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T45	0	5	0	0
T48	0	10	0	0
T50	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	40909	0	0
T1	8415	102	0	0
T2	0	510	0	0
T6	19504	258	0	0
T7	0	69	0	0
T8	0	175	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	144	0	0
T37	0	58	0	0
T45	0	161	0	0
T48	0	539	0	0
T50	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5592860	0	0
T1	8415	8010	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	19083	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	83	0	0
T1	8415	0	0	0
T6	19504	3	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T48	0	5	0	0
T78	0	10	0	0
T92	0	2	0	0
T93	0	2	0	0
T196	0	1	0	0
T262	0	5	0	0
T265	0	2	0	0
T270	0	5	0	0
T271	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	12238	0	0
T1	8415	20	0	0
T2	27976	340	0	0
T7	0	43	0	0
T8	0	42	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T36	0	74	0	0
T38	0	201	0	0
T45	0	95	0	0
T50	0	9	0	0
T260	0	31	0	0
T261	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	256	0	0
T1	8415	1	0	0
T2	27976	4	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T36	0	1	0	0
T38	0	3	0	0
T45	0	2	0	0
T50	0	1	0	0
T260	0	7	0	0
T261	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5234401	0	0
T1	8415	4029	0	0
T4	639	238	0	0
T5	423	22	0	0
T6	19504	16114	0	0
T14	522	121	0	0
T15	502	101	0	0
T22	403	2	0	0
T23	427	26	0	0
T24	421	20	0	0
T25	491	90	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5236125	0	0
T1	8415	4029	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	16114	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	392	0	0
T1	8415	1	0	0
T2	0	5	0	0
T6	19504	3	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T45	0	3	0	0
T48	0	5	0	0
T50	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	346	0	0
T1	8415	1	0	0
T2	0	4	0	0
T6	19504	3	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T22	403	0	0	0
T23	427	0	0	0
T24	421	0	0	0
T25	491	0	0	0
T36	0	1	0	0
T38	0	3	0	0
T45	0	2	0	0
T48	0	5	0	0
T50	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	256	0	0
T1	8415	1	0	0
T2	27976	4	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T36	0	1	0	0
T38	0	3	0	0
T45	0	2	0	0
T50	0	1	0	0
T260	0	7	0	0
T261	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	256	0	0
T1	8415	1	0	0
T2	27976	4	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T36	0	1	0	0
T38	0	3	0	0
T45	0	2	0	0
T50	0	1	0	0
T260	0	7	0	0
T261	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	11963	0	0
T1	8415	19	0	0
T2	27976	336	0	0
T7	0	42	0	0
T8	0	41	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T36	0	73	0	0
T38	0	198	0	0
T45	0	93	0	0
T50	0	8	0	0
T260	0	24	0	0
T261	0	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	5595925	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6273387	235	0	0
T1	8415	1	0	0
T2	27976	4	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	522	0	0	0
T15	502	0	0	0
T16	421	0	0	0
T17	12500	0	0	0
T18	522	0	0	0
T19	657	0	0	0
T20	495	0	0	0
T21	421	0	0	0
T36	0	1	0	0
T38	0	3	0	0
T45	0	2	0	0
T50	0	1	0	0
T260	0	7	0	0
T261	0	3	0	0