Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1050742572	10398	0	0
auto_block_debounce_ctl_rd_A	1050742572	1474	0	0
auto_block_out_ctl_rd_A	1050742572	1974	0	0
com_det_ctl_0_rd_A	1050742572	3226	0	0
com_det_ctl_1_rd_A	1050742572	3328	0	0
com_det_ctl_2_rd_A	1050742572	3310	0	0
com_det_ctl_3_rd_A	1050742572	3458	0	0
com_out_ctl_0_rd_A	1050742572	3592	0	0
com_out_ctl_1_rd_A	1050742572	3672	0	0
com_out_ctl_2_rd_A	1050742572	3756	0	0
com_out_ctl_3_rd_A	1050742572	3600	0	0
com_pre_det_ctl_0_rd_A	1050742572	1130	0	0
com_pre_det_ctl_1_rd_A	1050742572	1123	0	0
com_pre_det_ctl_2_rd_A	1050742572	1117	0	0
com_pre_det_ctl_3_rd_A	1050742572	1053	0	0
com_pre_sel_ctl_0_rd_A	1050742572	3641	0	0
com_pre_sel_ctl_1_rd_A	1050742572	3944	0	0
com_pre_sel_ctl_2_rd_A	1050742572	3652	0	0
com_pre_sel_ctl_3_rd_A	1050742572	3843	0	0
com_sel_ctl_0_rd_A	1050742572	3742	0	0
com_sel_ctl_1_rd_A	1050742572	3821	0	0
com_sel_ctl_2_rd_A	1050742572	3812	0	0
com_sel_ctl_3_rd_A	1050742572	3746	0	0
ec_rst_ctl_rd_A	1050742572	2032	0	0
intr_enable_rd_A	1050742572	1764	0	0
key_intr_ctl_rd_A	1050742572	2319	0	0
key_intr_debounce_ctl_rd_A	1050742572	1017	0	0
key_invert_ctl_rd_A	1050742572	3576	0	0
pin_allowed_ctl_rd_A	1050742572	4208	0	0
pin_out_ctl_rd_A	1050742572	3130	0	0
pin_out_value_rd_A	1050742572	3090	0	0
regwen_rd_A	1050742572	1338	0	0
ulp_ac_debounce_ctl_rd_A	1050742572	1204	0	0
ulp_ctl_rd_A	1050742572	1305	0	0
ulp_lid_debounce_ctl_rd_A	1050742572	1257	0	0
ulp_pwrb_debounce_ctl_rd_A	1050742572	1237	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	10398	0	0
T3	223612	11	0	0
T7	161242	0	0	0
T8	422958	11	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T35	0	10	0	0
T36	0	3	0	0
T40	0	27	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	6	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T62	0	26	0	0
T72	0	13	0	0
T74	0	9	0	0
T75	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1474	0	0
T1	420770	0	0	0
T3	0	12	0	0
T4	153479	21	0	0
T5	105769	0	0	0
T6	936157	0	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T19	0	13	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T36	0	7	0	0
T52	0	5	0	0
T72	0	28	0	0
T74	0	51	0	0
T75	0	13	0	0
T100	0	5	0	0
T295	0	21	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1974	0	0
T1	420770	0	0	0
T3	0	5	0	0
T4	153479	12	0	0
T5	105769	0	0	0
T6	936157	0	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T19	0	10	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T36	0	13	0	0
T52	0	9	0	0
T72	0	53	0	0
T74	0	57	0	0
T75	0	21	0	0
T100	0	4	0	0
T295	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3226	0	0
T1	420770	54	0	0
T2	135691	58	0	0
T3	0	11	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	8	0	0
T37	0	60	0	0
T72	0	30	0	0
T74	0	34	0	0
T75	0	22	0	0
T259	0	62	0	0
T265	0	83	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3328	0	0
T1	420770	75	0	0
T2	135691	81	0	0
T3	0	6	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	23	0	0
T37	0	57	0	0
T72	0	22	0	0
T74	0	28	0	0
T75	0	25	0	0
T259	0	61	0	0
T265	0	81	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3310	0	0
T1	420770	67	0	0
T2	135691	56	0	0
T3	0	16	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	23	0	0
T37	0	65	0	0
T72	0	34	0	0
T74	0	21	0	0
T75	0	11	0	0
T259	0	54	0	0
T265	0	83	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3458	0	0
T1	420770	88	0	0
T2	135691	43	0	0
T3	0	4	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	26	0	0
T37	0	85	0	0
T72	0	29	0	0
T74	0	40	0	0
T75	0	19	0	0
T259	0	67	0	0
T265	0	88	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3592	0	0
T1	420770	62	0	0
T2	135691	65	0	0
T3	0	2	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	21	0	0
T37	0	72	0	0
T72	0	26	0	0
T74	0	32	0	0
T75	0	18	0	0
T259	0	74	0	0
T265	0	76	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3672	0	0
T1	420770	82	0	0
T2	135691	79	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	9	0	0
T37	0	86	0	0
T72	0	25	0	0
T74	0	48	0	0
T75	0	15	0	0
T253	0	83	0	0
T259	0	66	0	0
T265	0	71	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3756	0	0
T1	420770	90	0	0
T2	135691	79	0	0
T3	0	4	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	18	0	0
T37	0	80	0	0
T72	0	31	0	0
T74	0	26	0	0
T75	0	22	0	0
T259	0	77	0	0
T265	0	64	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3600	0	0
T1	420770	59	0	0
T2	135691	65	0	0
T3	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	32	0	0
T37	0	59	0	0
T72	0	20	0	0
T74	0	27	0	0
T75	0	21	0	0
T259	0	64	0	0
T265	0	71	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1130	0	0
T3	223612	7	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	9	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T72	0	27	0	0
T74	0	43	0	0
T75	0	22	0	0
T123	0	10	0	0
T176	0	4	0	0
T248	0	3	0	0
T295	0	17	0	0
T296	0	22	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1123	0	0
T3	223612	1	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	10	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T72	0	39	0	0
T74	0	32	0	0
T75	0	16	0	0
T98	0	2	0	0
T123	0	33	0	0
T176	0	12	0	0
T295	0	21	0	0
T296	0	15	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1117	0	0
T3	223612	3	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	13	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T72	0	31	0	0
T74	0	42	0	0
T75	0	14	0	0
T123	0	22	0	0
T176	0	1	0	0
T248	0	5	0	0
T295	0	8	0	0
T296	0	11	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1053	0	0
T3	223612	3	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	7	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T72	0	25	0	0
T74	0	32	0	0
T75	0	15	0	0
T123	0	8	0	0
T176	0	5	0	0
T248	0	4	0	0
T295	0	14	0	0
T296	0	10	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3641	0	0
T1	420770	81	0	0
T2	135691	84	0	0
T3	0	9	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	13	0	0
T37	0	64	0	0
T72	0	31	0	0
T74	0	32	0	0
T75	0	35	0	0
T259	0	68	0	0
T265	0	50	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3944	0	0
T1	420770	77	0	0
T2	135691	59	0	0
T3	0	7	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	21	0	0
T37	0	56	0	0
T72	0	26	0	0
T74	0	25	0	0
T75	0	37	0	0
T259	0	60	0	0
T265	0	80	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3652	0	0
T1	420770	77	0	0
T2	135691	73	0	0
T3	0	6	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	22	0	0
T37	0	83	0	0
T72	0	30	0	0
T74	0	26	0	0
T75	0	24	0	0
T259	0	52	0	0
T265	0	61	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3843	0	0
T1	420770	77	0	0
T2	135691	95	0	0
T3	0	5	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	28	0	0
T37	0	95	0	0
T72	0	22	0	0
T74	0	31	0	0
T75	0	21	0	0
T259	0	60	0	0
T265	0	61	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3742	0	0
T1	420770	80	0	0
T2	135691	75	0	0
T3	0	2	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	28	0	0
T37	0	63	0	0
T72	0	29	0	0
T74	0	45	0	0
T75	0	23	0	0
T259	0	64	0	0
T265	0	68	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3821	0	0
T1	420770	95	0	0
T2	135691	100	0	0
T3	0	7	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	29	0	0
T37	0	67	0	0
T72	0	25	0	0
T74	0	38	0	0
T75	0	24	0	0
T259	0	61	0	0
T265	0	80	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3812	0	0
T1	420770	73	0	0
T2	135691	67	0	0
T3	0	3	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	14	0	0
T37	0	59	0	0
T72	0	26	0	0
T74	0	35	0	0
T75	0	25	0	0
T259	0	77	0	0
T265	0	74	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3746	0	0
T1	420770	79	0	0
T2	135691	59	0	0
T3	0	7	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	17	0	0
T37	0	73	0	0
T72	0	37	0	0
T74	0	28	0	0
T75	0	34	0	0
T259	0	60	0	0
T265	0	71	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	2032	0	0
T1	420770	11	0	0
T2	135691	37	0	0
T3	0	9	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T31	0	5	0	0
T36	0	19	0	0
T37	0	48	0	0
T72	0	55	0	0
T74	0	38	0	0
T259	0	3	0	0
T265	0	47	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1764	0	0
T3	223612	52	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	4	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T72	0	47	0	0
T74	0	52	0	0
T75	0	38	0	0
T123	0	43	0	0
T195	0	7	0	0
T295	0	33	0	0
T297	0	17	0	0
T298	0	4	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	2319	0	0
T36	152655	16	0	0
T37	346073	0	0	0
T39	300743	0	0	0
T42	0	7	0	0
T45	133007	0	0	0
T60	61125	0	0	0
T72	0	23	0	0
T74	0	47	0	0
T75	0	20	0	0
T84	0	6	0	0
T137	164922	0	0	0
T138	241348	0	0	0
T139	54588	0	0	0
T140	58211	0	0	0
T159	0	8	0	0
T168	0	2	0	0
T194	0	7	0	0
T237	260941	0	0	0
T295	0	10	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1017	0	0
T3	223612	9	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	8	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T72	0	30	0	0
T74	0	24	0	0
T75	0	22	0	0
T98	0	6	0	0
T123	0	23	0	0
T295	0	29	0	0
T296	0	25	0	0
T299	0	47	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3576	0	0
T3	223612	62	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	67	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T72	0	32	0	0
T74	0	88	0	0
T75	0	84	0	0
T114	0	83	0	0
T118	0	49	0	0
T134	0	34	0	0
T300	0	59	0	0
T301	0	95	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	4208	0	0
T2	135691	0	0	0
T3	0	150	0	0
T15	246356	60	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	75	0	0
T47	359838	0	0	0
T66	158636	0	0	0
T72	0	176	0	0
T74	0	30	0	0
T75	0	26	0	0
T302	0	40	0	0
T303	0	60	0	0
T304	0	60	0	0
T305	0	77	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3130	0	0
T2	135691	0	0	0
T3	0	159	0	0
T15	246356	64	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	69	0	0
T47	359838	0	0	0
T66	158636	0	0	0
T72	0	182	0	0
T74	0	24	0	0
T75	0	11	0	0
T302	0	41	0	0
T303	0	72	0	0
T304	0	44	0	0
T305	0	69	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	3090	0	0
T2	135691	0	0	0
T3	0	125	0	0
T15	246356	69	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	65	0	0
T47	359838	0	0	0
T66	158636	0	0	0
T72	0	170	0	0
T74	0	14	0	0
T75	0	23	0	0
T302	0	49	0	0
T303	0	74	0	0
T304	0	40	0	0
T305	0	71	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1338	0	0
T3	223612	8	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	10	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T72	0	28	0	0
T74	0	21	0	0
T75	0	11	0	0
T123	0	43	0	0
T176	0	2	0	0
T248	0	1	0	0
T295	0	17	0	0
T296	0	20	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1204	0	0
T3	223612	7	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	4	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T61	0	7	0	0
T72	0	34	0	0
T74	0	46	0	0
T75	0	19	0	0
T109	0	4	0	0
T226	0	2	0	0
T295	0	11	0	0
T306	0	4	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1305	0	0
T3	223612	21	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	7	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T61	0	1	0	0
T72	0	49	0	0
T74	0	46	0	0
T75	0	32	0	0
T109	0	6	0	0
T168	0	1	0	0
T295	0	27	0	0
T306	0	3	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1257	0	0
T3	223612	4	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	10	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T72	0	35	0	0
T74	0	43	0	0
T75	0	32	0	0
T168	0	3	0	0
T226	0	1	0	0
T295	0	24	0	0
T306	0	4	0	0
T307	0	6	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1237	0	0
T3	223612	14	0	0
T7	161242	0	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T36	0	17	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T72	0	34	0	0
T74	0	53	0	0
T75	0	29	0	0
T109	0	4	0	0
T168	0	8	0	0
T226	0	3	0	0
T295	0	12	0	0
T306	0	3	0	0