Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T25,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T25,T1
1	1	Covered	T6,T25,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T25,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T25,T1
1	1	Covered	T6,T25,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T13
1	-	Covered	T1,T2,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	105192780	0	0
DstReqKnown_A	222225802	192431874	0	0
SrcAckBusyChk_A	2147483647	113398	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	105192780	0	0
T1	4207700	6776	0	0
T2	0	33912	0	0
T3	0	689	0	0
T4	306958	5682	0	0
T5	211538	0	0	0
T6	9361570	24820	0	0
T7	161242	2485	0	0
T8	422958	25120	0	0
T9	61248	0	0	0
T10	35912	198	0	0
T14	2505740	0	0	0
T15	2463560	0	0	0
T16	1586496	0	0	0
T17	1650032	3785	0	0
T19	0	3929	0	0
T22	2018260	0	0	0
T23	1070470	0	0	0
T24	2111260	0	0	0
T25	1230890	0	0	0
T31	0	282	0	0
T32	0	945	0	0
T35	0	14444	0	0
T47	0	14521	0	0
T48	0	18894	0	0
T49	360036	5785	0	0
T50	587878	910	0	0
T51	0	11965	0	0
T52	0	3906	0	0
T53	0	4822	0	0
T54	0	6577	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222225802	192431874	0	0
T1	286110	272476	0	0
T4	21726	8126	0	0
T5	14382	782	0	0
T6	663136	649298	0	0
T14	17748	4148	0	0
T15	17068	3468	0	0
T22	13702	102	0	0
T23	14518	918	0	0
T24	14314	714	0	0
T25	16694	3094	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	113398	0	0
T1	4207700	4	0	0
T2	0	20	0	0
T3	0	1	0	0
T4	306958	7	0	0
T5	211538	0	0	0
T6	9361570	16	0	0
T7	161242	6	0	0
T8	422958	30	0	0
T9	61248	0	0	0
T10	35912	1	0	0
T14	2505740	0	0	0
T15	2463560	0	0	0
T16	1586496	0	0	0
T17	1650032	7	0	0
T19	0	8	0	0
T22	2018260	0	0	0
T23	1070470	0	0	0
T24	2111260	0	0	0
T25	1230890	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	15	0	0
T47	0	9	0	0
T48	0	12	0	0
T49	360036	4	0	0
T50	587878	3	0	0
T51	0	7	0	0
T52	0	9	0	0
T53	0	6	0	0
T54	0	8	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14306180	14304310	0	0
T4	5218286	5215056	0	0
T5	3596146	3593290	0	0
T6	31829338	31817676	0	0
T14	8519516	8516762	0	0
T15	8376104	8372772	0	0
T22	6862084	6859602	0	0
T23	3639598	3637490	0	0
T24	7178284	7175836	0	0
T25	4185026	4181626	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T58,T59,T33
1	-	Covered	T1,T2,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1056828	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1134	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1056828	0	0
T1	420770	22620	0	0
T2	135691	13381	0	0
T7	0	2050	0	0
T8	0	1390	0	0
T11	0	553	0	0
T13	0	2865	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	424	0	0
T37	0	409	0	0
T45	0	832	0	0
T60	0	764	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1134	0	0
T1	420770	13	0	0
T2	135691	8	0	0
T7	0	5	0	0
T8	0	2	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T45	0	2	0	0
T60	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1784130	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1912	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1784130	0	0
T1	420770	3239	0	0
T2	0	16165	0	0
T3	0	1629	0	0
T6	936157	12290	0	0
T7	0	1303	0	0
T8	0	3215	0	0
T10	0	194	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T48	0	9357	0	0
T49	0	2791	0	0
T50	0	878	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1912	0	0
T1	420770	2	0	0
T2	0	10	0	0
T3	0	2	0	0
T6	936157	8	0	0
T7	0	3	0	0
T8	0	4	0	0
T10	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T3,T8,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T3,T8,T11
1	1	Covered	T3,T8,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T3,T8,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T8,T11
1	1	Covered	T3,T8,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T3,T8,T11
0	0	1	Covered	T3,T8,T11
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T3,T8,T11
0	0	1	Covered	T3,T8,T11
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1066975	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1051	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1066975	0	0
T3	223612	1701	0	0
T7	161242	0	0	0
T8	422958	2378	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T11	0	558	0	0
T13	0	2870	0	0
T35	0	1031	0	0
T40	0	3499	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T60	0	812	0	0
T61	0	599	0	0
T62	0	1915	0	0
T63	0	419	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1051	0	0
T3	223612	2	0	0
T7	161242	0	0	0
T8	422958	3	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T35	0	1	0	0
T40	0	2	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T3,T8,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T3,T8,T11
1	1	Covered	T3,T8,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T3,T8,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T8,T11
1	1	Covered	T3,T8,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T3,T8,T11
0	0	1	Covered	T3,T8,T11
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T3,T8,T11
0	0	1	Covered	T3,T8,T11
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1067664	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1059	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1067664	0	0
T3	223612	1678	0	0
T7	161242	0	0	0
T8	422958	2355	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T11	0	556	0	0
T13	0	2866	0	0
T35	0	1026	0	0
T40	0	3495	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T60	0	800	0	0
T61	0	584	0	0
T62	0	1911	0	0
T63	0	417	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1059	0	0
T3	223612	2	0	0
T7	161242	0	0	0
T8	422958	3	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T35	0	1	0	0
T40	0	2	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T3,T8,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T3,T8,T11
1	1	Covered	T3,T8,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T3,T8,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T8,T11
1	1	Covered	T3,T8,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T3,T8,T11
0	0	1	Covered	T3,T8,T11
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T3,T8,T11
0	0	1	Covered	T3,T8,T11
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1064428	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1059	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1064428	0	0
T3	223612	1667	0	0
T7	161242	0	0	0
T8	422958	2338	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T11	0	554	0	0
T13	0	2862	0	0
T35	0	1017	0	0
T40	0	3491	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T60	0	778	0	0
T61	0	566	0	0
T62	0	1907	0	0
T63	0	415	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1059	0	0
T3	223612	2	0	0
T7	161242	0	0	0
T8	422958	3	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T35	0	1	0	0
T40	0	2	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T25,T20,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T25,T20,T3
1	1	Covered	T25,T20,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T25,T20,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T20,T3
1	1	Covered	T25,T20,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T25,T20,T3
0	0	1	Covered	T25,T20,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T25,T20,T3
0	0	1	Covered	T25,T20,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	2793125	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	2813	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	2793125	0	0
T1	420770	0	0	0
T3	0	16529	0	0
T8	0	16913	0	0
T11	0	10084	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	8626	0	0
T21	109532	0	0	0
T25	123089	16866	0	0
T35	0	18881	0	0
T36	0	7695	0	0
T57	0	8656	0	0
T64	0	8400	0	0
T65	0	8161	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	2813	0	0
T1	420770	0	0	0
T3	0	20	0	0
T8	0	20	0	0
T11	0	20	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	0	0	0
T19	82171	0	0	0
T20	61948	20	0	0
T21	109532	0	0	0
T25	123089	20	0	0
T35	0	20	0	0
T36	0	20	0	0
T57	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T25,T14,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T25,T14,T15
1	1	Covered	T25,T14,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T25,T14,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T14,T15
1	1	Covered	T25,T14,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T25,T14,T15
0	0	1	Covered	T25,T14,T15
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T25,T14,T15
0	0	1	Covered	T25,T14,T15
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	6335565	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	6889	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6335565	0	0
T1	420770	0	0	0
T3	0	51684	0	0
T8	0	38159	0	0
T14	250574	32244	0	0
T15	246356	32807	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	33473	0	0
T19	82171	0	0	0
T20	61948	369	0	0
T21	109532	0	0	0
T25	123089	725	0	0
T50	0	11594	0	0
T56	0	17178	0	0
T66	0	21663	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6889	0	0
T1	420770	0	0	0
T3	0	61	0	0
T8	0	46	0	0
T14	250574	20	0	0
T15	246356	20	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	20	0	0
T19	82171	0	0	0
T20	61948	1	0	0
T21	109532	0	0	0
T25	123089	1	0	0
T50	0	40	0	0
T56	0	20	0	0
T66	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T25,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T25,T1
1	1	Covered	T6,T25,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T25,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T25,T1
1	1	Covered	T6,T25,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T25,T1
0	0	1	Covered	T6,T25,T1
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T25,T1
0	0	1	Covered	T6,T25,T1
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	7406625	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	7998	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	7406625	0	0
T1	420770	3458	0	0
T2	0	17290	0	0
T3	0	55567	0	0
T6	936157	12435	0	0
T14	250574	32514	0	0
T15	246356	33217	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	0	33751	0	0
T20	0	371	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	727	0	0
T66	0	21743	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	7998	0	0
T1	420770	2	0	0
T2	0	10	0	0
T3	0	64	0	0
T6	936157	8	0	0
T14	250574	20	0	0
T15	246356	20	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	0	20	0	0
T20	0	1	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	1	0	0
T66	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T14,T15,T18

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T14,T15,T18
1	1	Covered	T14,T15,T18

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T14,T15,T18

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T15,T18
1	1	Covered	T14,T15,T18

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T14,T15,T18
0	0	1	Covered	T14,T15,T18
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T14,T15,T18
0	0	1	Covered	T14,T15,T18
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	6313695	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	6851	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6313695	0	0
T2	135691	0	0	0
T3	0	51308	0	0
T8	0	37525	0	0
T14	250574	32367	0	0
T15	246356	33019	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	33611	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T35	0	18732	0	0
T36	0	29736	0	0
T50	0	11872	0	0
T56	0	17218	0	0
T66	158636	21703	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6851	0	0
T2	135691	0	0	0
T3	0	60	0	0
T8	0	45	0	0
T14	250574	20	0	0
T15	246356	20	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T18	245551	20	0	0
T19	82171	0	0	0
T20	61948	0	0	0
T21	109532	0	0	0
T35	0	20	0	0
T36	0	80	0	0
T50	0	40	0	0
T56	0	20	0	0
T66	158636	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T3,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T3,T8,T9
1	1	Covered	T3,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T3,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T8,T9
1	1	Covered	T3,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T3,T8,T9
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T3,T8,T9
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1091002	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1066	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1091002	0	0
T3	223612	723	0	0
T7	161242	0	0	0
T8	422958	2375	0	0
T9	61248	477	0	0
T10	35912	0	0	0
T11	0	1395	0	0
T12	0	1499	0	0
T35	0	1035	0	0
T36	0	741	0	0
T39	0	1349	0	0
T41	0	1996	0	0
T44	0	718	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1066	0	0
T3	223612	1	0	0
T7	161242	0	0	0
T8	422958	3	0	0
T9	61248	1	0	0
T10	35912	0	0	0
T11	0	3	0	0
T12	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T48	778749	0	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1763306	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1905	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1763306	0	0
T1	420770	3220	0	0
T2	0	16056	0	0
T3	0	1613	0	0
T6	936157	12274	0	0
T7	0	1278	0	0
T8	0	3232	0	0
T9	0	475	0	0
T10	0	192	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T48	0	9345	0	0
T49	0	2777	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1905	0	0
T1	420770	2	0	0
T2	0	10	0	0
T3	0	2	0	0
T6	936157	8	0	0
T7	0	3	0	0
T8	0	4	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T48	0	6	0	0
T49	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T17,T19

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T17,T19
1	1	Covered	T4,T17,T19

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T17,T19

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T17,T19
1	1	Covered	T4,T17,T19

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T17,T19
0	0	1	Covered	T4,T17,T19
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T17,T19
0	0	1	Covered	T4,T17,T19
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1412125	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1445	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1412125	0	0
T1	420770	0	0	0
T4	153479	3327	0	0
T5	105769	0	0	0
T6	936157	0	0	0
T8	0	14542	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T17	0	2143	0	0
T19	0	2481	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T35	0	8796	0	0
T47	0	9377	0	0
T51	0	6988	0	0
T52	0	2614	0	0
T53	0	2422	0	0
T54	0	4155	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1445	0	0
T1	420770	0	0	0
T4	153479	4	0	0
T5	105769	0	0	0
T6	936157	0	0	0
T8	0	17	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T17	0	4	0	0
T19	0	5	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T35	0	9	0	0
T47	0	6	0	0
T51	0	4	0	0
T52	0	6	0	0
T53	0	3	0	0
T54	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T17,T19

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T17,T19
1	1	Covered	T4,T17,T19

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T17,T19

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T17,T19
1	1	Covered	T4,T17,T19

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T17,T19
0	0	1	Covered	T4,T17,T19
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T17,T19
0	0	1	Covered	T4,T17,T19
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1297690	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1291	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1297690	0	0
T1	420770	0	0	0
T4	153479	2355	0	0
T5	105769	0	0	0
T6	936157	0	0	0
T8	0	9214	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T17	0	1642	0	0
T19	0	1448	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T35	0	5648	0	0
T47	0	5144	0	0
T51	0	4977	0	0
T52	0	1292	0	0
T53	0	2400	0	0
T54	0	2422	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1291	0	0
T1	420770	0	0	0
T4	153479	3	0	0
T5	105769	0	0	0
T6	936157	0	0	0
T8	0	11	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T17	0	3	0	0
T19	0	3	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T35	0	6	0	0
T47	0	3	0	0
T51	0	3	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T10,T31

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T10,T31
1	1	Covered	T7,T10,T31

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T10,T31

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T10,T31
1	1	Covered	T7,T10,T31

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T10,T31
0	0	1	Covered	T7,T10,T31
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T10,T31
0	0	1	Covered	T7,T10,T31
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	6340754	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	6863	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6340754	0	0
T7	161242	29284	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	206	0	0
T31	0	20485	0	0
T32	0	41681	0	0
T38	0	144782	0	0
T45	0	30165	0	0
T46	0	6595	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	26560	0	0
T68	0	44242	0	0
T69	0	21527	0	0
T70	285454	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6863	0	0
T7	161242	70	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	1	0	0
T31	0	51	0	0
T32	0	51	0	0
T38	0	84	0	0
T45	0	73	0	0
T46	0	78	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	64	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	285454	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	6227207	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	6858	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6227207	0	0
T7	161242	25202	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	19626	0	0
T32	0	41471	0	0
T38	0	146517	0	0
T45	0	27126	0	0
T46	0	5986	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	38616	0	0
T68	0	43522	0	0
T69	0	21317	0	0
T70	285454	0	0	0
T71	0	15071	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6858	0	0
T7	161242	62	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	51	0	0
T32	0	51	0	0
T38	0	86	0	0
T45	0	67	0	0
T46	0	74	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	93	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	285454	0	0	0
T71	0	98	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	6271870	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	6955	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6271870	0	0
T7	161242	32317	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	18666	0	0
T32	0	41261	0	0
T38	0	110593	0	0
T45	0	29569	0	0
T46	0	5019	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	38220	0	0
T68	0	42790	0	0
T69	0	21107	0	0
T70	285454	0	0	0
T71	0	10983	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6955	0	0
T7	161242	81	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	51	0	0
T32	0	51	0	0
T38	0	65	0	0
T45	0	73	0	0
T46	0	65	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	93	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	285454	0	0	0
T71	0	72	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	6010606	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	6742	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6010606	0	0
T7	161242	28442	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	17894	0	0
T32	0	41051	0	0
T38	0	125888	0	0
T45	0	22758	0	0
T46	0	5685	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	29089	0	0
T68	0	42050	0	0
T69	0	20897	0	0
T70	285454	0	0	0
T71	0	11122	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6742	0	0
T7	161242	74	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	51	0	0
T32	0	51	0	0
T38	0	75	0	0
T45	0	57	0	0
T46	0	75	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	72	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	285454	0	0	0
T71	0	75	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T10,T31

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T10,T31
1	1	Covered	T7,T10,T31

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T10,T31

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T10,T31
1	1	Covered	T7,T10,T31

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T10,T31
0	0	1	Covered	T7,T10,T31
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T10,T31
0	0	1	Covered	T7,T10,T31
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1217916	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1222	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1217916	0	0
T7	161242	1342	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	204	0	0
T31	0	347	0	0
T32	0	959	0	0
T38	0	9910	0	0
T45	0	1316	0	0
T46	0	245	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	1553	0	0
T68	0	969	0	0
T69	0	479	0	0
T70	285454	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1222	0	0
T7	161242	3	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	6	0	0
T45	0	3	0	0
T46	0	3	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	4	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	285454	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1197471	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1224	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1197471	0	0
T7	161242	1234	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	298	0	0
T32	0	949	0	0
T38	0	9688	0	0
T45	0	1286	0	0
T46	0	215	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	1513	0	0
T68	0	940	0	0
T69	0	469	0	0
T70	285454	0	0	0
T71	0	292	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1224	0	0
T7	161242	3	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	6	0	0
T45	0	3	0	0
T46	0	3	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	4	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	285454	0	0	0
T71	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1207720	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1232	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1207720	0	0
T7	161242	1124	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	258	0	0
T32	0	939	0	0
T38	0	9497	0	0
T45	0	1256	0	0
T46	0	185	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	1473	0	0
T68	0	915	0	0
T69	0	459	0	0
T70	285454	0	0	0
T71	0	272	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1232	0	0
T7	161242	3	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	6	0	0
T45	0	3	0	0
T46	0	3	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	4	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	285454	0	0	0
T71	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T31,T32
1	1	Covered	T7,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T31,T32
0	0	1	Covered	T7,T31,T32
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1208000	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1237	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1208000	0	0
T7	161242	1274	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	319	0	0
T32	0	929	0	0
T38	0	9284	0	0
T45	0	1226	0	0
T46	0	230	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	1433	0	0
T68	0	884	0	0
T69	0	449	0	0
T70	285454	0	0	0
T71	0	252	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1237	0	0
T7	161242	3	0	0
T8	422958	0	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	6	0	0
T45	0	3	0	0
T46	0	3	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T67	0	4	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	285454	0	0	0
T71	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	6835052	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	7378	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6835052	0	0
T1	420770	3487	0	0
T2	0	17415	0	0
T3	0	708	0	0
T6	936157	12482	0	0
T7	0	29579	0	0
T8	0	710	0	0
T10	0	200	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T48	0	9501	0	0
T49	0	2936	0	0
T50	0	625	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	7378	0	0
T1	420770	2	0	0
T2	0	10	0	0
T3	0	1	0	0
T6	936157	8	0	0
T7	0	70	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	6619311	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	7323	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6619311	0	0
T1	420770	3465	0	0
T2	0	17318	0	0
T6	936157	12466	0	0
T7	0	25596	0	0
T8	0	705	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	19981	0	0
T32	0	41567	0	0
T48	0	9489	0	0
T49	0	2928	0	0
T50	0	351	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	7323	0	0
T1	420770	2	0	0
T2	0	10	0	0
T6	936157	8	0	0
T7	0	62	0	0
T8	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	51	0	0
T32	0	51	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	6724944	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	7454	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6724944	0	0
T1	420770	3437	0	0
T2	0	17229	0	0
T6	936157	12450	0	0
T7	0	32824	0	0
T8	0	698	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	19118	0	0
T32	0	41357	0	0
T48	0	9477	0	0
T49	0	2921	0	0
T50	0	342	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	7454	0	0
T1	420770	2	0	0
T2	0	10	0	0
T6	936157	8	0	0
T7	0	81	0	0
T8	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	51	0	0
T32	0	51	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	6505890	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	7282	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	6505890	0	0
T1	420770	3415	0	0
T2	0	17128	0	0
T6	936157	12434	0	0
T7	0	29141	0	0
T8	0	696	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	18295	0	0
T32	0	41147	0	0
T48	0	9465	0	0
T49	0	2913	0	0
T50	0	332	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	7282	0	0
T1	420770	2	0	0
T2	0	10	0	0
T6	936157	8	0	0
T7	0	74	0	0
T8	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	51	0	0
T32	0	51	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1724337	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1823	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1724337	0	0
T1	420770	3392	0	0
T2	0	17002	0	0
T3	0	689	0	0
T6	936157	12418	0	0
T7	0	1302	0	0
T8	0	687	0	0
T10	0	198	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T48	0	9453	0	0
T49	0	2901	0	0
T50	0	588	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1823	0	0
T1	420770	2	0	0
T2	0	10	0	0
T3	0	1	0	0
T6	936157	8	0	0
T7	0	3	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1646049	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1736	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1646049	0	0
T1	420770	3384	0	0
T2	0	16910	0	0
T6	936157	12402	0	0
T7	0	1183	0	0
T8	0	677	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	282	0	0
T32	0	945	0	0
T48	0	9441	0	0
T49	0	2884	0	0
T50	0	322	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1736	0	0
T1	420770	2	0	0
T2	0	10	0	0
T6	936157	8	0	0
T7	0	3	0	0
T8	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1669142	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1767	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1669142	0	0
T1	420770	3356	0	0
T2	0	16803	0	0
T6	936157	12386	0	0
T7	0	1085	0	0
T8	0	673	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	354	0	0
T32	0	935	0	0
T48	0	9429	0	0
T49	0	2876	0	0
T50	0	319	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1767	0	0
T1	420770	2	0	0
T2	0	10	0	0
T6	936157	8	0	0
T7	0	3	0	0
T8	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1663076	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1753	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1663076	0	0
T1	420770	3330	0	0
T2	0	16682	0	0
T6	936157	12370	0	0
T7	0	1230	0	0
T8	0	669	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	303	0	0
T32	0	925	0	0
T48	0	9417	0	0
T49	0	2862	0	0
T50	0	315	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1753	0	0
T1	420770	2	0	0
T2	0	10	0	0
T6	936157	8	0	0
T7	0	3	0	0
T8	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1706038	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1806	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1706038	0	0
T1	420770	3316	0	0
T2	0	16572	0	0
T3	0	677	0	0
T6	936157	12354	0	0
T7	0	1290	0	0
T8	0	666	0	0
T10	0	196	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T48	0	9405	0	0
T49	0	2846	0	0
T50	0	561	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1806	0	0
T1	420770	2	0	0
T2	0	10	0	0
T3	0	1	0	0
T6	936157	8	0	0
T7	0	3	0	0
T8	0	1	0	0
T10	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1658293	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1759	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1658293	0	0
T1	420770	3296	0	0
T2	0	16481	0	0
T6	936157	12338	0	0
T7	0	1171	0	0
T8	0	664	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	270	0	0
T32	0	943	0	0
T48	0	9393	0	0
T49	0	2835	0	0
T50	0	304	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1759	0	0
T1	420770	2	0	0
T2	0	10	0	0
T6	936157	8	0	0
T7	0	3	0	0
T8	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1644467	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1745	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1644467	0	0
T1	420770	3277	0	0
T2	0	16368	0	0
T6	936157	12322	0	0
T7	0	1066	0	0
T8	0	652	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	343	0	0
T32	0	933	0	0
T48	0	9381	0	0
T49	0	2815	0	0
T50	0	302	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1745	0	0
T1	420770	2	0	0
T2	0	10	0	0
T6	936157	8	0	0
T7	0	3	0	0
T8	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1612206	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1727	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1612206	0	0
T1	420770	3252	0	0
T2	0	16271	0	0
T6	936157	12306	0	0
T7	0	1197	0	0
T8	0	645	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	293	0	0
T32	0	923	0	0
T48	0	9369	0	0
T49	0	2807	0	0
T50	0	293	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1727	0	0
T1	420770	2	0	0
T2	0	10	0	0
T6	936157	8	0	0
T7	0	3	0	0
T8	0	1	0	0
T14	250574	0	0	0
T15	246356	0	0	0
T16	198312	0	0	0
T17	206254	0	0	0
T22	201826	0	0	0
T23	107047	0	0	0
T24	211126	0	0	0
T25	123089	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T48	0	6	0	0
T49	0	2	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T11,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T11,T13
1	1	Covered	T8,T11,T13

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T13
1	-	Covered	T8,T11,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T11,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T11,T13
1	1	Covered	T8,T11,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T11,T13
0	0	1	Covered	T8,T11,T13
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T11,T13
0	0	1	Covered	T8,T11,T13
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1050742572	1049273	0	0
DstReqKnown_A	6536053	5659761	0	0
SrcAckBusyChk_A	1050742572	1039	0	0
SrcBusyKnown_A	1050742572	1050309594	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1049273	0	0
T8	422958	1650	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T11	0	1115	0	0
T13	0	6704	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T58	0	1395	0	0
T60	0	1730	0	0
T62	0	1671	0	0
T70	285454	0	0	0
T72	0	2970	0	0
T73	0	2589	0	0
T74	0	2927	0	0
T75	0	2885	0	0
T76	46740	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6536053	5659761	0	0
T1	8415	8014	0	0
T4	639	239	0	0
T5	423	23	0	0
T6	19504	19097	0	0
T14	522	122	0	0
T15	502	102	0	0
T22	403	3	0	0
T23	427	27	0	0
T24	421	21	0	0
T25	491	91	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1039	0	0
T8	422958	2	0	0
T9	61248	0	0	0
T10	35912	0	0	0
T11	0	2	0	0
T13	0	4	0	0
T49	360036	0	0	0
T50	587878	0	0	0
T55	50697	0	0	0
T56	130843	0	0	0
T57	59821	0	0	0
T58	0	4	0	0
T60	0	4	0	0
T62	0	2	0	0
T70	285454	0	0	0
T72	0	2	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	46740	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050742572	1050309594	0	0
T1	420770	420715	0	0
T4	153479	153384	0	0
T5	105769	105685	0	0
T6	936157	935814	0	0
T14	250574	250493	0	0
T15	246356	246258	0	0
T22	201826	201753	0	0
T23	107047	106985	0	0
T24	211126	211054	0	0
T25	123089	122989	0	0