Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	81.25	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_auto_blk_out_ctl_cg_(4)	37.50	1	100	1	64	64
sysrst_ctrl_auto_blk_out_ctl_cg_(5)	62.50	1	100	1	64	64
sysrst_ctrl_auto_blk_out_ctl_cg_(3)	87.50	1	100	1	64	64
sysrst_ctrl_auto_blk_out_ctl_cg	100.00	1	100	1	64	64
sysrst_ctrl_auto_blk_out_ctl_cg_(1)	100.00	1	100	1	64	64
sysrst_ctrl_auto_blk_out_ctl_cg_(2)	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(4)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
37.50	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	6	6	50.00
Crosses	12	9	3	25.00

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	1	1	50.00	100	1	1	2
cp_key0_out_value	2	1	1	50.00	100	1	1	2
cp_key1_out_sel	2	1	1	50.00	100	1	1	2
cp_key1_out_value	2	1	1	50.00	100	1	1	2
cp_key2_out_sel	2	1	1	50.00	100	1	1	2
cp_key2_out_value	2	1	1	50.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	3	1	25.00	100	1	1	0
cross_key1_out_sel_value	4	3	1	25.00	100	1	1	0
cross_key2_out_sel_value	4	3	1	25.00	100	1	1	0

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(5)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(5)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	3	9	75.00
Crosses	12	6	6	50.00

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(5)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	1	1	50.00	100	1	1	2
cp_key0_out_value	2	0	2	100.00	100	1	1	2
cp_key1_out_sel	2	1	1	50.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	1	1	50.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(5)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	2	2	50.00	100	1	1	0
cross_key1_out_sel_value	4	2	2	50.00	100	1	1	0
cross_key2_out_sel_value	4	2	2	50.00	100	1	1	0

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(3)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	12	3	9	75.00

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	0	2	100.00	100	1	1	2
cp_key0_out_value	2	0	2	100.00	100	1	1	2
cp_key1_out_sel	2	0	2	100.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	0	2	100.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	1	3	75.00	100	1	1	0
cross_key1_out_sel_value	4	1	3	75.00	100	1	1	0
cross_key2_out_sel_value	4	1	3	75.00	100	1	1	0

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	12	0	12	100.00

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	0	2	100.00	100	1	1	2
cp_key0_out_value	2	0	2	100.00	100	1	1	2
cp_key1_out_sel	2	0	2	100.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	0	2	100.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key1_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key2_out_sel_value	4	0	4	100.00	100	1	1	0

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	12	0	12	100.00

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	0	2	100.00	100	1	1	2
cp_key0_out_value	2	0	2	100.00	100	1	1	2
cp_key1_out_sel	2	0	2	100.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	0	2	100.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key1_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key2_out_sel_value	4	0	4	100.00	100	1	1	0

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(2)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	12	0	12	100.00

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	0	2	100.00	100	1	1	2
cp_key0_out_value	2	0	2	100.00	100	1	1	2
cp_key1_out_sel	2	0	2	100.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	0	2	100.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key1_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key2_out_sel_value	4	0	4	100.00	100	1	1	0

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_key0_out_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[1]	1	1			T10	1

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_key0_out_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T10	1

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_key1_out_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[1]	1	1			T10	1

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_key1_out_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[1]	1	1			T10	1

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_key2_out_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T10	1

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_key2_out_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T10	1

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	3	1	25.00	3

Automatically Generated Cross Bins for cross_key0_out_sel_value

Element holes

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	2

Uncovered bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	0	1	1

Covered bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[1]	1	1			T10	1

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	3	1	25.00	3

Automatically Generated Cross Bins for cross_key1_out_sel_value

Element holes

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	--	--	2

Uncovered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[1]	auto[1]	1	1			T10	1

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	3	1	25.00	3

Automatically Generated Cross Bins for cross_key2_out_sel_value

Element holes

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	2

Uncovered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	1	1			T10	1

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_key0_out_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[1]	3	1			T10	3

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	2	1			T10	2
auto[1]	1	1			T10	1

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_key1_out_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	3	1			T10	3

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	2	1			T10	2
auto[1]	1	1			T10	1

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_key2_out_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	3	1			T10	3

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T10	1
auto[1]	2	1			T10	2

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cross_key0_out_sel_value

Element holes

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[0]]	--	--	2

Covered bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[1]	2	1			T10	2
auto[1]	auto[1]	1	1			T10	1

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cross_key1_out_sel_value

Element holes

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	2	1			T10	2
auto[1]	auto[0]	1	1			T10	1

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cross_key2_out_sel_value

Element holes

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	1	1			T10	1
auto[1]	auto[0]	2	1			T10	2

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	2	1			T10	1		T149	1
auto[1]	4	1			T10	2		T149	2

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	4	1			T10	1		T149	3
auto[1]	2	1			T10	2		-	-

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	5	1			T10	3		T149	2
auto[1]	1	1			T149	1		-	-

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	1	1			T10	1		-	-
auto[1]	5	1			T10	2		T149	3

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	1	1			T149	1		-	-
auto[1]	5	1			T10	3		T149	2

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	4	1			T10	2		T149	2
auto[1]	2	1			T10	1		T149	1

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cross_key0_out_sel_value

Uncovered bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	2	1			T10	1		T149	1
auto[0]	auto[1]	2	1			T149	2		-	-
auto[1]	auto[1]	2	1			T10	2		-	-

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cross_key1_out_sel_value

Uncovered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	1	1			T10	1		-	-
auto[1]	auto[0]	4	1			T10	2		T149	2
auto[1]	auto[1]	1	1			T149	1		-	-

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	0	1	1

Covered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[1]	4	1			T10	2		T149	2
auto[1]	auto[0]	1	1			T149	1		-	-
auto[1]	auto[1]	1	1			T10	1		-	-

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119

1

T12

3

T5

1

T9

1

auto[1]

125

1

T5

1

T9

2

T21

3

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132

1

T5

2

T9

3

T21

1

auto[1]

112

1

T12

3

T21

2

T33

2

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129

1

T12

2

T5

2

T9

2

auto[1]

115

1

T12

1

T9

1

T21

1

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125

1

T12

1

T5

2

T9

2

auto[1]

119

1

T12

2

T9

1

T21

2

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112

1

T12

3

T9

1

T10

3

auto[1]

132

1

T5

2

T9

2

T21

3

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119

1

T12

2

T9

1

T33

1

auto[1]

125

1

T12

1

T5

2

T9

2

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins

cp_key0_out_value

cp_key0_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

60

1

T5

1

T9

1

T34

1

auto[0]

auto[1]

72

1

T5

1

T9

2

T21

1

auto[1]

auto[0]

59

1

T12

3

T33

1

T10

1

auto[1]

auto[1]

53

1

T21

2

T33

1

T10

1

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins

cp_key1_out_value

cp_key1_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

62

1

T5

2

T9

1

T10

1

auto[0]

auto[1]

63

1

T12

1

T9

1

T21

1

auto[1]

auto[0]

67

1

T12

2

T9

1

T21

2

auto[1]

auto[1]

52

1

T10

2

T94

1

T193

1

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins

cp_key2_out_value

cp_key2_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

48

1

T12

2

T10

3

T35

1

auto[0]

auto[1]

71

1

T9

1

T33

1

T34

1

auto[1]

auto[0]

64

1

T12

1

T9

1

T34

1

auto[1]

auto[1]

61

1

T5

2

T9

1

T21

3

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28

1

T10

1

T32

2

T287

2

auto[1]

27

1

T9

1

T10

2

T32

1

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29

1

T9

1

T10

2

T70

3

auto[1]

26

1

T10

1

T32

3

T27

1

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26

1

T10

1

T32

1

T70

1

auto[1]

29

1

T9

1

T10

2

T32

2

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29

1

T9

1

T10

2

T32

1

auto[1]

26

1

T10

1

T32

2

T70

2

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29

1

T10

2

T32

1

T27

3

auto[1]

26

1

T9

1

T10

1

T32

2

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32

1

T9

1

T10

2

T32

1

auto[1]

23

1

T10

1

T32

2

T27

2

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins

cp_key0_out_value

cp_key0_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

13

1

T287

1

T149

1

T73

1

auto[0]

auto[1]

16

1

T9

1

T10

2

T70

3

auto[1]

auto[0]

15

1

T10

1

T32

2

T287

1

auto[1]

auto[1]

11

1

T32

1

T27

1

T269

1

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins

cp_key1_out_value

cp_key1_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

13

1

T10

1

T70

1

T27

1

auto[0]

auto[1]

16

1

T9

1

T10

1

T32

1

auto[1]

auto[0]

13

1

T32

1

T287

1

T66

1

auto[1]

auto[1]

13

1

T10

1

T32

1

T70

2

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins

cp_key2_out_value

cp_key2_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

15

1

T10

1

T27

1

T269

1

auto[0]

auto[1]

17

1

T9

1

T10

1

T32

1

auto[1]

auto[0]

14

1

T10

1

T32

1

T27

2

auto[1]

auto[1]

9

1

T32

1

T269

2

T66

1

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12

1

T9

1

T287

3

T149

1

auto[1]

9

1

T9

2

T149

2

T73

2

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12

1

T9

2

T287

3

T149

2

auto[1]

9

1

T9

1

T149

1

T73

3

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13

1

T9

1

T287

1

T149

2

auto[1]

8

1

T9

2

T287

2

T149

1

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12

1

T9

2

T149

2

T73

2

auto[1]

9

1

T9

1

T287

3

T149

1

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10

1

T9

1

T287

2

T149

2

auto[1]

11

1

T9

2

T287

1

T149

1

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11

1

T9

2

T287

2

T149

1

auto[1]

10

1

T9

1

T287

1

T149

2

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins

cp_key0_out_value

cp_key0_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

9

1

T9

1

T287

3

T149

1

auto[0]

auto[1]

3

1

T9

1

T149

1

T85

1

auto[1]

auto[0]

3

1

T73

1

T72

1

T85

1

auto[1]

auto[1]

6

1

T9

1

T149

1

T73

2

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins

cp_key1_out_value

cp_key1_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

9

1

T9

1

T149

1

T73

2

auto[0]

auto[1]

3

1

T9

1

T149

1

T274

1

auto[1]

auto[0]

4

1

T287

1

T149

1

T274

1

auto[1]

auto[1]

5

1

T9

1

T287

2

T73

1

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins

cp_key2_out_value

cp_key2_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

4

1

T287

1

T149

1

T274

1

auto[0]

auto[1]

7

1

T9

2

T287

1

T73

2

auto[1]

auto[0]

6

1

T9

1

T287

1

T149

1

auto[1]

auto[1]

4

1

T149

1

T72

2

T85

1