Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1817

1

T1

13

T8

4

T9

2

auto[1]

575

1

T1

3

T8

2

T9

11

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1820

1

T1

14

T8

2

T9

8

auto[1]

572

1

T1

2

T8

4

T9

5

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1808

1

T1

13

T8

6

T9

9

auto[1]

584

1

T1

3

T9

4

T22

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1854

1

T1

12

T8

2

T9

7

auto[1]

538

1

T1

4

T8

4

T9

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2186

1

T1

14

T8

6

T9

13

auto[1]

206

1

T1

2

T25

45

T38

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2134

1

T1

16

T8

6

T9

13

auto[1]

258

1

T25

54

T58

1

T67

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2187

1

T1

14

T8

6

T9

13

auto[1]

205

1

T1

2

T38

2

T57

5

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2175

1

T1

15

T8

6

T9

13

auto[1]

217

1

T1

1

T25

9

T26

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2319

1

T1

12

T8

6

T9

13

auto[1]

73

1

T1

4

T22

1

T26

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1741

1

T1

15

T8

6

T9

3

auto[1]

651

1

T1

1

T9

10

T11

5

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	851	1			T8	6		T9	11		T11	5
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	49	1			T58	8		T74	2		T67	8
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	20	1			T1	3		T22	1		T234	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T204	1		-	-		-	-
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	91	1			T96	1		T234	3		T323	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	30	1			T323	2		T183	3		T203	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	13	1			T26	1		T165	3		T316	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T332	2		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	55	1			T58	5		T67	6		T109	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	15	1			T38	2		T333	1		T334	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T203	2		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	5	1			T1	1		T219	1		T335	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	28	1			T57	5		T221	3		T183	5
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	5	1			T234	1		T336	4		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T337	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	67	1			T96	3		T241	30		T240	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	81	1			T25	45		T241	9		T313	10
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	7	1			T338	4		T339	3		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	18	1			T25	9		T231	2		T340	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T67	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	1	1			T198	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T58	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	52	1			T221	5		T313	30		T316	3
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T337	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	11	1			T313	10		T222	1		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T341	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

107

1

T27

2

T98

2

T313

15

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

133

1

T25

15

T57

5

T67

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

81

1

T9

4

T11

5

T241

15

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

121

1

T234

2

T221

5

T313

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

43

1

T8

2

T28

2

T239

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T27

1

T233

4

T186

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T58

5

T235

1

T236

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

109

1

T58

1

T165

3

T323

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

65

1

T26

1

T96

1

T98

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

68

1

T25

24

T76

5

T223

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T314

2

T242

6

T80

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

57

1

T25

15

T28

1

T74

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T1

3

T9

2

T61

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T314

2

T185

4

T244

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T79

1

T238

1

T342

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

73

1

T8

2

T58

8

T98

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T96

1

T235

3

T149

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

76

1

T9

1

T109

2

T221

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T343

1

T344

3

T72

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T1

1

T8

2

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T28

1

T239

3

T149

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

26

1

T38

2

T96

1

T225

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T9

3

T27

1

T272

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

75

1

T62

4

T239

4

T224

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T234

3

T316

2

T185

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

24

1

T62

1

T314

2

T154

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T314

2

T338

9

T345

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

12

1

T28

1

T239

2

T272

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T22

1

T27

1

T66

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T235

2

T224

1

T246

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T154

1

T79

1

T246

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded