Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T5

10

T8

17

T10

12

auto[1]

1062

1

T5

10

T8

23

T10

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

520

1

T5

4

T8

11

T10

3

from_0to1

517

1

T5

4

T8

10

T10

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T5

12

T8

23

T10

9

auto[1]

1026

1

T5

8

T8

17

T10

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T5

12

T8

21

T10

12

auto[1]

1079

1

T5

8

T8

19

T10

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T5

1

T8

1

T28

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T8

2

T53

1

T54

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T8

3

T10

1

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T5

1

T53

1

T293

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T8

1

T54

3

T136

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T5

2

T8

1

T53

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T10

1

T28

3

T136

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T8

1

T10

1

T53

2

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T8

1

T10

1

T54

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T5

1

T8

1

T293

2

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T5

1

T8

2

T170

1

auto[1]

from_1to0

auto[1]

auto[1]

51

1

T8

1

T10

1

T53

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T8

1

T53

1

T293

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T5

1

T8

1

T53

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T8

3

T293

1

T355

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T5

1

T8

2

T10

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T5

6

T8

14

T10

8

auto[1]

1061

1

T5

14

T8

26

T10

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

505

1

T5

5

T8

8

T10

6

from_0to1

506

1

T5

4

T8

7

T10

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T5

10

T8

22

T10

12

auto[1]

1068

1

T5

10

T8

18

T10

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042

1

T5

10

T8

18

T10

10

auto[1]

1094

1

T5

10

T8

22

T10

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T8

1

T10

2

T28

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T5

1

T8

1

T53

3

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T5

1

T54

1

T293

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T8

2

T10

1

T53

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T8

2

T170

1

T87

3

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T293

1

T355

2

T170

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T10

1

T53

1

T54

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T10

1

T28

2

T170

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T5

1

T8

1

T53

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T5

2

T8

2

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T8

1

T10

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T10

1

T54

1

T136

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T5

3

T8

3

T10

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T5

1

T8

1

T10

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T8

1

T10

1

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T53

2

T54

3

T355

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T5

9

T8

24

T10

8

auto[1]

1082

1

T5

11

T8

16

T10

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T5

5

T8

11

T10

3

from_0to1

512

1

T5

5

T8

12

T10

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T5

7

T8

18

T10

11

auto[1]

1016

1

T5

13

T8

22

T10

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T5

10

T8

21

T10

7

auto[1]

1084

1

T5

10

T8

19

T10

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T8

2

T53

1

T54

1

auto[0]

from_1to0

auto[0]

auto[1]

83

1

T5

1

T10

1

T28

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T5

1

T8

2

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T8

1

T53

1

T54

2

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T5

1

T8

2

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T5

1

T8

2

T136

2

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T8

1

T170

1

T27

4

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T8

4

T53

1

T54

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T8

2

T54

1

T293

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T5

1

T8

1

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T5

1

T8

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T5

1

T8

2

T10

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T5

1

T8

2

T10

2

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T8

1

T53

3

T28

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T5

1

T10

1

T28

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T5

1

T54

1

T355

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T5

7

T8

27

T10

12

auto[1]

1069

1

T5

13

T8

13

T10

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

510

1

T5

2

T8

9

T10

7

from_0to1

505

1

T5

3

T8

8

T10

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T5

14

T8

17

T10

8

auto[1]

1059

1

T5

6

T8

23

T10

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T5

11

T8

17

T10

9

auto[1]

1084

1

T5

9

T8

23

T10

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T8

2

T53

1

T54

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T8

1

T53

1

T293

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T8

1

T53

1

T293

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T8

2

T10

3

T355

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T8

1

T10

2

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T8

1

T10

1

T53

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T8

1

T10

1

T28

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T8

4

T10

1

T28

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T8

1

T10

2

T53

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T5

2

T293

1

T28

2

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T54

1

T293

1

T136

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T8

2

T10

2

T293

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T5

1

T53

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T8

1

T170

1

T87

4

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T10

1

T293

2

T28

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T5

2

T293

1

T28

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T5

12

T8

13

T10

8

auto[1]

1055

1

T5

8

T8

27

T10

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T5

6

T8

10

T10

5

from_0to1

513

1

T5

6

T8

11

T10

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T5

12

T8

23

T10

12

auto[1]

1075

1

T5

8

T8

17

T10

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T5

10

T8

31

T10

15

auto[1]

1085

1

T5

10

T8

9

T10

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T5

2

T8

1

T53

2

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T53

1

T28

1

T136

2

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T8

1

T54

1

T136

2

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T5

1

T293

2

T89

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T5

2

T8

1

T10

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T5

1

T8

1

T10

2

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T8

2

T10

1

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T5

1

T54

2

T293

2

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T5

1

T8

2

T10

2

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T8

1

T28

1

T136

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T8

4

T10

1

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

78

1

T5

2

T8

1

T10

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T5

1

T8

3

T10

2

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T5

1

T8

1

T293

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T8

2

T28

1

T355

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T8

1

T54

1

T28

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T5

12

T8

24

T10

6

auto[1]

1041

1

T5

8

T8

16

T10

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

534

1

T5

5

T8

11

T10

6

from_0to1

538

1

T5

6

T8

11

T10

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T5

14

T8

24

T10

11

auto[1]

1016

1

T5

6

T8

16

T10

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T5

8

T8

20

T10

9

auto[1]

1047

1

T5

12

T8

20

T10

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T8

2

T54

1

T87

1

auto[0]

from_1to0

auto[0]

auto[1]

93

1

T5

2

T8

2

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T8

1

T53

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T8

1

T54

1

T61

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T5

1

T8

3

T10

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T5

2

T8

1

T10

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T5

1

T8

1

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T5

1

T8

3

T53

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T5

1

T8

1

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T5

1

T8

3

T10

2

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T8

1

T10

2

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T5

1

T53

2

T54

1

auto[1]

from_0to1

auto[0]

auto[0]

90

1

T8

1

T10

2

T53

1

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T10

1

T53

1

T54

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T5

1

T8

1

T10

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T8

1

T87

1

T89

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T5

10

T8

15

T10

10

auto[1]

1092

1

T5

10

T8

25

T10

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

508

1

T5

4

T8

11

T10

4

from_0to1

518

1

T5

5

T8

11

T10

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T5

10

T8

22

T10

13

auto[1]

1068

1

T5

10

T8

18

T10

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T5

11

T8

15

T10

8

auto[1]

1064

1

T5

9

T8

25

T10

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T5

1

T8

1

T28

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T5

1

T8

2

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T136

2

T87

1

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T8

2

T10

1

T53

1

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T8

1

T10

2

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T8

2

T10

1

T53

1

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T5

1

T8

1

T54

2

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T5

1

T8

1

T53

2

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T8

2

T28

1

T136

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T5

1

T8

2

T293

2

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T5

1

T8

1

T10

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T8

1

T10

1

T53

2

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T5

2

T8

2

T10

1

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T8

1

T355

1

T87

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T5

1

T8

1

T293

2

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T8

2

T53

1

T54

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T5

10

T8

21

T10

12

auto[1]

1052

1

T5

10

T8

19

T10

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

506

1

T5

4

T8

10

T10

4

from_0to1

517

1

T5

4

T8

10

T10

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T5

13

T8

17

T10

11

auto[1]

1073

1

T5

7

T8

23

T10

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T5

10

T8

16

T10

8

auto[1]

1078

1

T5

10

T8

24

T10

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T5

1

T8

1

T54

2

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T8

2

T53

2

T28

2

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T8

2

T10

1

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T10

1

T53

1

T54

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T8

1

T28

1

T136

1

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T8

2

T53

1

T54

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T10

1

T293

1

T28

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T5

1

T8

3

T10

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T5

2

T8

2

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T5

1

T8

1

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T8

1

T54

2

T136

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T8

1

T293

2

T136

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T5

1

T54

1

T28

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T54

1

T293

1

T28

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T5

1

T8

2

T53

2

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T5

1

T8

2

T10

1