Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153201	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118610

1

T1

310

T4

122

T2

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	139336	1			T1	259		T4	3		T2	7
values[0x0]	65633	1			T1	304		T4	207		T2	2
values[0x1]	66842	1			T1	322		T4	217		T2	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124426	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147385

1

T1

390

T4

149

T2

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2542	1			T14	2		T9	2		T33	1
valid_sources[0x01]	789	1			T9	3		T22	3		T293	7
valid_sources[0x02]	1059	1			T15	1		T9	2		T22	5
valid_sources[0x03]	902	1			T9	6		T33	1		T22	3
valid_sources[0x04]	834	1			T8	4		T9	1		T22	1
valid_sources[0x05]	755	1			T14	5		T9	2		T22	7
valid_sources[0x06]	1037	1			T13	5		T5	3		T9	4
valid_sources[0x07]	934	1			T15	1		T8	118		T9	3
valid_sources[0x08]	888	1			T14	1		T3	2		T9	1
valid_sources[0x09]	952	1			T9	2		T22	7		T54	11
valid_sources[0x0a]	878	1			T15	1		T22	5		T95	1
valid_sources[0x0b]	950	1			T9	3		T95	1		T28	3
valid_sources[0x0c]	927	1			T2	4		T9	2		T22	2
valid_sources[0x0d]	786	1			T13	1		T14	1		T5	3
valid_sources[0x0e]	1257	1			T9	5		T22	1		T46	1
valid_sources[0x0f]	965	1			T9	2		T22	3		T25	16
valid_sources[0x10]	1628	1			T8	345		T9	2		T22	4
valid_sources[0x11]	1573	1			T9	2		T22	4		T54	1
valid_sources[0x12]	902	1			T9	4		T22	7		T54	1
valid_sources[0x13]	868	1			T9	5		T22	5		T95	1
valid_sources[0x14]	1208	1			T9	5		T22	4		T54	3
valid_sources[0x15]	794	1			T14	3		T3	1		T9	7
valid_sources[0x16]	1032	1			T22	9		T95	1		T25	5
valid_sources[0x17]	1206	1			T9	1		T22	3		T25	26
valid_sources[0x18]	903	1			T291	2		T114	1		T25	5
valid_sources[0x19]	739	1			T9	4		T22	2		T45	1
valid_sources[0x1a]	1160	1			T9	3		T22	1		T34	15
valid_sources[0x1b]	1162	1			T12	2		T14	5		T15	1
valid_sources[0x1c]	850	1			T13	1		T9	3		T22	12
valid_sources[0x1d]	991	1			T9	2		T22	3		T53	2
valid_sources[0x1e]	873	1			T8	4		T9	3		T10	20
valid_sources[0x1f]	801	1			T9	3		T22	8		T114	1
valid_sources[0x20]	1169	1			T13	2		T3	1		T8	97
valid_sources[0x21]	736	1			T13	2		T14	6		T6	3
valid_sources[0x22]	707	1			T14	7		T9	4		T22	1
valid_sources[0x23]	1102	1			T14	3		T9	1		T22	2
valid_sources[0x24]	926	1			T9	4		T95	1		T53	1
valid_sources[0x25]	911	1			T9	4		T22	3		T53	2
valid_sources[0x26]	1537	1			T9	4		T33	1		T54	7
valid_sources[0x27]	931	1			T6	1		T9	1		T22	8
valid_sources[0x28]	1491	1			T12	1		T14	4		T9	3
valid_sources[0x29]	2077	1			T9	3		T53	1		T39	6
valid_sources[0x2a]	947	1			T13	6		T14	1		T9	2
valid_sources[0x2b]	1389	1			T22	9		T53	1		T20	1
valid_sources[0x2c]	921	1			T15	1		T9	8		T22	2
valid_sources[0x2d]	956	1			T14	8		T9	4		T53	1
valid_sources[0x2e]	883	1			T9	1		T22	1		T53	1
valid_sources[0x2f]	785	1			T9	5		T22	3		T267	9
valid_sources[0x30]	849	1			T14	2		T9	3		T22	1
valid_sources[0x31]	807	1			T9	4		T22	1		T95	4
valid_sources[0x32]	854	1			T6	2		T9	4		T22	10
valid_sources[0x33]	984	1			T14	1		T9	2		T22	2
valid_sources[0x34]	859	1			T5	84		T9	9		T22	4
valid_sources[0x35]	819	1			T9	1		T43	3		T25	2
valid_sources[0x36]	1749	1			T8	11		T9	6		T22	5
valid_sources[0x37]	892	1			T22	3		T356	1		T25	2
valid_sources[0x38]	807	1			T9	3		T22	4		T117	1
valid_sources[0x39]	981	1			T9	4		T22	1		T44	1
valid_sources[0x3a]	1121	1			T14	3		T9	2		T22	4
valid_sources[0x3b]	865	1			T12	1		T9	5		T22	2
valid_sources[0x3c]	898	1			T14	3		T3	1		T22	6
valid_sources[0x3d]	646	1			T9	1		T22	9		T95	1
valid_sources[0x3e]	907	1			T15	2		T8	2		T28	1
valid_sources[0x3f]	1018	1			T9	6		T35	1		T113	1
valid_sources[0x40]	802	1			T9	5		T22	2		T230	2
valid_sources[0x41]	939	1			T14	8		T9	1		T22	1
valid_sources[0x42]	876	1			T9	4		T53	1		T293	1
valid_sources[0x43]	956	1			T14	10		T9	3		T22	2
valid_sources[0x44]	1240	1			T9	2		T22	1		T53	1
valid_sources[0x45]	865	1			T9	3		T22	16		T25	11
valid_sources[0x46]	1698	1			T9	4		T22	2		T43	1
valid_sources[0x47]	777	1			T14	2		T9	3		T22	2
valid_sources[0x48]	1503	1			T15	1		T9	4		T22	4
valid_sources[0x49]	872	1			T14	5		T9	4		T22	5
valid_sources[0x4a]	1150	1			T8	20		T9	3		T22	1
valid_sources[0x4b]	757	1			T15	1		T9	3		T22	4
valid_sources[0x4c]	824	1			T3	2		T8	8		T9	3
valid_sources[0x4d]	2349	1			T9	3		T22	5		T10	80
valid_sources[0x4e]	1712	1			T9	4		T22	6		T54	7
valid_sources[0x4f]	2075	1			T14	6		T9	7		T22	3
valid_sources[0x50]	798	1			T13	7		T9	3		T33	2
valid_sources[0x51]	957	1			T12	1		T9	3		T22	7
valid_sources[0x52]	1166	1			T9	1		T22	2		T267	13
valid_sources[0x53]	986	1			T9	2		T22	1		T95	4
valid_sources[0x54]	737	1			T14	3		T8	10		T9	5
valid_sources[0x55]	1531	1			T9	4		T22	1		T267	1
valid_sources[0x56]	1041	1			T9	4		T33	1		T22	3
valid_sources[0x57]	1220	1			T5	196		T9	1		T22	1
valid_sources[0x58]	774	1			T9	4		T22	2		T95	1
valid_sources[0x59]	984	1			T8	4		T9	5		T22	8
valid_sources[0x5a]	1089	1			T14	3		T9	3		T22	9
valid_sources[0x5b]	1444	1			T22	1		T25	5		T28	2
valid_sources[0x5c]	1035	1			T5	20		T53	1		T28	4
valid_sources[0x5d]	1096	1			T95	2		T293	4		T50	2
valid_sources[0x5e]	887	1			T9	1		T22	2		T118	1
valid_sources[0x5f]	1830	1			T9	1		T22	1		T228	1
valid_sources[0x60]	1117	1			T9	3		T22	3		T53	1
valid_sources[0x61]	1395	1			T14	1		T9	4		T22	4
valid_sources[0x62]	1024	1			T13	5		T14	1		T9	4
valid_sources[0x63]	920	1			T9	4		T22	2		T28	3
valid_sources[0x64]	879	1			T9	3		T22	4		T104	9
valid_sources[0x65]	957	1			T13	4		T9	4		T22	1
valid_sources[0x66]	728	1			T5	5		T9	1		T22	3
valid_sources[0x67]	933	1			T13	1		T3	1		T22	3
valid_sources[0x68]	901	1			T9	2		T33	1		T22	4
valid_sources[0x69]	1223	1			T9	3		T22	3		T267	2
valid_sources[0x6a]	1513	1			T5	10		T22	3		T47	1
valid_sources[0x6b]	992	1			T9	3		T95	1		T54	3
valid_sources[0x6c]	942	1			T12	1		T9	4		T22	8
valid_sources[0x6d]	780	1			T9	8		T33	1		T22	3
valid_sources[0x6e]	1028	1			T14	2		T9	4		T22	2
valid_sources[0x6f]	903	1			T9	1		T53	3		T54	3
valid_sources[0x70]	998	1			T9	3		T22	3		T95	4
valid_sources[0x71]	2456	1			T9	2		T30	1		T52	7
valid_sources[0x72]	1133	1			T9	1		T22	9		T53	4
valid_sources[0x73]	851	1			T9	1		T22	5		T267	5
valid_sources[0x74]	937	1			T14	8		T9	5		T22	4
valid_sources[0x75]	1240	1			T9	2		T22	4		T95	5
valid_sources[0x76]	941	1			T14	4		T9	1		T22	1
valid_sources[0x77]	1024	1			T13	1		T9	5		T22	12
valid_sources[0x78]	967	1			T9	3		T22	5		T293	3
valid_sources[0x79]	885	1			T8	2		T9	2		T22	4
valid_sources[0x7a]	1092	1			T9	2		T267	5		T25	8
valid_sources[0x7b]	1109	1			T14	7		T9	11		T22	4
valid_sources[0x7c]	1550	1			T9	2		T22	7		T95	1
valid_sources[0x7d]	846	1			T14	1		T293	4		T28	5
valid_sources[0x7e]	1522	1			T9	3		T22	1		T43	1
valid_sources[0x7f]	929	1			T9	5		T33	2		T22	2
valid_sources[0x80]	1022	1			T12	1		T14	8		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63876

1

T1

131

T4

1

T2

1

values[0x0]

all_enables

biggest_size

31898

1

T1

125

T4

84

T2

2

values[0x1]

all_enables

biggest_size

22836

1

T1

54

T4

37

T12

1