Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T5,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T12,T5,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T5,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T9
1	0	Covered	T1,T4,T2
1	1	Covered	T12,T5,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T9
0	1	Covered	T64,T66,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T5,T9
0	1	Covered	T12,T5,T9
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T5,T9
1	-	Covered	T12,T5,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T5,T9
DetectSt	168	Covered	T12,T5,T9
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T12,T5,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T5,T9
DebounceSt->IdleSt	163	Covered	T5,T9,T10
DetectSt->IdleSt	186	Covered	T64,T66,T80
DetectSt->StableSt	191	Covered	T12,T5,T9
IdleSt->DebounceSt	148	Covered	T12,T5,T9
StableSt->IdleSt	206	Covered	T12,T5,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T5,T9
0	1	Covered	T12,T5,T9
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T5,T9
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T5,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T5,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T35,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T5,T9
DetectSt	-	-	-	-	1	-	-	Covered	T64,T66,T80
DetectSt	-	-	-	-	0	1	-	Covered	T12,T5,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T5,T9
StableSt	-	-	-	-	-	-	0	Covered	T12,T5,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	309	0	0
CntIncr_A	7311466	181564	0	0
CntNoWrap_A	7311466	6613592	0	0
DetectStDropOut_A	7311466	4	0	0
DetectedOut_A	7311466	882	0	0
DetectedPulseOut_A	7311466	138	0	0
DisabledIdleSt_A	7311466	6425162	0	0
DisabledNoDetection_A	7311466	6427579	0	0
EnterDebounceSt_A	7311466	173	0	0
EnterDetectSt_A	7311466	142	0	0
EnterStableSt_A	7311466	138	0	0
PulseIsPulse_A	7311466	138	0	0
StayInStableSt	7311466	744	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7311466	7039	0	0
gen_low_level_sva.LowLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	138	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	309	0	0
T3	645	0	0	0
T5	6258	4	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	6	0	0
T10	0	14	0	0
T12	659	2	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T21	0	4	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	181564	0	0
T3	645	0	0	0
T5	6258	2876	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	2943	0	0
T10	0	402	0	0
T12	659	67	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T21	0	1713	0	0
T33	0	36128	0	0
T34	0	32	0	0
T35	0	45	0	0
T36	0	15	0	0
T37	0	49	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613592	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3370	0	0
T6	482	81	0	0
T12	659	256	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	4	0	0
T27	25260	0	0	0
T61	13684	0	0	0
T64	660	1	0	0
T66	0	1	0	0
T80	0	1	0	0
T85	0	1	0	0
T86	429	0	0	0
T87	507	0	0	0
T88	800	0	0	0
T89	3543	0	0	0
T90	3441	0	0	0
T91	429	0	0	0
T92	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	882	0	0
T3	645	0	0	0
T5	6258	18	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	7	0	0
T10	0	37	0	0
T12	659	4	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T21	0	19	0	0
T33	0	19	0	0
T34	0	13	0	0
T35	0	11	0	0
T36	0	1	0	0
T37	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	138	0	0
T3	645	0	0	0
T5	6258	2	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	3	0	0
T10	0	6	0	0
T12	659	1	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T21	0	2	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6425162	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	376	0	0
T6	482	81	0	0
T12	659	146	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6427579	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	384	0	0
T6	482	82	0	0
T12	659	147	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	173	0	0
T3	645	0	0	0
T5	6258	3	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	4	0	0
T10	0	8	0	0
T12	659	1	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T21	0	2	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	142	0	0
T3	645	0	0	0
T5	6258	2	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	3	0	0
T10	0	6	0	0
T12	659	1	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T21	0	2	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	138	0	0
T3	645	0	0	0
T5	6258	2	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	3	0	0
T10	0	6	0	0
T12	659	1	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T21	0	2	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	138	0	0
T3	645	0	0	0
T5	6258	2	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	3	0	0
T10	0	6	0	0
T12	659	1	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T21	0	2	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	744	0	0
T3	645	0	0	0
T5	6258	16	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	4	0	0
T10	0	31	0	0
T12	659	3	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T21	0	17	0	0
T33	0	16	0	0
T34	0	12	0	0
T35	0	10	0	0
T37	0	3	0	0
T94	0	12	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	7039	0	0
T1	13960	24	0	0
T2	647	1	0	0
T3	645	0	0	0
T4	4567	22	0	0
T5	6258	17	0	0
T6	482	1	0	0
T7	0	14	0	0
T8	0	50	0	0
T12	659	3	0	0
T13	1385	8	0	0
T14	2733	22	0	0
T15	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	138	0	0
T3	645	0	0	0
T5	6258	2	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	3	0	0
T10	0	6	0	0
T12	659	1	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T21	0	2	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T7,T10,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T7,T10,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T7,T10,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T20
1	0	Covered	T1,T4,T2
1	1	Covered	T7,T10,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T20,T43
0	1	Covered	T10,T27,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T20,T43
0	1	Unreachable
1	0	Covered	T7,T20,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T20
DetectSt	168	Covered	T7,T10,T20
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T7,T20,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T20
DebounceSt->IdleSt	163	Covered	T39,T59,T60
DetectSt->IdleSt	186	Covered	T10,T27,T73
DetectSt->StableSt	191	Covered	T7,T20,T43
IdleSt->DebounceSt	148	Covered	T7,T10,T20
StableSt->IdleSt	206	Covered	T7,T20,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T20
0	1	Covered	T7,T10,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T20
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T59,T60,T27
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T20
DetectSt	-	-	-	-	1	-	-	Covered	T10,T27,T73
DetectSt	-	-	-	-	0	1	-	Covered	T7,T20,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T20,T43
StableSt	-	-	-	-	-	-	0	Covered	T7,T20,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	187	0	0
CntIncr_A	7311466	123300	0	0
CntNoWrap_A	7311466	6613714	0	0
DetectStDropOut_A	7311466	13	0	0
DetectedOut_A	7311466	351601	0	0
DetectedPulseOut_A	7311466	64	0	0
DisabledIdleSt_A	7311466	4963722	0	0
DisabledNoDetection_A	7311466	4966188	0	0
EnterDebounceSt_A	7311466	111	0	0
EnterDetectSt_A	7311466	77	0	0
EnterStableSt_A	7311466	64	0	0
PulseIsPulse_A	7311466	64	0	0
StayInStableSt	7311466	351537	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7311466	7039	0	0
gen_low_level_sva.LowLevelEvent_A	7311466	6616370	0	0
gen_sticky_sva.StableStDropOut_A	7311466	1129387	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	187	0	0
T7	2218	4	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	4	0	0
T20	0	2	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	2	0	0
T41	817	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T59	0	2	0	0
T60	0	3	0	0
T61	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	123300	0	0
T7	2218	104	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	42	0	0
T20	0	74	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	12	0	0
T41	817	0	0	0
T43	0	28	0	0
T44	0	61	0	0
T45	0	58	0	0
T59	0	182	0	0
T60	0	192	0	0
T61	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613714	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	13	0	0
T10	19176	2	0	0
T11	15749	0	0	0
T27	0	1	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T46	555	0	0	0
T53	506	0	0	0
T72	0	3	0	0
T73	0	2	0	0
T85	0	2	0	0
T95	451	0	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	866	0	0	0
T104	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	351601	0	0
T7	2218	812	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	222	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	52	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	125	0	0
T44	0	243	0	0
T45	0	41	0	0
T61	0	212	0	0
T97	0	231	0	0
T98	0	564	0	0
T99	0	435	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	64	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T61	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	4963722	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	4966188	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	111	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	2	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	2	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	0	2	0	0
T60	0	3	0	0
T61	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	77	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	2	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	3	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T61	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	64	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T61	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	64	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T61	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	351537	0	0
T7	2218	810	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	221	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	50	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	124	0	0
T44	0	242	0	0
T45	0	40	0	0
T61	0	211	0	0
T97	0	229	0	0
T98	0	563	0	0
T99	0	434	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	7039	0	0
T1	13960	24	0	0
T2	647	1	0	0
T3	645	0	0	0
T4	4567	22	0	0
T5	6258	17	0	0
T6	482	1	0	0
T7	0	14	0	0
T8	0	50	0	0
T12	659	3	0	0
T13	1385	8	0	0
T14	2733	22	0	0
T15	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1129387	0	0
T7	2218	193	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	58	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	571	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	720	0	0
T44	0	167	0	0
T45	0	32	0	0
T61	0	342	0	0
T97	0	206	0	0
T98	0	102	0	0
T99	0	83906	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T13,T14
1	1	Covered	T2,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T7,T10,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T7,T10,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T7,T10,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T20
1	0	Covered	T2,T13,T14
1	1	Covered	T7,T10,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T20
0	1	Covered	T60,T71,T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T20
0	1	Unreachable
1	0	Covered	T7,T10,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T20
DetectSt	168	Covered	T7,T10,T20
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T7,T10,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T20
DebounceSt->IdleSt	163	Covered	T45,T39,T60
DetectSt->IdleSt	186	Covered	T60,T71,T72
DetectSt->StableSt	191	Covered	T7,T10,T20
IdleSt->DebounceSt	148	Covered	T7,T10,T20
StableSt->IdleSt	206	Covered	T7,T10,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T20
0	1	Covered	T7,T10,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T20
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T20
IdleSt	0	-	-	-	-	-	-	Covered	T2,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T60,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T20
DetectSt	-	-	-	-	1	-	-	Covered	T60,T71,T72
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T20
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	192	0	0
CntIncr_A	7311466	248126	0	0
CntNoWrap_A	7311466	6613709	0	0
DetectStDropOut_A	7311466	11	0	0
DetectedOut_A	7311466	686139	0	0
DetectedPulseOut_A	7311466	58	0	0
DisabledIdleSt_A	7311466	4963722	0	0
DisabledNoDetection_A	7311466	4966188	0	0
EnterDebounceSt_A	7311466	124	0	0
EnterDetectSt_A	7311466	69	0	0
EnterStableSt_A	7311466	58	0	0
PulseIsPulse_A	7311466	58	0	0
StayInStableSt	7311466	686081	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_sticky_sva.StableStDropOut_A	7311466	654145	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	192	0	0
T7	2218	4	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	2	0	0
T20	0	2	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	2	0	0
T41	817	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T59	0	2	0	0
T60	0	5	0	0
T61	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	248126	0	0
T7	2218	24	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	100	0	0
T20	0	14	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	13	0	0
T41	817	0	0	0
T43	0	93	0	0
T44	0	72	0	0
T45	0	42	0	0
T59	0	32	0	0
T60	0	201	0	0
T61	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613709	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	11	0	0
T60	3148	2	0	0
T64	660	0	0	0
T67	22120	0	0	0
T70	7130	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T74	10796	0	0	0
T86	429	0	0	0
T87	507	0	0	0
T88	800	0	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	0	3	0	0
T108	412	0	0	0
T109	11130	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	686139	0	0
T7	2218	178	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	191	0	0
T20	0	53	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	430	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	677	0	0
T44	0	316	0	0
T59	0	156	0	0
T61	0	475	0	0
T97	0	17	0	0
T98	0	405	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	58	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	1	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	3	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	4963722	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	4966188	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	124	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	1	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	2	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	0	1	0	0
T60	0	3	0	0
T61	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	69	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	1	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	3	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T97	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	58	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	1	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	3	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	58	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	1	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	3	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	686081	0	0
T7	2218	176	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	190	0	0
T20	0	52	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	427	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	676	0	0
T44	0	315	0	0
T59	0	155	0	0
T61	0	474	0	0
T97	0	15	0	0
T98	0	404	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	654145	0	0
T7	2218	912	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	103	0	0
T20	0	283	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	443	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	94	0	0
T44	0	72	0	0
T59	0	486	0	0
T61	0	81	0	0
T97	0	568	0	0
T98	0	247	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T7,T10,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T7,T10,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T7,T20,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T20
1	0	Covered	T1,T4,T2
1	1	Covered	T7,T10,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T20,T43
0	1	Covered	T45,T61,T69
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T20,T43
0	1	Unreachable
1	0	Covered	T7,T20,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T20
DetectSt	168	Covered	T7,T20,T43
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T7,T20,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T20,T43
DebounceSt->IdleSt	163	Covered	T10,T39,T27
DetectSt->IdleSt	186	Covered	T45,T61,T69
DetectSt->StableSt	191	Covered	T7,T20,T43
IdleSt->DebounceSt	148	Covered	T7,T10,T20
StableSt->IdleSt	206	Covered	T7,T20,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T20
0	1	Covered	T7,T10,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T20,T43
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T20,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T27,T97
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T20
DetectSt	-	-	-	-	1	-	-	Covered	T45,T61,T69
DetectSt	-	-	-	-	0	1	-	Covered	T7,T20,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T20,T43
StableSt	-	-	-	-	-	-	0	Covered	T7,T20,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	203	0	0
CntIncr_A	7311466	79532	0	0
CntNoWrap_A	7311466	6613698	0	0
DetectStDropOut_A	7311466	17	0	0
DetectedOut_A	7311466	375080	0	0
DetectedPulseOut_A	7311466	54	0	0
DisabledIdleSt_A	7311466	4963722	0	0
DisabledNoDetection_A	7311466	4966188	0	0
EnterDebounceSt_A	7311466	133	0	0
EnterDetectSt_A	7311466	71	0	0
EnterStableSt_A	7311466	54	0	0
PulseIsPulse_A	7311466	54	0	0
StayInStableSt	7311466	375026	0	0
gen_high_event_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_sticky_sva.StableStDropOut_A	7311466	172653	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	203	0	0
T7	2218	4	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	2	0	0
T20	0	2	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	2	0	0
T41	817	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	79532	0	0
T7	2218	20	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	186	0	0
T20	0	58	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	14	0	0
T41	817	0	0	0
T43	0	51	0	0
T44	0	28	0	0
T45	0	63	0	0
T59	0	58	0	0
T60	0	57	0	0
T61	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613698	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	17	0	0
T25	23576	0	0	0
T30	709	0	0	0
T45	577	1	0	0
T61	0	2	0	0
T69	0	3	0	0
T72	0	3	0	0
T85	0	1	0	0
T105	0	1	0	0
T110	0	3	0	0
T111	0	3	0	0
T112	402	0	0	0
T113	422	0	0	0
T114	422	0	0	0
T115	4420	0	0	0
T116	423	0	0	0
T117	425	0	0	0
T118	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	375080	0	0
T7	2218	97	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	252	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	38	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	290	0	0
T44	0	85	0	0
T59	0	221	0	0
T60	0	212	0	0
T61	0	18	0	0
T98	0	75	0	0
T99	0	115	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	54	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	4963722	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	4966188	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	133	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	2	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	2	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	71	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	3	0	0
T98	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	54	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	54	0	0
T7	2218	2	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	1	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	375026	0	0
T7	2218	95	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	251	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	37	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	289	0	0
T44	0	84	0	0
T59	0	220	0	0
T60	0	211	0	0
T61	0	17	0	0
T98	0	74	0	0
T99	0	114	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	172653	0	0
T7	2218	1016	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T20	0	48	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	296	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T43	0	536	0	0
T44	0	362	0	0
T59	0	408	0	0
T60	0	142	0	0
T61	0	288	0	0
T98	0	509	0	0
T99	0	84270	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T8,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T3,T8,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T30,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T4,T2
1	1	Covered	T3,T8,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T27
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T27
0	1	Covered	T8,T30,T119
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T30,T27
1	-	Covered	T8,T30,T119

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T30
DetectSt	168	Covered	T8,T30,T27
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T30,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T30,T27
DebounceSt->IdleSt	163	Covered	T3,T39,T120
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T30,T27
IdleSt->DebounceSt	148	Covered	T3,T8,T30
StableSt->IdleSt	206	Covered	T8,T30,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T30
0	1	Covered	T3,T8,T30
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T30,T27
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T30,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T120,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T30,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T30,T119
StableSt	-	-	-	-	-	-	0	Covered	T8,T30,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	77	0	0
CntIncr_A	7311466	27310	0	0
CntNoWrap_A	7311466	6613824	0	0
DetectStDropOut_A	7311466	0	0	0
DetectedOut_A	7311466	2203	0	0
DetectedPulseOut_A	7311466	36	0	0
DisabledIdleSt_A	7311466	6432819	0	0
DisabledNoDetection_A	7311466	6435237	0	0
EnterDebounceSt_A	7311466	42	0	0
EnterDetectSt_A	7311466	36	0	0
EnterStableSt_A	7311466	36	0	0
PulseIsPulse_A	7311466	36	0	0
StayInStableSt	7311466	2144	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	77	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	2	0	0
T30	0	4	0	0
T33	36658	0	0	0
T39	0	1	0	0
T119	0	4	0	0
T122	0	2	0	0
T123	0	2	0	0
T124	0	2	0	0
T125	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	27310	0	0
T3	645	41	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	15	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	83	0	0
T30	0	48	0	0
T33	36658	0	0	0
T39	0	24	0	0
T119	0	104	0	0
T122	0	22	0	0
T123	0	25	0	0
T124	0	39	0	0
T125	0	17154	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613824	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	243	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2203	0	0
T8	17745	10	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	43	0	0
T30	0	118	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T65	0	37	0	0
T119	0	91	0	0
T122	0	38	0	0
T123	0	64	0	0
T124	0	41	0	0
T125	0	49	0	0
T126	0	93	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	36	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T30	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T65	0	1	0	0
T119	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6432819	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	4	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6435237	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	4	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	42	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T30	0	2	0	0
T33	36658	0	0	0
T39	0	1	0	0
T119	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	36	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T30	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T65	0	1	0	0
T119	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	36	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T30	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T65	0	1	0	0
T119	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	36	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T30	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T65	0	1	0	0
T119	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2144	0	0
T8	17745	9	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	41	0	0
T30	0	115	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T65	0	35	0	0
T119	0	88	0	0
T122	0	36	0	0
T123	0	62	0	0
T124	0	40	0	0
T125	0	47	0	0
T126	0	91	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	13	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T30	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T119	0	1	0	0
T124	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T8,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T3,T8,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T8,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T28
1	0	Covered	T1,T13,T14
1	1	Covered	T3,T8,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T28
0	1	Not Covered
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T28
0	1	Covered	T3,T8,T28
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T28
1	-	Covered	T3,T8,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T28
DetectSt	168	Covered	T3,T8,T28
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T8,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T28
DebounceSt->IdleSt	163	Covered	T124,T133,T63
DetectSt->IdleSt	186	Covered	T39,T134
DetectSt->StableSt	191	Covered	T3,T8,T28
IdleSt->DebounceSt	148	Covered	T3,T8,T28
StableSt->IdleSt	206	Covered	T3,T8,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T28
0	1	Covered	T3,T8,T28
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T28
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T124,T133,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T28
DetectSt	-	-	-	-	1	-	-	Covered	T39
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T28
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	127	0	0
CntIncr_A	7311466	20488	0	0
CntNoWrap_A	7311466	6613774	0	0
DetectStDropOut_A	7311466	0	0	0
DetectedOut_A	7311466	42328	0	0
DetectedPulseOut_A	7311466	59	0	0
DisabledIdleSt_A	7311466	6395721	0	0
DisabledNoDetection_A	7311466	6398138	0	0
EnterDebounceSt_A	7311466	68	0	0
EnterDetectSt_A	7311466	60	0	0
EnterStableSt_A	7311466	59	0	0
PulseIsPulse_A	7311466	59	0	0
StayInStableSt	7311466	42244	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7311466	2697	0	0
gen_low_level_sva.LowLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	127	0	0
T3	645	4	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	8	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	6	0	0
T32	0	2	0	0
T33	36658	0	0	0
T39	0	2	0	0
T70	0	4	0	0
T89	0	2	0	0
T122	0	2	0	0
T136	0	2	0	0
T137	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	20488	0	0
T3	645	82	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	114	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	205	0	0
T32	0	57	0	0
T33	36658	0	0	0
T39	0	24	0	0
T70	0	200	0	0
T89	0	15	0	0
T122	0	22	0	0
T136	0	41	0	0
T137	0	196	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613774	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	240	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	42328	0	0
T3	645	140	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	214	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	462	0	0
T32	0	361	0	0
T33	36658	0	0	0
T70	0	53	0	0
T89	0	140	0	0
T122	0	72	0	0
T136	0	239	0	0
T137	0	228	0	0
T138	0	315	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	59	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	4	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T32	0	1	0	0
T33	36658	0	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T136	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6395721	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6398138	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	68	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	4	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T32	0	1	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T136	0	1	0	0
T137	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	60	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	4	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T32	0	1	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T136	0	1	0	0
T137	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	59	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	4	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T32	0	1	0	0
T33	36658	0	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T136	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	59	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	4	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T32	0	1	0	0
T33	36658	0	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T136	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	42244	0	0
T3	645	137	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	208	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	458	0	0
T32	0	359	0	0
T33	36658	0	0	0
T70	0	51	0	0
T89	0	138	0	0
T122	0	71	0	0
T136	0	237	0	0
T137	0	226	0	0
T138	0	314	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2697	0	0
T3	645	2	0	0
T5	6258	17	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	53	0	0
T9	20631	18	0	0
T10	0	77	0	0
T13	1385	10	0	0
T14	2733	20	0	0
T15	402	0	0	0
T21	0	18	0	0
T24	699	0	0	0
T42	0	2	0	0
T95	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	34	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	2	0	0
T33	36658	0	0	0
T70	0	2	0	0
T120	0	1	0	0
T122	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0