Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T8,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T6,T8,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T28,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T4,T2
1	1	Covered	T6,T8,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T28,T31
0	1	Covered	T28,T139
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T28,T31
0	1	Covered	T28,T137,T140
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T28,T31
1	-	Covered	T28,T137,T140

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T28
DetectSt	168	Covered	T6,T28,T39
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T6,T28,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T28,T39
DebounceSt->IdleSt	163	Covered	T8,T120,T63
DetectSt->IdleSt	186	Covered	T28,T39,T139
DetectSt->StableSt	191	Covered	T6,T28,T31
IdleSt->DebounceSt	148	Covered	T6,T8,T28
StableSt->IdleSt	206	Covered	T28,T137,T140

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T28
0	1	Covered	T6,T8,T28
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T28,T39
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T28,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T28
DetectSt	-	-	-	-	1	-	-	Covered	T28,T39,T139
DetectSt	-	-	-	-	0	1	-	Covered	T6,T28,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T137,T140
StableSt	-	-	-	-	-	-	0	Covered	T6,T28,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	69	0	0
CntIncr_A	7311466	1856	0	0
CntNoWrap_A	7311466	6613832	0	0
DetectStDropOut_A	7311466	2	0	0
DetectedOut_A	7311466	2384	0	0
DetectedPulseOut_A	7311466	30	0	0
DisabledIdleSt_A	7311466	6591354	0	0
DisabledNoDetection_A	7311466	6593775	0	0
EnterDebounceSt_A	7311466	36	0	0
EnterDetectSt_A	7311466	33	0	0
EnterStableSt_A	7311466	30	0	0
PulseIsPulse_A	7311466	30	0	0
StayInStableSt	7311466	2333	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	69	0	0
T6	482	2	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	6	0	0
T31	0	2	0	0
T33	36658	0	0	0
T39	0	2	0	0
T119	0	2	0	0
T120	0	1	0	0
T137	0	2	0	0
T140	0	2	0	0
T141	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1856	0	0
T6	482	13	0	0
T7	2218	0	0	0
T8	17745	42	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	173	0	0
T31	0	88	0	0
T33	36658	0	0	0
T39	0	24	0	0
T119	0	52	0	0
T120	0	72	0	0
T137	0	98	0	0
T140	0	89	0	0
T141	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613832	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	79	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2	0	0
T28	17051	1	0	0
T38	9604	0	0	0
T39	6562	0	0	0
T49	494	0	0	0
T139	0	1	0	0
T142	8432	0	0	0
T143	402	0	0	0
T144	536	0	0	0
T145	425	0	0	0
T146	407	0	0	0
T147	669	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2384	0	0
T6	482	45	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	84	0	0
T31	0	137	0	0
T33	36658	0	0	0
T119	0	247	0	0
T126	0	94	0	0
T137	0	219	0	0
T140	0	35	0	0
T141	0	45	0	0
T148	0	40	0	0
T149	0	142	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	30	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	2	0	0
T31	0	1	0	0
T33	36658	0	0	0
T119	0	1	0	0
T126	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6591354	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	4	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6593775	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	4	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	36	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T31	0	1	0	0
T33	36658	0	0	0
T39	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	33	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T31	0	1	0	0
T33	36658	0	0	0
T39	0	1	0	0
T119	0	1	0	0
T126	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T148	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	30	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	2	0	0
T31	0	1	0	0
T33	36658	0	0	0
T119	0	1	0	0
T126	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	30	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	2	0	0
T31	0	1	0	0
T33	36658	0	0	0
T119	0	1	0	0
T126	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2333	0	0
T6	482	43	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	81	0	0
T31	0	135	0	0
T33	36658	0	0	0
T119	0	245	0	0
T126	0	92	0	0
T137	0	218	0	0
T140	0	34	0	0
T141	0	43	0	0
T148	0	38	0	0
T149	0	140	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	9	0	0
T28	17051	1	0	0
T38	9604	0	0	0
T39	6562	0	0	0
T49	494	0	0	0
T130	0	1	0	0
T132	0	1	0	0
T134	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0
T142	8432	0	0	0
T143	402	0	0	0
T144	536	0	0	0
T145	425	0	0	0
T146	407	0	0	0
T147	669	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T8,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T3,T8,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T8,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T29
1	0	Covered	T1,T2,T13
1	1	Covered	T3,T8,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T29
0	1	Covered	T65
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T29
0	1	Covered	T8,T29,T28
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T29
1	-	Covered	T8,T29,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T29
DetectSt	168	Covered	T3,T8,T29
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T8,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T29
DebounceSt->IdleSt	163	Covered	T32,T133,T63
DetectSt->IdleSt	186	Covered	T65
DetectSt->StableSt	191	Covered	T3,T8,T29
IdleSt->DebounceSt	148	Covered	T3,T8,T29
StableSt->IdleSt	206	Covered	T8,T29,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T29
0	1	Covered	T3,T8,T29
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T29
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T29
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T133,T153
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T29
DetectSt	-	-	-	-	1	-	-	Covered	T65
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T29,T28
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	116	0	0
CntIncr_A	7311466	162436	0	0
CntNoWrap_A	7311466	6613785	0	0
DetectStDropOut_A	7311466	1	0	0
DetectedOut_A	7311466	78802	0	0
DetectedPulseOut_A	7311466	54	0	0
DisabledIdleSt_A	7311466	6158116	0	0
DisabledNoDetection_A	7311466	6160530	0	0
EnterDebounceSt_A	7311466	62	0	0
EnterDetectSt_A	7311466	55	0	0
EnterStableSt_A	7311466	54	0	0
PulseIsPulse_A	7311466	54	0	0
StayInStableSt	7311466	78729	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7311466	3209	0	0
gen_low_level_sva.LowLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	116	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	6	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	3	0	0
T33	36658	0	0	0
T39	0	2	0	0
T70	0	4	0	0
T89	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	162436	0	0
T3	645	41	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	99	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	83	0	0
T28	0	79	0	0
T29	0	91	0	0
T31	0	88	0	0
T32	0	114	0	0
T33	36658	0	0	0
T39	0	24	0	0
T70	0	200	0	0
T89	0	15	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613785	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	242	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1	0	0
T65	524	1	0	0
T126	9015	0	0	0
T127	11301	0	0	0
T154	23372	0	0	0
T155	39625	0	0	0
T156	402	0	0	0
T157	1378	0	0	0
T158	504	0	0	0
T159	503	0	0	0
T160	622	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	78802	0	0
T3	645	194	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	144	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	123	0	0
T28	0	319	0	0
T29	0	347	0	0
T31	0	129	0	0
T32	0	102	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	98	0	0
T89	0	69	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	54	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	2	0	0
T89	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6158116	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6160530	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	62	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	2	0	0
T89	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	55	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	2	0	0
T89	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	54	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	2	0	0
T89	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	54	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	2	0	0
T89	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	78729	0	0
T3	645	192	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	139	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	121	0	0
T28	0	318	0	0
T29	0	346	0	0
T31	0	128	0	0
T32	0	101	0	0
T33	36658	0	0	0
T70	0	96	0	0
T89	0	68	0	0
T122	0	70	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	3209	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	12	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	53	0	0
T9	0	27	0	0
T10	0	95	0	0
T12	659	0	0	0
T13	1385	9	0	0
T14	2733	22	0	0
T15	402	0	0	0
T21	0	16	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	34	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T141	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T6,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T3,T6,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T28,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T28
1	0	Covered	T1,T4,T2
1	1	Covered	T3,T6,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T28,T32
0	1	Covered	T141,T80,T161
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T28,T32
0	1	Covered	T32,T89,T122
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T28,T32
1	-	Covered	T32,T89,T122

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T28
DetectSt	168	Covered	T3,T28,T39
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T28,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T28,T39
DebounceSt->IdleSt	163	Covered	T6,T27,T126
DetectSt->IdleSt	186	Covered	T39,T141,T80
DetectSt->StableSt	191	Covered	T3,T28,T32
IdleSt->DebounceSt	148	Covered	T3,T6,T28
StableSt->IdleSt	206	Covered	T28,T32,T70

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T28
0	1	Covered	T3,T6,T28
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T28,T39
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T28,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T27,T126
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T28
DetectSt	-	-	-	-	1	-	-	Covered	T39,T141,T80
DetectSt	-	-	-	-	0	1	-	Covered	T3,T28,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T89,T122
StableSt	-	-	-	-	-	-	0	Covered	T3,T28,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	113	0	0
CntIncr_A	7311466	11088	0	0
CntNoWrap_A	7311466	6613788	0	0
DetectStDropOut_A	7311466	4	0	0
DetectedOut_A	7311466	4457	0	0
DetectedPulseOut_A	7311466	48	0	0
DisabledIdleSt_A	7311466	6504150	0	0
DisabledNoDetection_A	7311466	6506569	0	0
EnterDebounceSt_A	7311466	61	0	0
EnterDetectSt_A	7311466	53	0	0
EnterStableSt_A	7311466	48	0	0
PulseIsPulse_A	7311466	48	0	0
StayInStableSt	7311466	4386	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	113	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T32	0	4	0	0
T33	36658	0	0	0
T39	0	2	0	0
T70	0	4	0	0
T89	0	2	0	0
T122	0	2	0	0
T141	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	11088	0	0
T3	645	41	0	0
T5	6258	0	0	0
T6	482	13	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	49	0	0
T28	0	79	0	0
T32	0	114	0	0
T33	36658	0	0	0
T39	0	24	0	0
T70	0	162	0	0
T89	0	15	0	0
T122	0	22	0	0
T141	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613788	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	242	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	80	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	4	0	0
T68	8322	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T137	1226	0	0	0
T140	910	0	0	0
T141	716	1	0	0
T161	0	1	0	0
T162	522	0	0	0
T163	9566	0	0	0
T164	10459	0	0	0
T165	19253	0	0	0
T166	522	0	0	0
T167	1064	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	4457	0	0
T3	645	194	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	437	0	0
T32	0	245	0	0
T33	36658	0	0	0
T70	0	909	0	0
T89	0	59	0	0
T122	0	3	0	0
T123	0	6	0	0
T138	0	162	0	0
T141	0	46	0	0
T168	0	199	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	48	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T138	0	3	0	0
T141	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6504150	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	4	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6506569	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	4	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	61	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T141	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	53	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T141	0	2	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	48	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T138	0	3	0	0
T141	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	48	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T70	0	2	0	0
T89	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T138	0	3	0	0
T141	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	4386	0	0
T3	645	192	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	435	0	0
T32	0	242	0	0
T33	36658	0	0	0
T70	0	905	0	0
T89	0	58	0	0
T122	0	2	0	0
T123	0	5	0	0
T138	0	158	0	0
T141	0	44	0	0
T168	0	197	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	25	0	0
T32	19707	1	0	0
T60	3148	0	0	0
T67	22120	0	0	0
T70	7130	0	0	0
T74	10796	0	0	0
T89	0	1	0	0
T108	412	0	0	0
T109	11130	0	0	0
T122	0	1	0	0
T123	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T138	0	2	0	0
T148	0	1	0	0
T150	0	2	0	0
T169	0	1	0	0
T170	501	0	0	0
T171	431	0	0	0
T172	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T6,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T6,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T131
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T8,T141,T138
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T10
1	-	Covered	T8,T141,T138

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T10
DetectSt	168	Covered	T6,T8,T10
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T6,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T10
DebounceSt->IdleSt	163	Covered	T63
DetectSt->IdleSt	186	Covered	T39,T131
DetectSt->StableSt	191	Covered	T6,T8,T10
IdleSt->DebounceSt	148	Covered	T6,T8,T10
StableSt->IdleSt	206	Covered	T8,T10,T136

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T10
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T39,T131
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T141,T138
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	75	0	0
CntIncr_A	7311466	18878	0	0
CntNoWrap_A	7311466	6613826	0	0
DetectStDropOut_A	7311466	1	0	0
DetectedOut_A	7311466	39554	0	0
DetectedPulseOut_A	7311466	35	0	0
DisabledIdleSt_A	7311466	6183833	0	0
DisabledNoDetection_A	7311466	6186251	0	0
EnterDebounceSt_A	7311466	38	0	0
EnterDetectSt_A	7311466	37	0	0
EnterStableSt_A	7311466	35	0	0
PulseIsPulse_A	7311466	35	0	0
StayInStableSt	7311466	39500	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7311466	6672	0	0
gen_low_level_sva.LowLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	75	0	0
T6	482	2	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T9	20631	0	0	0
T10	19176	2	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T29	0	2	0	0
T33	36658	0	0	0
T39	0	2	0	0
T119	0	2	0	0
T123	0	2	0	0
T136	0	2	0	0
T138	0	4	0	0
T141	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	18878	0	0
T6	482	13	0	0
T7	2218	0	0	0
T8	17745	15	0	0
T9	20631	0	0	0
T10	19176	33	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T29	0	91	0	0
T33	36658	0	0	0
T39	0	24	0	0
T119	0	52	0	0
T123	0	25	0	0
T136	0	41	0	0
T138	0	92	0	0
T141	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613826	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	79	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1	0	0
T72	104919	0	0	0
T131	821	1	0	0
T173	504	0	0	0
T174	504	0	0	0
T175	17709	0	0	0
T176	778	0	0	0
T177	167928	0	0	0
T178	765	0	0	0
T179	407	0	0	0
T180	15014	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	39554	0	0
T6	482	46	0	0
T7	2218	0	0	0
T8	17745	44	0	0
T9	20631	0	0	0
T10	19176	147	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T29	0	189	0	0
T33	36658	0	0	0
T119	0	44	0	0
T123	0	65	0	0
T125	0	36766	0	0
T136	0	101	0	0
T138	0	52	0	0
T141	0	177	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	35	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	1	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T29	0	1	0	0
T33	36658	0	0	0
T119	0	1	0	0
T123	0	1	0	0
T125	0	1	0	0
T136	0	1	0	0
T138	0	2	0	0
T141	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6183833	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	4	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6186251	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	4	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	38	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	1	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T29	0	1	0	0
T33	36658	0	0	0
T39	0	1	0	0
T119	0	1	0	0
T123	0	1	0	0
T136	0	1	0	0
T138	0	2	0	0
T141	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	37	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	1	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T29	0	1	0	0
T33	36658	0	0	0
T39	0	1	0	0
T119	0	1	0	0
T123	0	1	0	0
T136	0	1	0	0
T138	0	2	0	0
T141	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	35	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	1	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T29	0	1	0	0
T33	36658	0	0	0
T119	0	1	0	0
T123	0	1	0	0
T125	0	1	0	0
T136	0	1	0	0
T138	0	2	0	0
T141	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	35	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	1	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T29	0	1	0	0
T33	36658	0	0	0
T119	0	1	0	0
T123	0	1	0	0
T125	0	1	0	0
T136	0	1	0	0
T138	0	2	0	0
T141	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	39500	0	0
T6	482	44	0	0
T7	2218	0	0	0
T8	17745	43	0	0
T9	20631	0	0	0
T10	19176	145	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T29	0	187	0	0
T33	36658	0	0	0
T119	0	43	0	0
T123	0	63	0	0
T125	0	36764	0	0
T136	0	99	0	0
T138	0	50	0	0
T141	0	176	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6672	0	0
T1	13960	30	0	0
T2	647	1	0	0
T3	645	0	0	0
T4	4567	23	0	0
T5	6258	16	0	0
T6	482	1	0	0
T7	0	14	0	0
T8	0	54	0	0
T9	0	32	0	0
T12	659	0	0	0
T13	1385	7	0	0
T14	2733	17	0	0
T15	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	16	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T119	0	1	0	0
T120	0	1	0	0
T126	0	1	0	0
T128	0	1	0	0
T131	0	1	0	0
T138	0	2	0	0
T141	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T4,T13
1	1	Covered	T2,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T70,T169,T131
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T3,T8,T28
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T8
1	-	Covered	T3,T8,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T8
DetectSt	168	Covered	T2,T3,T8
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T8
DebounceSt->IdleSt	163	Covered	T27,T120,T128
DetectSt->IdleSt	186	Covered	T39,T70,T169
DetectSt->StableSt	191	Covered	T2,T3,T8
IdleSt->DebounceSt	148	Covered	T2,T3,T8
StableSt->IdleSt	206	Covered	T3,T8,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T8
0	1	Covered	T2,T3,T8
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T120,T128
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T39,T70,T169
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T28
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	147	0	0
CntIncr_A	7311466	163116	0	0
CntNoWrap_A	7311466	6613754	0	0
DetectStDropOut_A	7311466	3	0	0
DetectedOut_A	7311466	173727	0	0
DetectedPulseOut_A	7311466	66	0	0
DisabledIdleSt_A	7311466	6157463	0	0
DisabledNoDetection_A	7311466	6159872	0	0
EnterDebounceSt_A	7311466	78	0	0
EnterDetectSt_A	7311466	70	0	0
EnterStableSt_A	7311466	66	0	0
PulseIsPulse_A	7311466	66	0	0
StayInStableSt	7311466	173631	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	147	0	0
T2	647	2	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	4	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	3	0	0
T28	0	6	0	0
T39	0	2	0	0
T70	0	8	0	0
T122	0	2	0	0
T140	0	4	0	0
T141	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	163116	0	0
T2	647	79	0	0
T3	645	41	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	84	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	63	0	0
T28	0	141	0	0
T39	0	24	0	0
T70	0	362	0	0
T122	0	22	0	0
T140	0	178	0	0
T141	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613754	0	0
T1	13960	13553	0	0
T2	647	244	0	0
T3	645	242	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	3	0	0
T64	660	0	0	0
T67	22120	0	0	0
T70	7130	1	0	0
T74	10796	0	0	0
T86	429	0	0	0
T87	507	0	0	0
T88	800	0	0	0
T89	3543	0	0	0
T108	412	0	0	0
T109	11130	0	0	0
T131	0	1	0	0
T169	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	173727	0	0
T2	647	159	0	0
T3	645	115	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	83	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	99	0	0
T28	0	204	0	0
T70	0	174	0	0
T122	0	132	0	0
T123	0	97	0	0
T140	0	69	0	0
T141	0	251	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	66	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T70	0	3	0	0
T122	0	1	0	0
T123	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6157463	0	0
T1	13960	13553	0	0
T2	647	3	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6159872	0	0
T1	13960	13557	0	0
T2	647	3	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	78	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	2	0	0
T28	0	3	0	0
T39	0	1	0	0
T70	0	4	0	0
T122	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	70	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T39	0	1	0	0
T70	0	4	0	0
T122	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	66	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T70	0	3	0	0
T122	0	1	0	0
T123	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	66	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T70	0	3	0	0
T122	0	1	0	0
T123	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	173631	0	0
T2	647	157	0	0
T3	645	114	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	80	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	97	0	0
T28	0	200	0	0
T70	0	171	0	0
T122	0	130	0	0
T123	0	95	0	0
T140	0	66	0	0
T141	0	249	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	36	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T28	0	2	0	0
T33	36658	0	0	0
T70	0	3	0	0
T119	0	2	0	0
T120	0	1	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	2	0	0
T140	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T8,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T3,T8,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T4,T13
1	1	Covered	T3,T8,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T31,T32
0	1	Covered	T149
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T31,T32
0	1	Covered	T31,T32,T70
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T31,T32
1	-	Covered	T31,T32,T70

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T39
DetectSt	168	Covered	T3,T31,T32
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T31,T32
DebounceSt->IdleSt	163	Covered	T8,T39,T119
DetectSt->IdleSt	186	Covered	T149
DetectSt->StableSt	191	Covered	T3,T31,T32
IdleSt->DebounceSt	148	Covered	T3,T8,T39
StableSt->IdleSt	206	Covered	T31,T32,T70

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T39
0	1	Covered	T3,T8,T39
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T31,T32
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T39
DetectSt	-	-	-	-	1	-	-	Covered	T149
DetectSt	-	-	-	-	0	1	-	Covered	T3,T31,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T32,T70
StableSt	-	-	-	-	-	-	0	Covered	T3,T31,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	62	0	0
CntIncr_A	7311466	1883	0	0
CntNoWrap_A	7311466	6613839	0	0
DetectStDropOut_A	7311466	1	0	0
DetectedOut_A	7311466	1445	0	0
DetectedPulseOut_A	7311466	28	0	0
DisabledIdleSt_A	7311466	6470279	0	0
DisabledNoDetection_A	7311466	6472703	0	0
EnterDebounceSt_A	7311466	33	0	0
EnterDetectSt_A	7311466	29	0	0
EnterStableSt_A	7311466	28	0	0
PulseIsPulse_A	7311466	28	0	0
StayInStableSt	7311466	1399	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7311466	6353	0	0
gen_low_level_sva.LowLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	62	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	2	0	0
T31	0	2	0	0
T32	0	4	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	6	0	0
T89	0	2	0	0
T119	0	3	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1883	0	0
T3	645	41	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	42	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	14	0	0
T31	0	88	0	0
T32	0	114	0	0
T33	36658	0	0	0
T39	0	24	0	0
T70	0	300	0	0
T89	0	15	0	0
T119	0	104	0	0
T168	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613839	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	242	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1	0	0
T149	83696	1	0	0
T183	32076	0	0	0
T184	423	0	0	0
T185	19536	0	0	0
T186	32749	0	0	0
T187	426	0	0	0
T188	8401	0	0	0
T189	3725	0	0	0
T190	504	0	0	0
T191	810	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1445	0	0
T3	645	38	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	45	0	0
T31	0	3	0	0
T32	0	144	0	0
T33	36658	0	0	0
T70	0	126	0	0
T89	0	39	0	0
T119	0	143	0	0
T124	0	46	0	0
T126	0	80	0	0
T168	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	28	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T70	0	3	0	0
T89	0	1	0	0
T119	0	1	0	0
T124	0	1	0	0
T126	0	2	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6470279	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6472703	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	33	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T39	0	1	0	0
T70	0	3	0	0
T89	0	1	0	0
T119	0	2	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	29	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T70	0	3	0	0
T89	0	1	0	0
T119	0	1	0	0
T124	0	1	0	0
T126	0	2	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	28	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T70	0	3	0	0
T89	0	1	0	0
T119	0	1	0	0
T124	0	1	0	0
T126	0	2	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	28	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	36658	0	0	0
T70	0	3	0	0
T89	0	1	0	0
T119	0	1	0	0
T124	0	1	0	0
T126	0	2	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1399	0	0
T3	645	36	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T27	0	43	0	0
T31	0	2	0	0
T32	0	141	0	0
T33	36658	0	0	0
T70	0	122	0	0
T89	0	37	0	0
T119	0	141	0	0
T124	0	44	0	0
T126	0	77	0	0
T168	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6353	0	0
T1	13960	26	0	0
T2	647	0	0	0
T3	645	1	0	0
T4	4567	20	0	0
T5	6258	13	0	0
T6	482	0	0	0
T8	0	59	0	0
T9	0	29	0	0
T12	659	0	0	0
T13	1385	5	0	0
T14	2733	20	0	0
T15	402	0	0	0
T21	0	17	0	0
T22	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	10	0	0
T31	853	1	0	0
T32	0	1	0	0
T56	5366	0	0	0
T57	17100	0	0	0
T70	0	2	0	0
T85	0	1	0	0
T93	2242	0	0	0
T126	0	1	0	0
T131	0	1	0	0
T134	0	1	0	0
T136	2713	0	0	0
T148	0	1	0	0
T192	0	1	0	0
T193	1593	0	0	0
T194	406	0	0	0
T195	2235	0	0	0
T196	856	0	0	0
T197	422	0	0	0