Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T4,T13
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T80
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T3,T8,T29
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T6
1	-	Covered	T3,T8,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T6
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T27,T137,T149
DetectSt->IdleSt	186	Covered	T39,T80
DetectSt->StableSt	191	Covered	T2,T3,T6
IdleSt->DebounceSt	148	Covered	T2,T3,T6
StableSt->IdleSt	206	Covered	T3,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T137,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T39,T80
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T29
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	97	0	0
CntIncr_A	7311466	231076	0	0
CntNoWrap_A	7311466	6613804	0	0
DetectStDropOut_A	7311466	1	0	0
DetectedOut_A	7311466	73818	0	0
DetectedPulseOut_A	7311466	44	0	0
DisabledIdleSt_A	7311466	6100032	0	0
DisabledNoDetection_A	7311466	6102461	0	0
EnterDebounceSt_A	7311466	52	0	0
EnterDetectSt_A	7311466	46	0	0
EnterStableSt_A	7311466	44	0	0
PulseIsPulse_A	7311466	44	0	0
StayInStableSt	7311466	73755	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	97	0	0
T2	647	2	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	2	0	0
T7	2218	0	0	0
T8	17745	6	0	0
T10	0	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	3	0	0
T29	0	4	0	0
T39	0	2	0	0
T137	0	5	0	0
T141	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	231076	0	0
T2	647	79	0	0
T3	645	41	0	0
T5	6258	0	0	0
T6	482	13	0	0
T7	2218	0	0	0
T8	17745	99	0	0
T10	0	33	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	132	0	0
T29	0	182	0	0
T39	0	24	0	0
T137	0	294	0	0
T141	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613804	0	0
T1	13960	13553	0	0
T2	647	244	0	0
T3	645	242	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	79	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1	0	0
T73	12054	0	0	0
T80	20169	1	0	0
T150	226541	0	0	0
T198	31141	0	0	0
T199	132388	0	0	0
T200	406	0	0	0
T201	6594	0	0	0
T202	428	0	0	0
T203	22381	0	0	0
T204	8747	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	73818	0	0
T2	647	47	0	0
T3	645	53	0	0
T5	6258	0	0	0
T6	482	59	0	0
T7	2218	0	0	0
T8	17745	231	0	0
T10	0	38	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	99	0	0
T29	0	123	0	0
T137	0	257	0	0
T140	0	198	0	0
T141	0	127	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	44	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T137	0	2	0	0
T140	0	2	0	0
T141	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6100032	0	0
T1	13960	13553	0	0
T2	647	3	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	4	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6102461	0	0
T1	13960	13557	0	0
T2	647	3	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	4	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	52	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	2	0	0
T29	0	2	0	0
T39	0	1	0	0
T137	0	3	0	0
T141	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	46	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T39	0	1	0	0
T137	0	2	0	0
T141	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	44	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T137	0	2	0	0
T140	0	2	0	0
T141	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	44	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T137	0	2	0	0
T140	0	2	0	0
T141	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	73755	0	0
T2	647	45	0	0
T3	645	52	0	0
T5	6258	0	0	0
T6	482	57	0	0
T7	2218	0	0	0
T8	17745	227	0	0
T10	0	36	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	97	0	0
T29	0	121	0	0
T137	0	254	0	0
T140	0	195	0	0
T141	0	123	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	25	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T29	0	2	0	0
T33	36658	0	0	0
T124	0	1	0	0
T125	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T150	0	1	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T30,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T8,T30,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T30,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T30,T28
1	0	Covered	T1,T4,T13
1	1	Covered	T8,T30,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T28
0	1	Not Covered
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T28
0	1	Covered	T8,T30,T28
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T30,T28
1	-	Covered	T8,T30,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T30,T28
DetectSt	168	Covered	T8,T30,T28
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T30,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T30,T28
DebounceSt->IdleSt	163	Covered	T128,T63,T205
DetectSt->IdleSt	186	Covered	T39
DetectSt->StableSt	191	Covered	T8,T30,T28
IdleSt->DebounceSt	148	Covered	T8,T30,T28
StableSt->IdleSt	206	Covered	T8,T30,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T30,T28
0	1	Covered	T8,T30,T28
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T30,T28
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T30,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T30,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T128,T205
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T30,T28
DetectSt	-	-	-	-	1	-	-	Covered	T39
DetectSt	-	-	-	-	0	1	-	Covered	T8,T30,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T30,T28
StableSt	-	-	-	-	-	-	0	Covered	T8,T30,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	89	0	0
CntIncr_A	7311466	89761	0	0
CntNoWrap_A	7311466	6613812	0	0
DetectStDropOut_A	7311466	0	0	0
DetectedOut_A	7311466	2815	0	0
DetectedPulseOut_A	7311466	42	0	0
DisabledIdleSt_A	7311466	6295477	0	0
DisabledNoDetection_A	7311466	6297895	0	0
EnterDebounceSt_A	7311466	46	0	0
EnterDetectSt_A	7311466	43	0	0
EnterStableSt_A	7311466	42	0	0
PulseIsPulse_A	7311466	42	0	0
StayInStableSt	7311466	2751	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7311466	6403	0	0
gen_low_level_sva.LowLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	89	0	0
T8	17745	2	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	6	0	0
T30	0	4	0	0
T32	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	2	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	2	0	0
T89	0	2	0	0
T120	0	4	0	0
T124	0	2	0	0
T137	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	89761	0	0
T8	17745	42	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	173	0	0
T30	0	48	0	0
T32	0	57	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	24	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	100	0	0
T89	0	15	0	0
T120	0	144	0	0
T124	0	61	0	0
T137	0	196	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613812	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2815	0	0
T8	17745	98	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	173	0	0
T30	0	81	0	0
T32	0	262	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	40	0	0
T80	0	41	0	0
T89	0	12	0	0
T120	0	81	0	0
T124	0	60	0	0
T137	0	88	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	42	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T30	0	2	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T80	0	1	0	0
T89	0	1	0	0
T120	0	2	0	0
T124	0	1	0	0
T137	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6295477	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6297895	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	46	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T30	0	2	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	1	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T89	0	1	0	0
T120	0	2	0	0
T124	0	1	0	0
T137	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	43	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T30	0	2	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	1	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T89	0	1	0	0
T120	0	2	0	0
T124	0	1	0	0
T137	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	42	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T30	0	2	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T80	0	1	0	0
T89	0	1	0	0
T120	0	2	0	0
T124	0	1	0	0
T137	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	42	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T30	0	2	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T80	0	1	0	0
T89	0	1	0	0
T120	0	2	0	0
T124	0	1	0	0
T137	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2751	0	0
T8	17745	97	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	169	0	0
T30	0	78	0	0
T32	0	261	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	38	0	0
T80	0	39	0	0
T89	0	11	0	0
T120	0	79	0	0
T124	0	59	0	0
T137	0	86	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6403	0	0
T1	13960	28	0	0
T2	647	0	0	0
T3	645	1	0	0
T4	4567	26	0	0
T5	6258	16	0	0
T6	482	0	0	0
T8	0	59	0	0
T9	0	27	0	0
T12	659	0	0	0
T13	1385	7	0	0
T14	2733	18	0	0
T15	402	0	0	0
T21	0	19	0	0
T22	0	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	20	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T73	0	1	0	0
T89	0	1	0	0
T120	0	2	0	0
T121	0	1	0	0
T124	0	1	0	0
T137	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T10,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T4,T13
1	1	Covered	T2,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T30
0	1	Covered	T121
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T30
0	1	Covered	T2,T10,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T10,T30
1	-	Covered	T2,T10,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T10
DetectSt	168	Covered	T2,T10,T30
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T10,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T30
DebounceSt->IdleSt	163	Covered	T8,T31,T63
DetectSt->IdleSt	186	Covered	T39,T121
DetectSt->StableSt	191	Covered	T2,T10,T30
IdleSt->DebounceSt	148	Covered	T2,T8,T10
StableSt->IdleSt	206	Covered	T2,T10,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T10
0	1	Covered	T2,T8,T10
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T30
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T31,T206
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T39,T121
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T30
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	148	0	0
CntIncr_A	7311466	91234	0	0
CntNoWrap_A	7311466	6613753	0	0
DetectStDropOut_A	7311466	1	0	0
DetectedOut_A	7311466	109596	0	0
DetectedPulseOut_A	7311466	70	0	0
DisabledIdleSt_A	7311466	6293948	0	0
DisabledNoDetection_A	7311466	6296361	0	0
EnterDebounceSt_A	7311466	76	0	0
EnterDetectSt_A	7311466	72	0	0
EnterStableSt_A	7311466	70	0	0
PulseIsPulse_A	7311466	70	0	0
StayInStableSt	7311466	109494	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	148	0	0
T2	647	2	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T10	0	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	2	0	0
T28	0	6	0	0
T30	0	4	0	0
T31	0	3	0	0
T39	0	2	0	0
T70	0	6	0	0
T89	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	91234	0	0
T2	647	79	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	42	0	0
T10	0	33	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	14	0	0
T28	0	205	0	0
T30	0	48	0	0
T31	0	176	0	0
T39	0	24	0	0
T70	0	262	0	0
T89	0	15	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613753	0	0
T1	13960	13553	0	0
T2	647	244	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1	0	0
T121	811	1	0	0
T207	505	0	0	0
T208	410	0	0	0
T209	522	0	0	0
T210	1487	0	0	0
T211	13667	0	0	0
T212	25081	0	0	0
T213	742	0	0	0
T214	680	0	0	0
T215	496	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	109596	0	0
T2	647	32	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T10	0	74	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	45	0	0
T28	0	417	0	0
T30	0	187	0	0
T31	0	138	0	0
T70	0	320	0	0
T89	0	39	0	0
T122	0	39	0	0
T141	0	86	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	70	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T30	0	2	0	0
T31	0	1	0	0
T70	0	3	0	0
T89	0	1	0	0
T122	0	1	0	0
T141	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6293948	0	0
T1	13960	13553	0	0
T2	647	3	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6296361	0	0
T1	13960	13557	0	0
T2	647	3	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	76	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T30	0	2	0	0
T31	0	2	0	0
T39	0	1	0	0
T70	0	3	0	0
T89	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	72	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T30	0	2	0	0
T31	0	1	0	0
T39	0	1	0	0
T70	0	3	0	0
T89	0	1	0	0
T122	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	70	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T30	0	2	0	0
T31	0	1	0	0
T70	0	3	0	0
T89	0	1	0	0
T122	0	1	0	0
T141	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	70	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T30	0	2	0	0
T31	0	1	0	0
T70	0	3	0	0
T89	0	1	0	0
T122	0	1	0	0
T141	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	109494	0	0
T2	647	31	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T10	0	73	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T27	0	43	0	0
T28	0	413	0	0
T30	0	184	0	0
T31	0	136	0	0
T70	0	315	0	0
T89	0	37	0	0
T122	0	38	0	0
T141	0	82	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	38	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T28	0	2	0	0
T30	0	1	0	0
T70	0	1	0	0
T122	0	1	0	0
T126	0	3	0	0
T137	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T4,T13
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T3,T30,T137
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T6
1	-	Covered	T3,T30,T137

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T6
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T63,T69
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T3,T6
IdleSt->DebounceSt	148	Covered	T2,T3,T6
StableSt->IdleSt	206	Covered	T3,T8,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T30,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	63	0	0
CntIncr_A	7311466	9899	0	0
CntNoWrap_A	7311466	6613838	0	0
DetectStDropOut_A	7311466	0	0	0
DetectedOut_A	7311466	2182	0	0
DetectedPulseOut_A	7311466	31	0	0
DisabledIdleSt_A	7311466	6504141	0	0
DisabledNoDetection_A	7311466	6506563	0	0
EnterDebounceSt_A	7311466	33	0	0
EnterDetectSt_A	7311466	31	0	0
EnterStableSt_A	7311466	31	0	0
PulseIsPulse_A	7311466	31	0	0
StayInStableSt	7311466	2137	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7311466	6368	0	0
gen_low_level_sva.LowLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	63	0	0
T2	647	2	0	0
T3	645	2	0	0
T5	6258	0	0	0
T6	482	2	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T30	0	2	0	0
T39	0	2	0	0
T122	0	2	0	0
T123	0	2	0	0
T137	0	2	0	0
T140	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	9899	0	0
T2	647	79	0	0
T3	645	41	0	0
T5	6258	0	0	0
T6	482	13	0	0
T7	2218	0	0	0
T8	17745	42	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T30	0	24	0	0
T39	0	24	0	0
T122	0	22	0	0
T123	0	25	0	0
T137	0	98	0	0
T140	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613838	0	0
T1	13960	13553	0	0
T2	647	244	0	0
T3	645	242	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	79	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2182	0	0
T2	647	47	0	0
T3	645	41	0	0
T5	6258	0	0	0
T6	482	46	0	0
T7	2218	0	0	0
T8	17745	40	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T30	0	39	0	0
T39	0	1	0	0
T122	0	70	0	0
T123	0	64	0	0
T137	0	184	0	0
T140	0	164	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	31	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T30	0	1	0	0
T39	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6504141	0	0
T1	13960	13553	0	0
T2	647	3	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	4	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6506563	0	0
T1	13960	13557	0	0
T2	647	3	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	4	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	33	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T30	0	1	0	0
T39	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	31	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T30	0	1	0	0
T39	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	31	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T30	0	1	0	0
T39	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	31	0	0
T2	647	1	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	1	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T30	0	1	0	0
T39	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2137	0	0
T2	647	45	0	0
T3	645	40	0	0
T5	6258	0	0	0
T6	482	44	0	0
T7	2218	0	0	0
T8	17745	38	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T30	0	38	0	0
T122	0	68	0	0
T123	0	62	0	0
T126	0	193	0	0
T137	0	183	0	0
T140	0	162	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6368	0	0
T1	13960	28	0	0
T2	647	1	0	0
T3	645	1	0	0
T4	4567	17	0	0
T5	6258	15	0	0
T6	482	1	0	0
T8	0	55	0	0
T9	0	32	0	0
T12	659	0	0	0
T13	1385	8	0	0
T14	2733	19	0	0
T15	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	16	0	0
T3	645	1	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	0	0	0
T15	402	0	0	0
T21	4200	0	0	0
T24	699	0	0	0
T30	0	1	0	0
T33	36658	0	0	0
T126	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T169	0	1	0	0
T216	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T4,T12
1	1	Covered	T2,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T10
0	1	Covered	T32,T217
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T10
0	1	Covered	T2,T8,T29
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T10
1	-	Covered	T2,T8,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T10
DetectSt	168	Covered	T2,T8,T10
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T10
DebounceSt->IdleSt	163	Covered	T8,T27,T218
DetectSt->IdleSt	186	Covered	T39,T32,T217
DetectSt->StableSt	191	Covered	T2,T8,T10
IdleSt->DebounceSt	148	Covered	T2,T8,T10
StableSt->IdleSt	206	Covered	T2,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T10
0	1	Covered	T2,T8,T10
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T10
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T27,T218
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T39,T32,T217
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T29
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	116	0	0
CntIncr_A	7311466	121754	0	0
CntNoWrap_A	7311466	6613785	0	0
DetectStDropOut_A	7311466	2	0	0
DetectedOut_A	7311466	101766	0	0
DetectedPulseOut_A	7311466	52	0	0
DisabledIdleSt_A	7311466	6314070	0	0
DisabledNoDetection_A	7311466	6316487	0	0
EnterDebounceSt_A	7311466	61	0	0
EnterDetectSt_A	7311466	55	0	0
EnterStableSt_A	7311466	52	0	0
PulseIsPulse_A	7311466	52	0	0
StayInStableSt	7311466	101693	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	116	0	0
T2	647	2	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	3	0	0
T10	0	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T29	0	4	0	0
T30	0	6	0	0
T31	0	2	0	0
T32	0	4	0	0
T39	0	2	0	0
T89	0	2	0	0
T136	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	121754	0	0
T2	647	79	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	84	0	0
T10	0	33	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T29	0	182	0	0
T30	0	72	0	0
T31	0	88	0	0
T32	0	114	0	0
T39	0	24	0	0
T89	0	15	0	0
T136	0	41	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613785	0	0
T1	13960	13553	0	0
T2	647	244	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2	0	0
T32	19707	1	0	0
T60	3148	0	0	0
T67	22120	0	0	0
T70	7130	0	0	0
T74	10796	0	0	0
T108	412	0	0	0
T109	11130	0	0	0
T170	501	0	0	0
T171	431	0	0	0
T172	407	0	0	0
T217	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	101766	0	0
T2	647	32	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	40	0	0
T10	0	73	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T29	0	236	0	0
T30	0	27	0	0
T31	0	267	0	0
T32	0	42	0	0
T89	0	59	0	0
T136	0	100	0	0
T140	0	293	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	52	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T29	0	2	0	0
T30	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T89	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6314070	0	0
T1	13960	13553	0	0
T2	647	3	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6316487	0	0
T1	13960	13557	0	0
T2	647	3	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	61	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	2	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T29	0	2	0	0
T30	0	3	0	0
T31	0	1	0	0
T32	0	2	0	0
T39	0	1	0	0
T89	0	1	0	0
T136	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	55	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T29	0	2	0	0
T30	0	3	0	0
T31	0	1	0	0
T32	0	2	0	0
T39	0	1	0	0
T89	0	1	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	52	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T29	0	2	0	0
T30	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T89	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	52	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T10	0	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T29	0	2	0	0
T30	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T89	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	101693	0	0
T2	647	31	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	39	0	0
T10	0	71	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T29	0	233	0	0
T30	0	24	0	0
T31	0	265	0	0
T32	0	40	0	0
T89	0	58	0	0
T136	0	99	0	0
T140	0	291	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	31	0	0
T2	647	1	0	0
T3	645	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	1	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T29	0	1	0	0
T30	0	3	0	0
T89	0	1	0	0
T120	0	1	0	0
T124	0	1	0	0
T126	0	2	0	0
T136	0	1	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T29,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T8,T29,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T29,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T8,T29,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T30
0	1	Covered	T8,T29,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T29,T30
1	-	Covered	T8,T29,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T29,T30
DetectSt	168	Covered	T8,T29,T30
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T29,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T29,T30
DebounceSt->IdleSt	163	Covered	T39,T63
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T29,T30
IdleSt->DebounceSt	148	Covered	T8,T29,T30
StableSt->IdleSt	206	Covered	T8,T29,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T29,T30
0	1	Covered	T8,T29,T30
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T29,T30
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T29,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T29,T30
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T29,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T29,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T29,T30
StableSt	-	-	-	-	-	-	0	Covered	T8,T29,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	76	0	0
CntIncr_A	7311466	52701	0	0
CntNoWrap_A	7311466	6613825	0	0
DetectStDropOut_A	7311466	0	0	0
DetectedOut_A	7311466	2275	0	0
DetectedPulseOut_A	7311466	37	0	0
DisabledIdleSt_A	7311466	6088464	0	0
DisabledNoDetection_A	7311466	6090883	0	0
EnterDebounceSt_A	7311466	39	0	0
EnterDetectSt_A	7311466	37	0	0
EnterStableSt_A	7311466	37	0	0
PulseIsPulse_A	7311466	37	0	0
StayInStableSt	7311466	2220	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7311466	7039	0	0
gen_low_level_sva.LowLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	76	0	0
T8	17745	2	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	2	0	0
T28	0	8	0	0
T29	0	2	0	0
T30	0	6	0	0
T32	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	1	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	2	0	0
T123	0	2	0	0
T141	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	52701	0	0
T8	17745	15	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	14	0	0
T28	0	252	0	0
T29	0	91	0	0
T30	0	72	0	0
T32	0	57	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	24	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	100	0	0
T123	0	25	0	0
T141	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613825	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2275	0	0
T8	17745	44	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	45	0	0
T28	0	163	0	0
T29	0	58	0	0
T30	0	123	0	0
T32	0	102	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	340	0	0
T123	0	64	0	0
T124	0	39	0	0
T141	0	117	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	37	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	4	0	0
T29	0	1	0	0
T30	0	3	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T141	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6088464	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	4	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6090883	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	4	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	39	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	4	0	0
T29	0	1	0	0
T30	0	3	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	1	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T123	0	1	0	0
T141	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	37	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	4	0	0
T29	0	1	0	0
T30	0	3	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T141	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	37	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	4	0	0
T29	0	1	0	0
T30	0	3	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T141	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	37	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	1	0	0
T28	0	4	0	0
T29	0	1	0	0
T30	0	3	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T141	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2220	0	0
T8	17745	43	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T27	0	43	0	0
T28	0	158	0	0
T29	0	57	0	0
T30	0	119	0	0
T32	0	101	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	339	0	0
T123	0	62	0	0
T124	0	37	0	0
T141	0	114	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	7039	0	0
T1	13960	24	0	0
T2	647	1	0	0
T3	645	0	0	0
T4	4567	22	0	0
T5	6258	17	0	0
T6	482	1	0	0
T7	0	14	0	0
T8	0	50	0	0
T12	659	3	0	0
T13	1385	8	0	0
T14	2733	22	0	0
T15	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	19	0	0
T8	17745	1	0	0
T9	20631	0	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T28	0	3	0	0
T29	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T70	0	1	0	0
T120	0	1	0	0
T128	0	1	0	0
T141	0	1	0	0
T182	0	1	0	0