Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T22
1	0	Covered	T1,T22,T25
1	1	Covered	T1,T4,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T22
0	1	Covered	T4,T39,T56
1	0	Covered	T39,T57,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T25
0	1	Covered	T1,T22,T25
1	0	Covered	T68,T175

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T22,T25
1	-	Covered	T1,T22,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T22
DetectSt	168	Covered	T1,T4,T22
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T22,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T22
DebounceSt->IdleSt	163	Covered	T39,T163,T77
DetectSt->IdleSt	186	Covered	T4,T39,T56
DetectSt->StableSt	191	Covered	T1,T22,T25
IdleSt->DebounceSt	148	Covered	T1,T4,T22
StableSt->IdleSt	206	Covered	T1,T22,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T22
0	1	Covered	T1,T4,T22
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T22
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T163,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T22
DetectSt	-	-	-	-	1	-	-	Covered	T4,T39,T56
DetectSt	-	-	-	-	0	1	-	Covered	T1,T22,T25
DetectSt	-	-	-	-	0	0	-	Covered	T1,T4,T22
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T25
StableSt	-	-	-	-	-	-	0	Covered	T1,T22,T25
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	2917	0	0
CntIncr_A	7311466	96250	0	0
CntNoWrap_A	7311466	6610984	0	0
DetectStDropOut_A	7311466	512	0	0
DetectedOut_A	7311466	58971	0	0
DetectedPulseOut_A	7311466	732	0	0
DisabledIdleSt_A	7311466	6190256	0	0
DisabledNoDetection_A	7311466	6192540	0	0
EnterDebounceSt_A	7311466	1479	0	0
EnterDetectSt_A	7311466	1439	0	0
EnterStableSt_A	7311466	732	0	0
PulseIsPulse_A	7311466	732	0	0
StayInStableSt	7311466	58146	0	0
gen_high_event_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	634	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	2917	0	0
T1	13960	16	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	22	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	44	0	0
T25	0	38	0	0
T26	0	50	0	0
T38	0	36	0	0
T39	0	16	0	0
T40	0	2	0	0
T56	0	10	0	0
T57	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	96250	0	0
T1	13960	336	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	425	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	1144	0	0
T25	0	988	0	0
T26	0	1275	0	0
T38	0	450	0	0
T39	0	440	0	0
T40	0	21	0	0
T56	0	271	0	0
T57	0	1409	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6610984	0	0
T1	13960	13537	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4144	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	512	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	11	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T39	0	1	0	0
T56	0	5	0	0
T57	0	20	0	0
T74	0	16	0	0
T75	0	20	0	0
T77	0	19	0	0
T78	0	10	0	0
T201	0	6	0	0
T219	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	58971	0	0
T1	13960	276	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	713	0	0
T25	0	1431	0	0
T26	0	879	0	0
T38	0	1410	0	0
T39	0	402	0	0
T40	0	35	0	0
T58	0	144	0	0
T67	0	1602	0	0
T96	0	626	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	732	0	0
T1	13960	8	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	22	0	0
T25	0	19	0	0
T26	0	25	0	0
T38	0	18	0	0
T39	0	5	0	0
T40	0	1	0	0
T58	0	5	0	0
T67	0	31	0	0
T96	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6190256	0	0
T1	13960	9604	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	2015	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6192540	0	0
T1	13960	9607	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	2015	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1479	0	0
T1	13960	8	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	11	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	22	0	0
T25	0	19	0	0
T26	0	25	0	0
T38	0	18	0	0
T39	0	9	0	0
T40	0	1	0	0
T56	0	5	0	0
T57	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1439	0	0
T1	13960	8	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	11	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	22	0	0
T25	0	19	0	0
T26	0	25	0	0
T38	0	18	0	0
T39	0	7	0	0
T40	0	1	0	0
T56	0	5	0	0
T57	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	732	0	0
T1	13960	8	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	22	0	0
T25	0	19	0	0
T26	0	25	0	0
T38	0	18	0	0
T39	0	5	0	0
T40	0	1	0	0
T58	0	5	0	0
T67	0	31	0	0
T96	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	732	0	0
T1	13960	8	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	22	0	0
T25	0	19	0	0
T26	0	25	0	0
T38	0	18	0	0
T39	0	5	0	0
T40	0	1	0	0
T58	0	5	0	0
T67	0	31	0	0
T96	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	58146	0	0
T1	13960	268	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	691	0	0
T25	0	1408	0	0
T26	0	854	0	0
T38	0	1390	0	0
T39	0	397	0	0
T40	0	33	0	0
T58	0	139	0	0
T67	0	1565	0	0
T96	0	603	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	634	0	0
T1	13960	8	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	22	0	0
T25	0	15	0	0
T26	0	25	0	0
T38	0	16	0	0
T39	0	5	0	0
T58	0	5	0	0
T67	0	25	0	0
T96	0	21	0	0
T163	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T5,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T4,T13
1	1	Covered	T5,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T11
0	1	Covered	T9,T61,T76
1	0	Covered	T39,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T11
0	1	Covered	T5,T9,T11
1	0	Covered	T39,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T9,T11
1	-	Covered	T5,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T9,T10
DetectSt	168	Covered	T5,T9,T11
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T9,T11
DebounceSt->IdleSt	163	Covered	T10,T25,T28
DetectSt->IdleSt	186	Covered	T9,T39,T61
DetectSt->StableSt	191	Covered	T5,T9,T11
IdleSt->DebounceSt	148	Covered	T5,T9,T10
StableSt->IdleSt	206	Covered	T5,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T9,T10
0	1	Covered	T5,T9,T10
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T11
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T25,T28
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T9,T39,T61
DetectSt	-	-	-	-	0	1	-	Covered	T5,T9,T11
DetectSt	-	-	-	-	0	0	-	Covered	T5,T9,T11
StableSt	-	-	-	-	-	-	1	Covered	T5,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T5,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	876	0	0
CntIncr_A	7311466	44366	0	0
CntNoWrap_A	7311466	6613025	0	0
DetectStDropOut_A	7311466	33	0	0
DetectedOut_A	7311466	14132	0	0
DetectedPulseOut_A	7311466	367	0	0
DisabledIdleSt_A	7311466	6236674	0	0
DisabledNoDetection_A	7311466	6238433	0	0
EnterDebounceSt_A	7311466	474	0	0
EnterDetectSt_A	7311466	404	0	0
EnterStableSt_A	7311466	367	0	0
PulseIsPulse_A	7311466	367	0	0
StayInStableSt	7311466	13744	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	344	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	876	0	0
T5	6258	2	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	6	0	0
T10	0	1	0	0
T11	0	10	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	9	0	0
T28	0	1	0	0
T33	36658	0	0	0
T38	0	4	0	0
T39	0	8	0	0
T50	0	1	0	0
T62	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	44366	0	0
T5	6258	25	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	517	0	0
T10	0	20	0	0
T11	0	490	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	258	0	0
T28	0	20	0	0
T33	36658	0	0	0
T38	0	92	0	0
T39	0	238	0	0
T50	0	20	0	0
T62	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613025	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3372	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	33	0	0
T9	20631	1	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T46	555	0	0	0
T61	0	2	0	0
T69	0	4	0	0
T76	0	1	0	0
T79	0	7	0	0
T81	0	3	0	0
T82	0	5	0	0
T83	0	4	0	0
T84	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	14132	0	0
T5	6258	3	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	35	0	0
T11	0	69	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	205	0	0
T33	36658	0	0	0
T38	0	104	0	0
T39	0	95	0	0
T62	0	54	0	0
T67	0	485	0	0
T90	0	3	0	0
T93	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	367	0	0
T5	6258	1	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	2	0	0
T11	0	5	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	4	0	0
T33	36658	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T62	0	1	0	0
T67	0	6	0	0
T90	0	1	0	0
T93	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6236674	0	0
T1	13960	13277	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3290	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6238433	0	0
T1	13960	13281	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3298	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	474	0	0
T5	6258	1	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	3	0	0
T10	0	1	0	0
T11	0	5	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	5	0	0
T28	0	1	0	0
T33	36658	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T50	0	1	0	0
T62	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	404	0	0
T5	6258	1	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	3	0	0
T11	0	5	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	4	0	0
T33	36658	0	0	0
T38	0	2	0	0
T39	0	3	0	0
T61	0	2	0	0
T62	0	1	0	0
T67	0	6	0	0
T93	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	367	0	0
T5	6258	1	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	2	0	0
T11	0	5	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	4	0	0
T33	36658	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T62	0	1	0	0
T67	0	6	0	0
T90	0	1	0	0
T93	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	367	0	0
T5	6258	1	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	2	0	0
T11	0	5	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	4	0	0
T33	36658	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T62	0	1	0	0
T67	0	6	0	0
T90	0	1	0	0
T93	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	13744	0	0
T5	6258	2	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	33	0	0
T11	0	64	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	199	0	0
T33	36658	0	0	0
T38	0	100	0	0
T39	0	94	0	0
T62	0	53	0	0
T67	0	479	0	0
T90	0	2	0	0
T93	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	344	0	0
T5	6258	1	0	0
T6	482	0	0	0
T7	2218	0	0	0
T8	17745	0	0	0
T9	20631	2	0	0
T11	0	5	0	0
T15	402	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	2	0	0
T27	0	4	0	0
T33	36658	0	0	0
T62	0	1	0	0
T67	0	6	0	0
T90	0	1	0	0
T93	0	1	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T22
1	0	Covered	T1,T22,T25
1	1	Covered	T1,T4,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T22
0	1	Covered	T4,T38,T39
1	0	Covered	T38,T39,T165

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T25
0	1	Covered	T1,T22,T25
1	0	Covered	T220

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T22,T25
1	-	Covered	T1,T22,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T22
DetectSt	168	Covered	T1,T4,T22
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T22,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T22
DebounceSt->IdleSt	163	Covered	T39,T163,T77
DetectSt->IdleSt	186	Covered	T4,T38,T39
DetectSt->StableSt	191	Covered	T1,T22,T25
IdleSt->DebounceSt	148	Covered	T1,T4,T22
StableSt->IdleSt	206	Covered	T1,T22,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T22
0	1	Covered	T1,T4,T22
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T22
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T163,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T22
DetectSt	-	-	-	-	1	-	-	Covered	T4,T38,T39
DetectSt	-	-	-	-	0	1	-	Covered	T1,T22,T25
DetectSt	-	-	-	-	0	0	-	Covered	T1,T4,T22
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T25
StableSt	-	-	-	-	-	-	0	Covered	T1,T22,T25
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	3092	0	0
CntIncr_A	7311466	104750	0	0
CntNoWrap_A	7311466	6610809	0	0
DetectStDropOut_A	7311466	527	0	0
DetectedOut_A	7311466	75963	0	0
DetectedPulseOut_A	7311466	803	0	0
DisabledIdleSt_A	7311466	6178342	0	0
DisabledNoDetection_A	7311466	6180604	0	0
EnterDebounceSt_A	7311466	1565	0	0
EnterDetectSt_A	7311466	1528	0	0
EnterStableSt_A	7311466	803	0	0
PulseIsPulse_A	7311466	803	0	0
StayInStableSt	7311466	75044	0	0
gen_high_event_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	681	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	3092	0	0
T1	13960	6	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	44	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	42	0	0
T25	0	28	0	0
T26	0	18	0	0
T38	0	52	0	0
T39	0	16	0	0
T56	0	14	0	0
T57	0	22	0	0
T58	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	104750	0	0
T1	13960	180	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	857	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	1512	0	0
T25	0	630	0	0
T26	0	369	0	0
T38	0	880	0	0
T39	0	384	0	0
T56	0	379	0	0
T57	0	352	0	0
T58	0	1352	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6610809	0	0
T1	13960	13547	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4122	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	527	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	22	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T38	0	8	0	0
T39	0	1	0	0
T56	0	7	0	0
T75	0	20	0	0
T77	0	8	0	0
T78	0	30	0	0
T221	0	6	0	0
T222	0	14	0	0
T223	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	75963	0	0
T1	13960	275	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	1673	0	0
T25	0	1203	0	0
T26	0	235	0	0
T39	0	342	0	0
T57	0	1843	0	0
T58	0	1851	0	0
T67	0	2515	0	0
T74	0	1908	0	0
T109	0	1623	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	803	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	21	0	0
T25	0	14	0	0
T26	0	9	0	0
T39	0	5	0	0
T57	0	11	0	0
T58	0	26	0	0
T67	0	33	0	0
T74	0	24	0	0
T109	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6178342	0	0
T1	13960	9395	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	2015	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6180604	0	0
T1	13960	9398	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	2015	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1565	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	22	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	21	0	0
T25	0	14	0	0
T26	0	9	0	0
T38	0	26	0	0
T39	0	9	0	0
T56	0	7	0	0
T57	0	11	0	0
T58	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1528	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	22	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	21	0	0
T25	0	14	0	0
T26	0	9	0	0
T38	0	26	0	0
T39	0	7	0	0
T56	0	7	0	0
T57	0	11	0	0
T58	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	803	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	21	0	0
T25	0	14	0	0
T26	0	9	0	0
T39	0	5	0	0
T57	0	11	0	0
T58	0	26	0	0
T67	0	33	0	0
T74	0	24	0	0
T109	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	803	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	21	0	0
T25	0	14	0	0
T26	0	9	0	0
T39	0	5	0	0
T57	0	11	0	0
T58	0	26	0	0
T67	0	33	0	0
T74	0	24	0	0
T109	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	75044	0	0
T1	13960	272	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	1651	0	0
T25	0	1183	0	0
T26	0	226	0	0
T39	0	337	0	0
T57	0	1827	0	0
T58	0	1817	0	0
T67	0	2478	0	0
T74	0	1882	0	0
T109	0	1601	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	681	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	20	0	0
T25	0	8	0	0
T26	0	9	0	0
T39	0	5	0	0
T57	0	6	0	0
T58	0	18	0	0
T67	0	29	0	0
T74	0	22	0	0
T109	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T11,T61,T224
1	0	Covered	T39,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T9
1	-	Covered	T1,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T9
DetectSt	168	Covered	T1,T8,T9
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T9
DebounceSt->IdleSt	163	Covered	T39,T74,T68
DetectSt->IdleSt	186	Covered	T11,T28,T39
DetectSt->StableSt	191	Covered	T1,T8,T9
IdleSt->DebounceSt	148	Covered	T1,T8,T9
StableSt->IdleSt	206	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T74,T68,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T11,T39,T61
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	819	0	0
CntIncr_A	7311466	43359	0	0
CntNoWrap_A	7311466	6613082	0	0
DetectStDropOut_A	7311466	31	0	0
DetectedOut_A	7311466	15473	0	0
DetectedPulseOut_A	7311466	354	0	0
DisabledIdleSt_A	7311466	6224901	0	0
DisabledNoDetection_A	7311466	6226709	0	0
EnterDebounceSt_A	7311466	432	0	0
EnterDetectSt_A	7311466	390	0	0
EnterStableSt_A	7311466	354	0	0
PulseIsPulse_A	7311466	354	0	0
StayInStableSt	7311466	15084	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	317	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	819	0	0
T1	13960	2	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	4	0	0
T9	0	10	0	0
T11	0	4	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	2	0	0
T25	0	10	0	0
T26	0	2	0	0
T28	0	3	0	0
T39	0	8	0	0
T57	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	43359	0	0
T1	13960	63	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	260	0	0
T9	0	604	0	0
T11	0	222	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	64	0	0
T25	0	280	0	0
T26	0	27	0	0
T28	0	215	0	0
T39	0	178	0	0
T57	0	290	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613082	0	0
T1	13960	13551	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	31	0	0
T11	15749	2	0	0
T29	978	0	0	0
T53	506	0	0	0
T54	502	0	0	0
T55	531	0	0	0
T61	0	2	0	0
T63	0	1	0	0
T69	0	1	0	0
T103	866	0	0	0
T104	403	0	0	0
T149	0	2	0	0
T192	0	9	0	0
T224	0	5	0	0
T225	0	3	0	0
T226	0	1	0	0
T227	0	1	0	0
T228	422	0	0	0
T229	422	0	0	0
T230	418	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	15473	0	0
T1	13960	47	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	172	0	0
T9	0	335	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	73	0	0
T25	0	264	0	0
T26	0	49	0	0
T28	0	56	0	0
T39	0	95	0	0
T57	0	201	0	0
T58	0	335	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	354	0	0
T1	13960	1	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	5	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	1	0	0
T25	0	5	0	0
T26	0	1	0	0
T28	0	1	0	0
T39	0	1	0	0
T57	0	5	0	0
T58	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6224901	0	0
T1	13960	13278	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6226709	0	0
T1	13960	13282	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	432	0	0
T1	13960	1	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	5	0	0
T11	0	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	1	0	0
T25	0	5	0	0
T26	0	1	0	0
T28	0	2	0	0
T39	0	5	0	0
T57	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	390	0	0
T1	13960	1	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	5	0	0
T11	0	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	1	0	0
T25	0	5	0	0
T26	0	1	0	0
T28	0	2	0	0
T39	0	3	0	0
T57	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	354	0	0
T1	13960	1	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	5	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	1	0	0
T25	0	5	0	0
T26	0	1	0	0
T28	0	1	0	0
T39	0	1	0	0
T57	0	5	0	0
T58	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	354	0	0
T1	13960	1	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	5	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	1	0	0
T25	0	5	0	0
T26	0	1	0	0
T28	0	1	0	0
T39	0	1	0	0
T57	0	5	0	0
T58	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	15084	0	0
T1	13960	46	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	170	0	0
T9	0	330	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	71	0	0
T25	0	259	0	0
T26	0	48	0	0
T28	0	55	0	0
T39	0	94	0	0
T57	0	196	0	0
T58	0	329	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	317	0	0
T1	13960	1	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	5	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	5	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T57	0	5	0	0
T58	0	6	0	0
T67	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T22
1	0	Covered	T1,T22,T25
1	1	Covered	T1,T4,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T22
0	1	Covered	T4,T38,T39
1	0	Covered	T38,T39,T26

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T25
0	1	Covered	T1,T22,T25
1	0	Covered	T39,T231,T220

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T22,T25
1	-	Covered	T1,T22,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T22
DetectSt	168	Covered	T1,T4,T22
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T22,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T22
DebounceSt->IdleSt	163	Covered	T39,T163,T77
DetectSt->IdleSt	186	Covered	T4,T38,T39
DetectSt->StableSt	191	Covered	T1,T22,T25
IdleSt->DebounceSt	148	Covered	T1,T4,T22
StableSt->IdleSt	206	Covered	T1,T22,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T22
0	1	Covered	T1,T4,T22
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T22
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T163,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T22
DetectSt	-	-	-	-	1	-	-	Covered	T4,T38,T39
DetectSt	-	-	-	-	0	1	-	Covered	T1,T22,T25
DetectSt	-	-	-	-	0	0	-	Covered	T1,T4,T22
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T25
StableSt	-	-	-	-	-	-	0	Covered	T1,T22,T25
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	3073	0	0
CntIncr_A	7311466	97271	0	0
CntNoWrap_A	7311466	6610828	0	0
DetectStDropOut_A	7311466	539	0	0
DetectedOut_A	7311466	64381	0	0
DetectedPulseOut_A	7311466	762	0	0
DisabledIdleSt_A	7311466	6185063	0	0
DisabledNoDetection_A	7311466	6187341	0	0
EnterDebounceSt_A	7311466	1557	0	0
EnterDetectSt_A	7311466	1517	0	0
EnterStableSt_A	7311466	762	0	0
PulseIsPulse_A	7311466	762	0	0
StayInStableSt	7311466	63519	0	0
gen_high_event_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	643	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	3073	0	0
T1	13960	46	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	44	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	16	0	0
T25	0	28	0	0
T26	0	50	0	0
T38	0	24	0	0
T39	0	16	0	0
T56	0	50	0	0
T57	0	20	0	0
T58	0	40	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	97271	0	0
T1	13960	1265	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	857	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	456	0	0
T25	0	756	0	0
T26	0	1396	0	0
T38	0	403	0	0
T39	0	405	0	0
T56	0	1377	0	0
T57	0	560	0	0
T58	0	820	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6610828	0	0
T1	13960	13507	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4122	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	539	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	22	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T56	0	25	0	0
T57	0	5	0	0
T68	0	14	0	0
T74	0	9	0	0
T75	0	7	0	0
T77	0	22	0	0
T109	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	64381	0	0
T1	13960	1770	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	305	0	0
T25	0	1077	0	0
T39	0	317	0	0
T58	0	1278	0	0
T67	0	197	0	0
T96	0	1181	0	0
T232	0	2192	0	0
T233	0	167	0	0
T234	0	3806	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	762	0	0
T1	13960	23	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	8	0	0
T25	0	14	0	0
T39	0	5	0	0
T58	0	20	0	0
T67	0	4	0	0
T96	0	25	0	0
T232	0	29	0	0
T233	0	3	0	0
T234	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6185063	0	0
T1	13960	8289	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	2015	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6187341	0	0
T1	13960	8289	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	2015	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1557	0	0
T1	13960	23	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	22	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	8	0	0
T25	0	14	0	0
T26	0	25	0	0
T38	0	12	0	0
T39	0	9	0	0
T56	0	25	0	0
T57	0	10	0	0
T58	0	20	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1517	0	0
T1	13960	23	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	22	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	8	0	0
T25	0	14	0	0
T26	0	25	0	0
T38	0	12	0	0
T39	0	7	0	0
T56	0	25	0	0
T57	0	10	0	0
T58	0	20	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	762	0	0
T1	13960	23	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	8	0	0
T25	0	14	0	0
T39	0	5	0	0
T58	0	20	0	0
T67	0	4	0	0
T96	0	25	0	0
T232	0	29	0	0
T233	0	3	0	0
T234	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	762	0	0
T1	13960	23	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	8	0	0
T25	0	14	0	0
T39	0	5	0	0
T58	0	20	0	0
T67	0	4	0	0
T96	0	25	0	0
T232	0	29	0	0
T233	0	3	0	0
T234	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	63519	0	0
T1	13960	1744	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	297	0	0
T25	0	1057	0	0
T39	0	312	0	0
T58	0	1253	0	0
T67	0	192	0	0
T96	0	1155	0	0
T232	0	2163	0	0
T233	0	164	0	0
T234	0	3773	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	643	0	0
T1	13960	20	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	8	0	0
T25	0	8	0	0
T39	0	4	0	0
T58	0	15	0	0
T67	0	3	0	0
T96	0	24	0	0
T232	0	29	0	0
T233	0	3	0	0
T234	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T11,T62,T61
1	0	Covered	T39,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
1	0	Covered	T39,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T9
1	-	Covered	T1,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T9
DetectSt	168	Covered	T1,T8,T9
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T9
DebounceSt->IdleSt	163	Covered	T39,T232,T235
DetectSt->IdleSt	186	Covered	T11,T39,T62
DetectSt->StableSt	191	Covered	T1,T8,T9
IdleSt->DebounceSt	148	Covered	T1,T8,T9
StableSt->IdleSt	206	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T232,T235,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T11,T39,T62
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	814	0	0
CntIncr_A	7311466	45269	0	0
CntNoWrap_A	7311466	6613087	0	0
DetectStDropOut_A	7311466	73	0	0
DetectedOut_A	7311466	13697	0	0
DetectedPulseOut_A	7311466	307	0	0
DisabledIdleSt_A	7311466	6240171	0	0
DisabledNoDetection_A	7311466	6242008	0	0
EnterDebounceSt_A	7311466	430	0	0
EnterDetectSt_A	7311466	384	0	0
EnterStableSt_A	7311466	307	0	0
PulseIsPulse_A	7311466	307	0	0
StayInStableSt	7311466	13357	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	271	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	814	0	0
T1	13960	6	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	4	0	0
T9	0	4	0	0
T11	0	6	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	6	0	0
T28	0	4	0	0
T39	0	8	0	0
T58	0	8	0	0
T61	0	2	0	0
T62	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	45269	0	0
T1	13960	117	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	422	0	0
T9	0	352	0	0
T11	0	333	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	195	0	0
T28	0	193	0	0
T39	0	153	0	0
T58	0	156	0	0
T61	0	74	0	0
T62	0	460	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613087	0	0
T1	13960	13547	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	73	0	0
T11	15749	3	0	0
T29	978	0	0	0
T53	506	0	0	0
T54	502	0	0	0
T55	531	0	0	0
T61	0	1	0	0
T62	0	3	0	0
T80	0	1	0	0
T81	0	6	0	0
T103	866	0	0	0
T104	403	0	0	0
T149	0	7	0	0
T154	0	5	0	0
T228	422	0	0	0
T229	422	0	0	0
T230	418	0	0	0
T236	0	12	0	0
T237	0	3	0	0
T238	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	13697	0	0
T1	13960	211	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	12	0	0
T9	0	32	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	130	0	0
T27	0	8	0	0
T28	0	118	0	0
T39	0	97	0	0
T58	0	197	0	0
T96	0	63	0	0
T235	0	24	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	307	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	3	0	0
T27	0	1	0	0
T28	0	2	0	0
T39	0	1	0	0
T58	0	4	0	0
T96	0	1	0	0
T235	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6240171	0	0
T1	13960	11786	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6242008	0	0
T1	13960	11787	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	430	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T11	0	3	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	3	0	0
T28	0	2	0	0
T39	0	5	0	0
T58	0	4	0	0
T61	0	1	0	0
T62	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	384	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T11	0	3	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	3	0	0
T28	0	2	0	0
T39	0	3	0	0
T58	0	4	0	0
T61	0	1	0	0
T62	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	307	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	3	0	0
T27	0	1	0	0
T28	0	2	0	0
T39	0	1	0	0
T58	0	4	0	0
T96	0	1	0	0
T235	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	307	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	3	0	0
T27	0	1	0	0
T28	0	2	0	0
T39	0	1	0	0
T58	0	4	0	0
T96	0	1	0	0
T235	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	13357	0	0
T1	13960	208	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	10	0	0
T9	0	30	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	126	0	0
T27	0	7	0	0
T28	0	116	0	0
T39	0	96	0	0
T58	0	189	0	0
T96	0	62	0	0
T235	0	20	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	271	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T25	0	2	0	0
T27	0	1	0	0
T28	0	2	0	0
T96	0	1	0	0
T98	0	2	0	0
T235	0	2	0	0
T239	0	4	0	0