Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T22
1	0	Covered	T1,T22,T25
1	1	Covered	T1,T4,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T25
0	1	Covered	T4,T26,T56
1	0	Covered	T26,T57,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T25
0	1	Covered	T1,T22,T25
1	0	Covered	T67,T240

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T22,T25
1	-	Covered	T1,T22,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T22
DetectSt	168	Covered	T1,T4,T22
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T22,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T22
DebounceSt->IdleSt	163	Covered	T39,T163,T77
DetectSt->IdleSt	186	Covered	T4,T26,T56
DetectSt->StableSt	191	Covered	T1,T22,T25
IdleSt->DebounceSt	148	Covered	T1,T4,T22
StableSt->IdleSt	206	Covered	T1,T22,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T22
0	1	Covered	T1,T4,T22
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T22
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T163,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T22
DetectSt	-	-	-	-	1	-	-	Covered	T4,T26,T56
DetectSt	-	-	-	-	0	1	-	Covered	T1,T22,T25
DetectSt	-	-	-	-	0	0	-	Covered	T1,T22,T25
StableSt	-	-	-	-	-	-	1	Covered	T1,T22,T25
StableSt	-	-	-	-	-	-	0	Covered	T1,T22,T25
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	3056	0	0
CntIncr_A	7311466	101358	0	0
CntNoWrap_A	7311466	6610845	0	0
DetectStDropOut_A	7311466	503	0	0
DetectedOut_A	7311466	61279	0	0
DetectedPulseOut_A	7311466	789	0	0
DisabledIdleSt_A	7311466	6186604	0	0
DisabledNoDetection_A	7311466	6188897	0	0
EnterDebounceSt_A	7311466	1550	0	0
EnterDetectSt_A	7311466	1507	0	0
EnterStableSt_A	7311466	789	0	0
PulseIsPulse_A	7311466	789	0	0
StayInStableSt	7311466	60405	0	0
gen_high_event_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	695	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	3056	0	0
T1	13960	8	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	6	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	46	0	0
T25	0	28	0	0
T26	0	30	0	0
T38	0	22	0	0
T39	0	14	0	0
T56	0	52	0	0
T57	0	22	0	0
T58	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	101358	0	0
T1	13960	228	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	114	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	1587	0	0
T25	0	574	0	0
T26	0	830	0	0
T38	0	319	0	0
T39	0	282	0	0
T56	0	1430	0	0
T57	0	624	0	0
T58	0	147	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6610845	0	0
T1	13960	13545	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4160	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	503	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	3	0	0
T5	6258	0	0	0
T6	482	0	0	0
T7	2218	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T26	0	4	0	0
T56	0	26	0	0
T74	0	12	0	0
T75	0	20	0	0
T77	0	19	0	0
T78	0	15	0	0
T165	0	2	0	0
T219	0	22	0	0
T241	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	61279	0	0
T1	13960	197	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	343	0	0
T25	0	1259	0	0
T38	0	67	0	0
T39	0	290	0	0
T58	0	155	0	0
T67	0	1	0	0
T96	0	1176	0	0
T232	0	354	0	0
T234	0	1747	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	789	0	0
T1	13960	4	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	23	0	0
T25	0	14	0	0
T38	0	11	0	0
T39	0	5	0	0
T58	0	3	0	0
T67	0	1	0	0
T96	0	22	0	0
T232	0	16	0	0
T234	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6186604	0	0
T1	13960	9504	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	2015	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6188897	0	0
T1	13960	9506	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	2015	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1550	0	0
T1	13960	4	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	3	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	23	0	0
T25	0	14	0	0
T26	0	15	0	0
T38	0	11	0	0
T39	0	9	0	0
T56	0	26	0	0
T57	0	11	0	0
T58	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	1507	0	0
T1	13960	4	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	3	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	23	0	0
T25	0	14	0	0
T26	0	15	0	0
T38	0	11	0	0
T39	0	5	0	0
T56	0	26	0	0
T57	0	11	0	0
T58	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	789	0	0
T1	13960	4	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	23	0	0
T25	0	14	0	0
T38	0	11	0	0
T39	0	5	0	0
T58	0	3	0	0
T67	0	1	0	0
T96	0	22	0	0
T232	0	16	0	0
T234	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	789	0	0
T1	13960	4	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	23	0	0
T25	0	14	0	0
T38	0	11	0	0
T39	0	5	0	0
T58	0	3	0	0
T67	0	1	0	0
T96	0	22	0	0
T232	0	16	0	0
T234	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	60405	0	0
T1	13960	192	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	320	0	0
T25	0	1239	0	0
T38	0	56	0	0
T39	0	285	0	0
T58	0	151	0	0
T96	0	1153	0	0
T163	0	94	0	0
T232	0	338	0	0
T234	0	1725	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	695	0	0
T1	13960	3	0	0
T2	647	0	0	0
T3	645	0	0	0
T4	4567	0	0	0
T5	6258	0	0	0
T6	482	0	0	0
T12	659	0	0	0
T13	1385	0	0	0
T14	2733	0	0	0
T15	402	0	0	0
T22	0	23	0	0
T25	0	8	0	0
T38	0	11	0	0
T39	0	5	0	0
T58	0	2	0	0
T96	0	21	0	0
T163	0	1	0	0
T232	0	16	0	0
T234	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T8,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T4,T13
1	1	Covered	T8,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T11
0	1	Covered	T11,T242,T236
1	0	Covered	T39,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T25
0	1	Covered	T8,T9,T25
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T25
1	-	Covered	T8,T9,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T11
DetectSt	168	Covered	T8,T9,T11
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T9,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T11
DebounceSt->IdleSt	163	Covered	T39,T235,T76
DetectSt->IdleSt	186	Covered	T11,T39,T242
DetectSt->StableSt	191	Covered	T8,T9,T25
IdleSt->DebounceSt	148	Covered	T8,T9,T11
StableSt->IdleSt	206	Covered	T8,T9,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T11
0	1	Covered	T8,T9,T11
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T11
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T235,T76,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T11,T39,T242
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T25
DetectSt	-	-	-	-	0	0	-	Covered	T8,T9,T11
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T25
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7311466	725	0	0
CntIncr_A	7311466	40214	0	0
CntNoWrap_A	7311466	6613176	0	0
DetectStDropOut_A	7311466	35	0	0
DetectedOut_A	7311466	15765	0	0
DetectedPulseOut_A	7311466	308	0	0
DisabledIdleSt_A	7311466	6244061	0	0
DisabledNoDetection_A	7311466	6245924	0	0
EnterDebounceSt_A	7311466	378	0	0
EnterDetectSt_A	7311466	347	0	0
EnterStableSt_A	7311466	308	0	0
PulseIsPulse_A	7311466	308	0	0
StayInStableSt	7311466	15430	0	0
gen_high_level_sva.HighLevelEvent_A	7311466	6616370	0	0
gen_not_sticky_sva.StableStDropOut_A	7311466	279	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	725	0	0
T8	17745	4	0	0
T9	20631	8	0	0
T10	19176	0	0	0
T11	0	6	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	10	0	0
T27	0	4	0	0
T28	0	4	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	8	0	0
T41	817	0	0	0
T42	439	0	0	0
T58	0	2	0	0
T61	0	6	0	0
T62	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	40214	0	0
T8	17745	324	0	0
T9	20631	721	0	0
T10	19176	0	0	0
T11	0	335	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	360	0	0
T27	0	280	0	0
T28	0	213	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	126	0	0
T41	817	0	0	0
T42	439	0	0	0
T58	0	48	0	0
T61	0	171	0	0
T62	0	596	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6613176	0	0
T1	13960	13553	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	35	0	0
T11	15749	3	0	0
T29	978	0	0	0
T53	506	0	0	0
T54	502	0	0	0
T55	531	0	0	0
T103	866	0	0	0
T104	403	0	0	0
T192	0	2	0	0
T225	0	5	0	0
T228	422	0	0	0
T229	422	0	0	0
T230	418	0	0	0
T236	0	2	0	0
T242	0	2	0	0
T243	0	5	0	0
T244	0	2	0	0
T245	0	2	0	0
T246	0	3	0	0
T247	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	15765	0	0
T8	17745	110	0	0
T9	20631	22	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	183	0	0
T27	0	67	0	0
T28	0	11	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	95	0	0
T41	817	0	0	0
T42	439	0	0	0
T58	0	41	0	0
T61	0	51	0	0
T62	0	17	0	0
T235	0	16	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	308	0	0
T8	17745	2	0	0
T9	20631	4	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	5	0	0
T27	0	2	0	0
T28	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	1	0	0
T41	817	0	0	0
T42	439	0	0	0
T58	0	1	0	0
T61	0	3	0	0
T62	0	4	0	0
T235	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6244061	0	0
T1	13960	13357	0	0
T2	647	246	0	0
T3	645	244	0	0
T4	4567	4166	0	0
T5	6258	3374	0	0
T6	482	81	0	0
T12	659	258	0	0
T13	1385	183	0	0
T14	2733	328	0	0
T15	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6245924	0	0
T1	13960	13360	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	378	0	0
T8	17745	2	0	0
T9	20631	4	0	0
T10	19176	0	0	0
T11	0	3	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	5	0	0
T27	0	2	0	0
T28	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	5	0	0
T41	817	0	0	0
T42	439	0	0	0
T58	0	1	0	0
T61	0	3	0	0
T62	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	347	0	0
T8	17745	2	0	0
T9	20631	4	0	0
T10	19176	0	0	0
T11	0	3	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	5	0	0
T27	0	2	0	0
T28	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	3	0	0
T41	817	0	0	0
T42	439	0	0	0
T58	0	1	0	0
T61	0	3	0	0
T62	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	308	0	0
T8	17745	2	0	0
T9	20631	4	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	5	0	0
T27	0	2	0	0
T28	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	1	0	0
T41	817	0	0	0
T42	439	0	0	0
T58	0	1	0	0
T61	0	3	0	0
T62	0	4	0	0
T235	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	308	0	0
T8	17745	2	0	0
T9	20631	4	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	5	0	0
T27	0	2	0	0
T28	0	2	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	1	0	0
T41	817	0	0	0
T42	439	0	0	0
T58	0	1	0	0
T61	0	3	0	0
T62	0	4	0	0
T235	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	15430	0	0
T8	17745	108	0	0
T9	20631	18	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	178	0	0
T27	0	65	0	0
T28	0	8	0	0
T33	36658	0	0	0
T34	671	0	0	0
T39	0	94	0	0
T41	817	0	0	0
T42	439	0	0	0
T58	0	40	0	0
T61	0	48	0	0
T62	0	13	0	0
T235	0	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	6616370	0	0
T1	13960	13557	0	0
T2	647	247	0	0
T3	645	245	0	0
T4	4567	4167	0	0
T5	6258	3383	0	0
T6	482	82	0	0
T12	659	259	0	0
T13	1385	185	0	0
T14	2733	333	0	0
T15	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7311466	279	0	0
T8	17745	2	0	0
T9	20631	4	0	0
T10	19176	0	0	0
T21	4200	0	0	0
T22	10081	0	0	0
T24	699	0	0	0
T25	0	5	0	0
T27	0	2	0	0
T28	0	1	0	0
T33	36658	0	0	0
T34	671	0	0	0
T41	817	0	0	0
T42	439	0	0	0
T58	0	1	0	0
T61	0	3	0	0
T62	0	4	0	0
T98	0	1	0	0
T235	0	1	0	0