Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1164148137	11137	0	0
auto_block_debounce_ctl_rd_A	1164148137	2090	0	0
auto_block_out_ctl_rd_A	1164148137	2541	0	0
com_det_ctl_0_rd_A	1164148137	4084	0	0
com_det_ctl_1_rd_A	1164148137	3984	0	0
com_det_ctl_2_rd_A	1164148137	3926	0	0
com_det_ctl_3_rd_A	1164148137	3981	0	0
com_out_ctl_0_rd_A	1164148137	4478	0	0
com_out_ctl_1_rd_A	1164148137	4259	0	0
com_out_ctl_2_rd_A	1164148137	4269	0	0
com_out_ctl_3_rd_A	1164148137	4461	0	0
com_pre_det_ctl_0_rd_A	1164148137	1746	0	0
com_pre_det_ctl_1_rd_A	1164148137	1704	0	0
com_pre_det_ctl_2_rd_A	1164148137	1892	0	0
com_pre_det_ctl_3_rd_A	1164148137	1919	0	0
com_pre_sel_ctl_0_rd_A	1164148137	4529	0	0
com_pre_sel_ctl_1_rd_A	1164148137	4667	0	0
com_pre_sel_ctl_2_rd_A	1164148137	4536	0	0
com_pre_sel_ctl_3_rd_A	1164148137	4487	0	0
com_sel_ctl_0_rd_A	1164148137	4402	0	0
com_sel_ctl_1_rd_A	1164148137	4548	0	0
com_sel_ctl_2_rd_A	1164148137	4565	0	0
com_sel_ctl_3_rd_A	1164148137	4464	0	0
ec_rst_ctl_rd_A	1164148137	2784	0	0
intr_enable_rd_A	1164148137	2354	0	0
key_intr_ctl_rd_A	1164148137	3389	0	0
key_intr_debounce_ctl_rd_A	1164148137	1865	0	0
key_invert_ctl_rd_A	1164148137	5128	0	0
pin_allowed_ctl_rd_A	1164148137	5774	0	0
pin_out_ctl_rd_A	1164148137	4272	0	0
pin_out_value_rd_A	1164148137	4479	0	0
regwen_rd_A	1164148137	1883	0	0
ulp_ac_debounce_ctl_rd_A	1164148137	1852	0	0
ulp_ctl_rd_A	1164148137	1860	0	0
ulp_lid_debounce_ctl_rd_A	1164148137	2235	0	0
ulp_pwrb_debounce_ctl_rd_A	1164148137	1956	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	11137	0	0
T5	751098	10	0	0
T6	55514	0	0	0
T7	257597	0	0	0
T8	830950	23	0	0
T9	223471	3	0	0
T10	0	5	0	0
T15	193193	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T28	0	17	0	0
T32	0	15	0	0
T33	256607	0	0	0
T70	0	9	0	0
T89	0	1	0	0
T136	0	6	0	0
T267	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	2090	0	0
T3	322586	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T7	257597	0	0	0
T8	830950	0	0	0
T9	223471	35	0	0
T12	329548	12	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	9	0	0
T36	0	15	0	0
T37	0	10	0	0
T136	0	23	0	0
T268	0	5	0	0
T269	0	17	0	0
T270	0	8	0	0
T271	0	7	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	2541	0	0
T3	322586	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T7	257597	0	0	0
T8	830950	0	0	0
T9	223471	38	0	0
T12	329548	6	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	24	0	0
T36	0	8	0	0
T37	0	14	0	0
T136	0	19	0	0
T268	0	1	0	0
T269	0	30	0	0
T270	0	11	0	0
T271	0	6	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4084	0	0
T1	167514	51	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	40	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	17	0	0
T67	0	56	0	0
T68	0	26	0	0
T76	0	82	0	0
T109	0	26	0	0
T136	0	10	0	0
T234	0	21	0	0
T272	0	88	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	3984	0	0
T1	167514	39	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	57	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	10	0	0
T67	0	82	0	0
T68	0	34	0	0
T76	0	75	0	0
T109	0	25	0	0
T136	0	22	0	0
T234	0	18	0	0
T272	0	67	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	3926	0	0
T1	167514	34	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	102	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	20	0	0
T67	0	72	0	0
T68	0	29	0	0
T76	0	62	0	0
T109	0	28	0	0
T136	0	4	0	0
T234	0	46	0	0
T272	0	54	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	3981	0	0
T1	167514	38	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	33	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	10	0	0
T67	0	63	0	0
T68	0	38	0	0
T76	0	76	0	0
T109	0	20	0	0
T136	0	8	0	0
T234	0	48	0	0
T272	0	51	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4478	0	0
T1	167514	52	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	49	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	13	0	0
T67	0	63	0	0
T68	0	6	0	0
T76	0	79	0	0
T109	0	18	0	0
T136	0	27	0	0
T234	0	31	0	0
T272	0	76	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4259	0	0
T1	167514	47	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	45	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	11	0	0
T67	0	59	0	0
T68	0	7	0	0
T76	0	78	0	0
T109	0	18	0	0
T136	0	22	0	0
T234	0	34	0	0
T272	0	76	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4269	0	0
T1	167514	48	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	42	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	11	0	0
T67	0	59	0	0
T68	0	27	0	0
T76	0	75	0	0
T109	0	12	0	0
T136	0	18	0	0
T234	0	32	0	0
T272	0	68	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4461	0	0
T1	167514	52	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	60	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	10	0	0
T67	0	95	0	0
T68	0	36	0	0
T76	0	85	0	0
T109	0	13	0	0
T136	0	17	0	0
T234	0	54	0	0
T272	0	69	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	1746	0	0
T9	223471	14	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	9	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T69	0	40	0	0
T80	0	21	0	0
T127	0	24	0	0
T133	0	24	0	0
T136	0	12	0	0
T244	0	37	0	0
T273	0	14	0	0
T274	0	27	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	1704	0	0
T9	223471	12	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	10	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T69	0	16	0	0
T80	0	18	0	0
T127	0	40	0	0
T133	0	23	0	0
T136	0	18	0	0
T192	0	19	0	0
T244	0	16	0	0
T273	0	17	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	1892	0	0
T9	223471	15	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	13	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T69	0	12	0	0
T80	0	16	0	0
T127	0	31	0	0
T133	0	32	0	0
T136	0	14	0	0
T244	0	16	0	0
T273	0	17	0	0
T274	0	17	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	1919	0	0
T9	223471	23	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	15	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T69	0	31	0	0
T80	0	19	0	0
T127	0	21	0	0
T133	0	42	0	0
T136	0	26	0	0
T244	0	30	0	0
T273	0	12	0	0
T275	0	5	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4529	0	0
T1	167514	31	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	59	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	19	0	0
T67	0	89	0	0
T68	0	28	0	0
T76	0	80	0	0
T109	0	12	0	0
T136	0	16	0	0
T234	0	40	0	0
T272	0	78	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4667	0	0
T1	167514	36	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	61	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	21	0	0
T67	0	67	0	0
T68	0	16	0	0
T76	0	68	0	0
T109	0	28	0	0
T136	0	19	0	0
T234	0	32	0	0
T272	0	58	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4536	0	0
T1	167514	34	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	61	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	18	0	0
T67	0	59	0	0
T68	0	28	0	0
T76	0	85	0	0
T109	0	26	0	0
T136	0	19	0	0
T234	0	61	0	0
T272	0	55	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4487	0	0
T1	167514	51	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	52	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	21	0	0
T67	0	57	0	0
T68	0	40	0	0
T76	0	74	0	0
T109	0	27	0	0
T136	0	16	0	0
T234	0	31	0	0
T272	0	77	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4402	0	0
T1	167514	54	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	45	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	6	0	0
T67	0	70	0	0
T68	0	16	0	0
T76	0	57	0	0
T109	0	37	0	0
T136	0	13	0	0
T234	0	19	0	0
T272	0	73	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4548	0	0
T1	167514	36	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	70	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	16	0	0
T67	0	83	0	0
T68	0	37	0	0
T76	0	76	0	0
T109	0	21	0	0
T136	0	22	0	0
T234	0	23	0	0
T272	0	79	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4565	0	0
T1	167514	39	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	58	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	14	0	0
T67	0	80	0	0
T68	0	32	0	0
T76	0	56	0	0
T109	0	22	0	0
T136	0	20	0	0
T234	0	38	0	0
T272	0	56	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4464	0	0
T1	167514	44	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	46	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	14	0	0
T67	0	51	0	0
T68	0	36	0	0
T76	0	75	0	0
T109	0	11	0	0
T136	0	13	0	0
T234	0	41	0	0
T272	0	82	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	2784	0	0
T1	167514	16	0	0
T2	42302	0	0	0
T3	322586	0	0	0
T4	111913	0	0	0
T5	751098	0	0	0
T6	55514	0	0	0
T9	0	38	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	38	0	0
T39	0	5	0	0
T67	0	19	0	0
T68	0	9	0	0
T75	0	2	0	0
T136	0	16	0	0
T163	0	1	0	0
T234	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	2354	0	0
T9	223471	20	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	30	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T80	0	74	0	0
T127	0	54	0	0
T133	0	30	0	0
T136	0	20	0	0
T244	0	44	0	0
T273	0	10	0	0
T275	0	36	0	0
T276	0	15	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	3389	0	0
T2	42302	3	0	0
T3	322586	0	0	0
T5	751098	0	0	0
T6	55514	2	0	0
T7	257597	0	0	0
T8	830950	0	0	0
T9	0	13	0	0
T12	329548	0	0	0
T13	48484	0	0	0
T14	131170	0	0	0
T15	193193	0	0	0
T27	0	34	0	0
T30	0	1	0	0
T39	0	80	0	0
T65	0	4	0	0
T123	0	8	0	0
T136	0	20	0	0
T168	0	2	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	1865	0	0
T9	223471	10	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	10	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T69	0	39	0	0
T80	0	35	0	0
T127	0	30	0	0
T133	0	40	0	0
T136	0	24	0	0
T244	0	22	0	0
T273	0	17	0	0
T274	0	1	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	5128	0	0
T9	223471	114	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	126	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T48	0	71	0	0
T49	0	45	0	0
T52	0	97	0	0
T80	0	252	0	0
T127	0	97	0	0
T136	0	16	0	0
T277	0	60	0	0
T278	0	32	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	5774	0	0
T9	223471	10	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	166	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T80	0	88	0	0
T127	0	75	0	0
T136	0	91	0	0
T244	0	85	0	0
T279	0	50	0	0
T280	0	70	0	0
T281	0	79	0	0
T282	0	47	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4272	0	0
T9	223471	29	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	207	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T80	0	82	0	0
T127	0	92	0	0
T136	0	86	0	0
T244	0	87	0	0
T279	0	32	0	0
T280	0	60	0	0
T281	0	65	0	0
T282	0	35	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	4479	0	0
T9	223471	14	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	137	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T80	0	96	0	0
T127	0	99	0	0
T136	0	87	0	0
T244	0	96	0	0
T279	0	54	0	0
T280	0	95	0	0
T281	0	49	0	0
T282	0	31	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	1883	0	0
T9	223471	22	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T46	69428	0	0	0
T69	0	35	0	0
T80	0	19	0	0
T127	0	24	0	0
T133	0	13	0	0
T136	0	16	0	0
T244	0	34	0	0
T273	0	6	0	0
T274	0	12	0	0
T275	0	1	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	1852	0	0
T9	223471	12	0	0
T10	544797	0	0	0
T20	0	4	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	22	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T43	0	9	0	0
T46	69428	0	0	0
T97	0	6	0	0
T127	0	25	0	0
T136	0	9	0	0
T283	0	1	0	0
T284	0	6	0	0
T285	0	9	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	1860	0	0
T9	223471	16	0	0
T10	544797	0	0	0
T20	0	1	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	12	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T43	0	3	0	0
T46	69428	0	0	0
T59	0	3	0	0
T97	0	10	0	0
T136	0	17	0	0
T283	0	1	0	0
T284	0	2	0	0
T285	0	13	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	2235	0	0
T9	223471	31	0	0
T10	544797	0	0	0
T20	0	5	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	2	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T43	0	5	0	0
T46	69428	0	0	0
T52	0	2	0	0
T59	0	15	0	0
T97	0	6	0	0
T136	0	15	0	0
T283	0	3	0	0
T284	0	8	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164148137	1956	0	0
T9	223471	10	0	0
T10	544797	0	0	0
T21	163829	0	0	0
T22	504075	0	0	0
T24	202604	0	0	0
T27	0	29	0	0
T33	256607	0	0	0
T34	322197	0	0	0
T41	388390	0	0	0
T42	13173	0	0	0
T43	0	1	0	0
T46	69428	0	0	0
T59	0	12	0	0
T97	0	16	0	0
T127	0	42	0	0
T136	0	12	0	0
T283	0	5	0	0
T284	0	1	0	0
T285	0	10	0	0