Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.56	97.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	97.56	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.56	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	2	60	96.77

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	2	29	93.55	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1784

1

T3

9

T9

4

T29

13

auto[1]

722

1

T1

5

T3

6

T29

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1898

1

T1

3

T3

12

T9

3

auto[1]

608

1

T1

2

T3

3

T9

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1871

1

T1

3

T9

1

T33

8

auto[1]

635

1

T1

2

T3

15

T9

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1900

1

T1

4

T3

6

T9

3

auto[1]

606

1

T1

1

T3

9

T9

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2393

1

T1

5

T3

15

T9

4

auto[1]

113

1

T30

2

T67

5

T68

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2254

1

T1

5

T3

15

T9

4

auto[1]

252

1

T30

1

T66

3

T67

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2296

1

T1

5

T3

15

T9

4

auto[1]

210

1

T34

5

T30

2

T244

7

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2252

1

T1

5

T3

15

T9

4

auto[1]

254

1

T33

2

T34

13

T30

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2301

1

T1

5

T3

15

T9

4

auto[1]

205

1

T34

7

T67

10

T68

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1993

1

T1

4

T3

12

T9

3

auto[1]

513

1

T1

1

T3

3

T9

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	2	29	93.55	2
Automatically Generated Cross Bins	31	2	29	93.55	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	907	1			T1	5		T3	15		T9	4
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	14	1			T356	3		T357	8		T358	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	85	1			T34	7		T67	7		T263	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	3	1			T263	3		-	-		-	-
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	120	1			T33	2		T34	8		T67	12
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	11	1			T244	2		T359	3		T360	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	23	1			T67	3		T78	4		T334	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T78	2		T247	2		T218	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	73	1			T244	7		T268	1		T361	10
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	12	1			T30	2		T263	4		T362	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	13	1			T78	2		T363	2		T348	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	9	1			T263	3		T339	6		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	17	1			T34	5		T357	3		T364	6
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T363	1		T365	2		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T366	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	95	1			T68	5		T363	8		T227	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	13	1			T361	1		T348	1		T215	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	24	1			T187	2		T247	1		T367	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T68	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	34	1			T30	1		T334	7		T267	8
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	8	1			T67	5		T368	3		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	4	1			T365	4		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	15	1			T334	2		T92	4		T369	9
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	13	1			T356	2		T369	6		T347	3
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T339	4		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	7	1			T370	2		T339	4		T360	1
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	8	1			T334	2		T347	3		T371	3
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T368	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T79	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

165

1

T1

3

T32

18

T34

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

91

1

T67

12

T363

4

T361

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

51

1

T338

5

T334

2

T188

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

138

1

T264

10

T36

6

T78

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

50

1

T31

6

T207

7

T210

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T263

4

T221

3

T372

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T31

2

T334

2

T361

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

92

1

T9

3

T29

13

T67

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

82

1

T30

1

T67

3

T68

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

63

1

T90

7

T270

6

T230

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

36

1

T3

3

T79

2

T333

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

53

1

T3

9

T266

5

T191

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T20

1

T68

5

T265

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T338

1

T356

3

T215

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T29

2

T333

3

T373

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

175

1

T34

5

T31

4

T244

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

44

1

T33

2

T31

6

T269

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

20

1

T374

6

T159

3

T375

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T175

4

T159

2

T376

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T30

2

T67

7

T266

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T270

1

T268

1

T377

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T9

1

T91

6

T163

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T159

1

T188

3

T376

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T34

8

T264

6

T244

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

40

1

T1

1

T3

3

T266

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

22

1

T208

2

T376

1

T378

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T90

2

T369

12

T379

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

29

1

T20

1

T32

3

T96

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T86

2

T272

1

T346

12

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T208

1

T100

1

T380

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T1

1

T272

1

T381

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded