Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T1

9

T13

9

T46

8

auto[1]

1056

1

T1

11

T13

11

T46

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

504

1

T1

6

T13

5

T46

5

from_0to1

490

1

T1

6

T13

4

T46

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T1

8

T13

13

T46

11

auto[1]

1040

1

T1

12

T13

7

T46

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T1

8

T13

12

T46

7

auto[1]

1082

1

T1

12

T13

8

T46

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T13

1

T9

1

T62

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T1

2

T46

1

T9

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T1

2

T9

1

T261

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T46

1

T9

1

T64

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T13

1

T62

2

T64

1

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T1

1

T46

1

T62

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T1

1

T13

1

T9

3

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T13

1

T64

1

T151

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T13

1

T62

2

T64

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T1

1

T13

2

T9

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T1

1

T13

1

T9

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T46

3

T106

1

T261

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T1

1

T13

1

T46

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T1

1

T46

1

T9

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T1

2

T46

1

T9

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T46

1

T64

1

T151

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T1

9

T13

10

T46

7

auto[1]

1035

1

T1

11

T13

10

T46

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

514

1

T1

5

T13

2

T46

4

from_0to1

509

1

T1

6

T13

2

T46

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T1

11

T13

7

T46

6

auto[1]

1055

1

T1

9

T13

13

T46

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042

1

T1

7

T13

9

T46

11

auto[1]

1072

1

T1

13

T13

11

T46

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T1

1

T9

1

T151

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T1

1

T13

1

T46

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T20

1

T261

3

T299

2

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T46

1

T9

1

T62

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T9

1

T64

1

T149

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T13

1

T9

2

T62

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T46

3

T62

2

T149

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T1

1

T13

1

T149

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T13

1

T64

1

T149

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T1

1

T46

1

T62

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T1

1

T46

1

T9

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T1

1

T9

1

T62

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T1

1

T64

2

T20

2

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T1

1

T261

2

T390

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T1

1

T46

1

T62

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T1

2

T9

1

T62

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T1

10

T13

9

T46

10

auto[1]

1053

1

T1

10

T13

11

T46

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

520

1

T1

6

T13

4

T46

3

from_0to1

521

1

T1

5

T13

5

T46

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T1

10

T13

8

T46

9

auto[1]

1074

1

T1

10

T13

12

T46

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T1

11

T13

11

T46

10

auto[1]

1055

1

T1

9

T13

9

T46

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T1

1

T9

2

T62

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T13

1

T46

1

T62

2

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T1

2

T13

1

T46

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T1

2

T13

1

T64

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T46

1

T64

1

T149

1

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T1

2

T62

3

T151

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T13

2

T9

1

T64

1

auto[0]

from_0to1

auto[1]

auto[1]

81

1

T1

1

T64

1

T149

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T46

1

T9

1

T64

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T1

1

T9

1

T64

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T9

1

T64

1

T149

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T13

1

T9

1

T20

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T1

2

T46

1

T62

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T64

2

T149

2

T106

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T13

2

T9

4

T64

1

auto[1]

from_0to1

auto[1]

auto[1]

45

1

T13

1

T46

1

T149

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T1

7

T13

10

T46

12

auto[1]

1073

1

T1

13

T13

10

T46

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

505

1

T1

6

T13

5

T46

4

from_0to1

510

1

T1

5

T13

6

T46

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T1

13

T13

12

T46

11

auto[1]

1052

1

T1

7

T13

8

T46

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T1

7

T13

8

T46

8

auto[1]

1063

1

T1

13

T13

12

T46

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T1

1

T13

3

T46

2

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T13

1

T64

2

T151

2

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T46

1

T9

3

T62

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T9

1

T149

1

T20

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T9

1

T64

2

T149

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T1

1

T13

1

T46

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T1

2

T149

1

T20

3

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T46

2

T9

1

T149

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T1

1

T62

1

T37

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T1

2

T13

1

T62

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T1

1

T46

1

T9

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T1

1

T62

1

T151

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T9

1

T62

1

T261

3

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T1

1

T13

2

T46

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T1

1

T13

1

T9

2

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T13

2

T9

1

T64

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T1

11

T13

13

T46

10

auto[1]

1033

1

T1

9

T13

7

T46

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

506

1

T1

5

T13

6

T46

4

from_0to1

507

1

T1

5

T13

5

T46

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T1

11

T13

11

T46

12

auto[1]

1055

1

T1

9

T13

9

T46

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T1

6

T13

12

T46

7

auto[1]

1048

1

T1

14

T13

8

T46

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T1

1

T13

2

T9

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T1

2

T13

1

T9

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T13

1

T9

1

T62

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T1

2

T46

1

T9

2

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T1

1

T13

2

T62

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T13

1

T9

1

T64

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T13

1

T46

1

T151

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T149

2

T106

1

T308

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T46

2

T20

1

T37

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T46

1

T20

1

T106

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T13

1

T9

1

T62

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T13

1

T62

1

T151

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T9

1

T62

1

T64

3

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T1

3

T46

1

T9

3

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T13

1

T62

1

T20

2

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T1

1

T46

2

T62

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T1

10

T13

11

T46

9

auto[1]

1040

1

T1

10

T13

9

T46

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

510

1

T1

5

T13

4

T46

7

from_0to1

516

1

T1

5

T13

5

T46

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T1

12

T13

10

T46

13

auto[1]

1031

1

T1

8

T13

10

T46

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1015

1

T1

11

T13

9

T46

12

auto[1]

1099

1

T1

9

T13

11

T46

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T1

1

T13

1

T46

2

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T9

1

T64

1

T151

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T1

1

T46

1

T9

2

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T13

1

T9

1

T64

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T1

1

T13

1

T9

2

auto[0]

from_0to1

auto[0]

auto[1]

85

1

T13

1

T46

1

T9

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T1

1

T46

1

T9

2

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T13

2

T20

1

T261

2

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T46

1

T9

1

T62

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T1

2

T13

1

T46

2

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T13

1

T46

1

T106

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T1

1

T64

1

T149

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T1

2

T13

1

T9

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T46

1

T62

2

T64

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T46

2

T62

1

T64

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T1

1

T46

1

T149

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T1

8

T13

12

T46

15

auto[1]

1069

1

T1

12

T13

8

T46

5

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

515

1

T1

5

T13

4

T46

4

from_0to1

508

1

T1

5

T13

4

T46

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T1

11

T13

9

T46

11

auto[1]

1063

1

T1

9

T13

11

T46

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T1

14

T13

9

T46

10

auto[1]

1033

1

T1

6

T13

11

T46

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T1

1

T46

2

T9

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T46

1

T64

1

T149

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T13

1

T9

1

T62

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T13

2

T9

2

T149

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T1

1

T46

1

T9

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T1

2

T13

1

T9

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T9

1

T62

1

T64

2

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T13

2

T9

2

T151

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T1

2

T20

2

T106

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T13

1

T46

1

T9

1

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T1

2

T9

1

T62

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T62

2

T64

1

T151

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T62

2

T149

1

T151

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T13

1

T46

1

T149

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T1

1

T46

1

T64

1

auto[1]

from_0to1

auto[1]

auto[1]

81

1

T1

1

T46

1

T9

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T1

8

T13

13

T46

9

auto[1]

1005

1

T1

12

T13

7

T46

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

509

1

T1

4

T13

4

T46

4

from_0to1

506

1

T1

4

T13

4

T46

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T1

11

T13

10

T46

9

auto[1]

1059

1

T1

9

T13

10

T46

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T1

13

T13

7

T46

13

auto[1]

1042

1

T1

7

T13

13

T46

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T1

1

T9

1

T62

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T1

1

T46

1

T9

1

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T9

1

T62

2

T151

2

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T13

1

T64

2

T151

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T64

2

T20

2

T261

2

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T1

1

T13

3

T9

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T1

1

T46

1

T9

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T13

1

T46

1

T62

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T13

1

T9

1

T151

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T13

1

T151

1

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T1

2

T13

1

T46

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T46

2

T9

1

T151

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T9

1

T149

1

T20

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T1

1

T46

1

T62

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T46

2

T9

2

T62

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T1

1

T9

1

T62

1