Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120736

1

T1

429

T4

2

T5

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138696	1			T1	596		T4	2		T5	33
values[0x0]	66305	1			T1	147		T4	8		T5	12
values[0x1]	67679	1			T1	129		T4	1		T5	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	123245	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149435

1

T1

522

T4

3

T5

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	737	1			T9	8		T22	3		T64	3
valid_sources[0x01]	954	1			T9	3		T62	1		T22	5
valid_sources[0x02]	1501	1			T2	2		T14	17		T3	1
valid_sources[0x03]	779	1			T3	6		T9	1		T51	2
valid_sources[0x04]	959	1			T1	1		T3	3		T9	7
valid_sources[0x05]	785	1			T1	8		T2	1		T3	2
valid_sources[0x06]	994	1			T5	2		T3	2		T6	1
valid_sources[0x07]	1193	1			T2	1		T46	1		T9	8
valid_sources[0x08]	829	1			T6	2		T8	1		T9	8
valid_sources[0x09]	1039	1			T3	4		T8	1		T9	2
valid_sources[0x0a]	861	1			T2	1		T3	4		T6	1
valid_sources[0x0b]	908	1			T1	3		T14	1		T3	2
valid_sources[0x0c]	868	1			T1	3		T3	2		T9	9
valid_sources[0x0d]	1044	1			T1	8		T2	1		T3	2
valid_sources[0x0e]	1062	1			T14	13		T3	8		T9	1
valid_sources[0x0f]	1004	1			T5	2		T3	2		T46	1
valid_sources[0x10]	912	1			T1	7		T2	1		T3	1
valid_sources[0x11]	965	1			T3	3		T6	1		T46	1
valid_sources[0x12]	1010	1			T1	1		T2	2		T3	1
valid_sources[0x13]	1190	1			T1	1		T14	1		T3	3
valid_sources[0x14]	1072	1			T1	15		T2	1		T3	4
valid_sources[0x15]	813	1			T5	1		T3	4		T46	1
valid_sources[0x16]	930	1			T14	10		T3	5		T6	1
valid_sources[0x17]	948	1			T1	1		T3	3		T6	1
valid_sources[0x18]	798	1			T1	1		T2	2		T3	1
valid_sources[0x19]	768	1			T1	1		T14	27		T6	1
valid_sources[0x1a]	1003	1			T3	4		T6	1		T43	2
valid_sources[0x1b]	1001	1			T3	2		T46	1		T42	2
valid_sources[0x1c]	1037	1			T1	2		T14	1		T16	3
valid_sources[0x1d]	877	1			T1	18		T4	1		T3	5
valid_sources[0x1e]	1115	1			T3	3		T9	2		T62	1
valid_sources[0x1f]	777	1			T1	3		T2	1		T3	1
valid_sources[0x20]	907	1			T1	11		T3	2		T9	6
valid_sources[0x21]	867	1			T1	8		T3	1		T6	1
valid_sources[0x22]	1156	1			T2	1		T3	7		T46	2
valid_sources[0x23]	2430	1			T6	1		T9	4		T22	5
valid_sources[0x24]	956	1			T1	10		T3	2		T9	4
valid_sources[0x25]	879	1			T3	1		T9	6		T62	1
valid_sources[0x26]	900	1			T46	2		T9	6		T22	4
valid_sources[0x27]	856	1			T1	4		T3	2		T6	1
valid_sources[0x28]	1504	1			T1	2		T3	1		T6	1
valid_sources[0x29]	900	1			T14	14		T6	1		T9	2
valid_sources[0x2a]	876	1			T1	6		T3	1		T42	1
valid_sources[0x2b]	1976	1			T1	3		T9	2		T62	1
valid_sources[0x2c]	1132	1			T2	1		T3	1		T46	1
valid_sources[0x2d]	986	1			T1	17		T5	13		T14	29
valid_sources[0x2e]	941	1			T1	1		T3	1		T46	1
valid_sources[0x2f]	918	1			T1	9		T3	1		T46	1
valid_sources[0x30]	1003	1			T1	1		T5	5		T13	122
valid_sources[0x31]	984	1			T1	16		T14	10		T6	1
valid_sources[0x32]	1556	1			T1	1		T2	1		T9	4
valid_sources[0x33]	1313	1			T3	1		T46	1		T9	6
valid_sources[0x34]	782	1			T2	1		T3	2		T9	3
valid_sources[0x35]	805	1			T1	3		T6	1		T46	1
valid_sources[0x36]	803	1			T3	3		T6	2		T42	1
valid_sources[0x37]	1176	1			T3	6		T6	2		T46	1
valid_sources[0x38]	831	1			T3	4		T9	3		T22	2
valid_sources[0x39]	989	1			T2	2		T14	29		T3	1
valid_sources[0x3a]	1180	1			T3	2		T46	1		T43	2
valid_sources[0x3b]	935	1			T1	2		T2	1		T3	2
valid_sources[0x3c]	1103	1			T1	1		T14	9		T3	3
valid_sources[0x3d]	1345	1			T1	21		T3	3		T46	2
valid_sources[0x3e]	1252	1			T1	4		T14	6		T3	1
valid_sources[0x3f]	889	1			T1	4		T3	1		T9	1
valid_sources[0x40]	1020	1			T1	7		T5	3		T3	2
valid_sources[0x41]	1016	1			T1	4		T3	1		T9	5
valid_sources[0x42]	1040	1			T14	25		T6	2		T46	1
valid_sources[0x43]	843	1			T1	2		T3	5		T9	2
valid_sources[0x44]	1142	1			T14	28		T3	1		T9	4
valid_sources[0x45]	741	1			T1	1		T3	3		T9	4
valid_sources[0x46]	1448	1			T2	1		T6	1		T46	1
valid_sources[0x47]	883	1			T14	5		T3	1		T42	1
valid_sources[0x48]	840	1			T14	6		T3	1		T46	1
valid_sources[0x49]	755	1			T1	10		T3	1		T6	1
valid_sources[0x4a]	2533	1			T1	5		T16	4		T6	1
valid_sources[0x4b]	982	1			T1	5		T3	1		T46	1
valid_sources[0x4c]	1364	1			T1	5		T5	4		T2	3
valid_sources[0x4d]	825	1			T1	1		T3	6		T43	3
valid_sources[0x4e]	956	1			T1	5		T5	1		T14	6
valid_sources[0x4f]	937	1			T14	3		T3	1		T9	3
valid_sources[0x50]	870	1			T1	17		T3	4		T6	1
valid_sources[0x51]	962	1			T9	7		T44	2		T62	2
valid_sources[0x52]	964	1			T3	1		T48	2		T9	3
valid_sources[0x53]	1069	1			T1	5		T14	11		T9	7
valid_sources[0x54]	818	1			T3	1		T6	2		T46	1
valid_sources[0x55]	956	1			T1	8		T4	2		T2	1
valid_sources[0x56]	912	1			T3	2		T6	1		T9	4
valid_sources[0x57]	1159	1			T1	11		T3	1		T46	1
valid_sources[0x58]	938	1			T1	24		T3	2		T46	1
valid_sources[0x59]	914	1			T1	12		T14	27		T16	1
valid_sources[0x5a]	853	1			T14	6		T3	5		T46	1
valid_sources[0x5b]	877	1			T1	19		T5	1		T3	5
valid_sources[0x5c]	775	1			T3	4		T9	4		T62	2
valid_sources[0x5d]	871	1			T1	3		T9	4		T22	3
valid_sources[0x5e]	945	1			T1	2		T3	4		T6	1
valid_sources[0x5f]	1529	1			T14	25		T3	1		T46	2
valid_sources[0x60]	956	1			T14	6		T46	1		T9	5
valid_sources[0x61]	851	1			T3	5		T9	5		T22	4
valid_sources[0x62]	1124	1			T2	1		T3	6		T6	1
valid_sources[0x63]	795	1			T46	1		T9	13		T62	1
valid_sources[0x64]	840	1			T4	1		T14	1		T3	1
valid_sources[0x65]	2981	1			T5	2		T3	2		T6	1
valid_sources[0x66]	1951	1			T1	6		T3	1		T6	1
valid_sources[0x67]	946	1			T5	1		T3	2		T46	1
valid_sources[0x68]	1537	1			T1	5		T4	1		T14	3
valid_sources[0x69]	906	1			T2	1		T14	2		T3	3
valid_sources[0x6a]	889	1			T3	4		T43	1		T9	4
valid_sources[0x6b]	1712	1			T16	1		T3	2		T6	1
valid_sources[0x6c]	921	1			T1	4		T3	2		T46	1
valid_sources[0x6d]	933	1			T1	9		T5	3		T14	2
valid_sources[0x6e]	944	1			T3	7		T6	1		T9	5
valid_sources[0x6f]	802	1			T3	1		T9	10		T22	2
valid_sources[0x70]	1139	1			T1	18		T2	1		T3	3
valid_sources[0x71]	861	1			T3	1		T9	3		T22	9
valid_sources[0x72]	855	1			T1	4		T3	1		T46	1
valid_sources[0x73]	776	1			T1	13		T14	2		T3	5
valid_sources[0x74]	1453	1			T1	7		T6	1		T9	3
valid_sources[0x75]	1127	1			T9	4		T50	2		T62	1
valid_sources[0x76]	1115	1			T1	4		T2	1		T3	2
valid_sources[0x77]	1600	1			T5	6		T2	2		T14	5
valid_sources[0x78]	986	1			T1	1		T14	8		T3	1
valid_sources[0x79]	1331	1			T1	11		T43	1		T9	4
valid_sources[0x7a]	766	1			T1	12		T14	1		T6	1
valid_sources[0x7b]	918	1			T1	6		T3	2		T9	3
valid_sources[0x7c]	760	1			T14	32		T3	3		T6	2
valid_sources[0x7d]	970	1			T3	1		T9	2		T22	2
valid_sources[0x7e]	857	1			T3	1		T9	1		T50	5
valid_sources[0x7f]	2047	1			T3	5		T6	1		T21	1
valid_sources[0x80]	937	1			T1	20		T14	43		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64287

1

T1

299

T4

2

T5

17

values[0x0]

all_enables

biggest_size

32777

1

T1

84

T5

6

T2

4

values[0x1]

all_enables

biggest_size

23672

1

T1

46

T5

5

T2

3