Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
90 |
90 |
100.00 |
Total Bits 0->1 |
45 |
45 |
100.00 |
Total Bits 1->0 |
45 |
45 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
90 |
90 |
100.00 |
Port Bits 0->1 |
45 |
45 |
100.00 |
Port Bits 1->0 |
45 |
45 |
100.00 |
Port Details
| | | | | | |
clk_i |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T5,T2 |
Yes |
T1,T4,T5 |
INPUT |
oh_i[0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[15:1] |
Yes |
Yes |
*T1,*T5,*T2 |
Yes |
T1,T5,T2 |
INPUT |
oh_i[16] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[42:17] |
Yes |
Yes |
T1,T2,T6 |
Yes |
T1,T2,T6 |
INPUT |
addr_i[5:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
INPUT |
err_o |
Yes |
Yes |
T48,T279,T280 |
Yes |
T48,T279,T280 |
OUTPUT |
*Tests covering at least one bit in the range