Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T6,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T21,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T21
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T6,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T42
0	1	Covered	T20,T101,T105
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T42
0	1	Covered	T6,T21,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T21,T42
1	-	Covered	T6,T21,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T21
DetectSt	168	Covered	T6,T21,T42
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T21,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T21,T42
DebounceSt->IdleSt	163	Covered	T1,T9,T45
DetectSt->IdleSt	186	Covered	T20,T101,T105
DetectSt->StableSt	191	Covered	T6,T21,T42
IdleSt->DebounceSt	148	Covered	T1,T6,T21
StableSt->IdleSt	206	Covered	T6,T21,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T21
0	1	Covered	T1,T6,T21
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T21,T42
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T21,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T9,T45
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T21
DetectSt	-	-	-	-	1	-	-	Covered	T20,T101,T105
DetectSt	-	-	-	-	0	1	-	Covered	T6,T21,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T21,T42
StableSt	-	-	-	-	-	-	0	Covered	T6,T21,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	292	0	0
CntIncr_A	7084667	230960	0	0
CntNoWrap_A	7084667	6442723	0	0
DetectStDropOut_A	7084667	3	0	0
DetectedOut_A	7084667	964	0	0
DetectedPulseOut_A	7084667	133	0	0
DisabledIdleSt_A	7084667	6205085	0	0
DisabledNoDetection_A	7084667	6207344	0	0
EnterDebounceSt_A	7084667	159	0	0
EnterDetectSt_A	7084667	136	0	0
EnterStableSt_A	7084667	133	0	0
PulseIsPulse_A	7084667	133	0	0
StayInStableSt	7084667	831	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7084667	6691	0	0
gen_low_level_sva.LowLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	133	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	292	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	6	0	0
T9	0	7	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	6	0	0
T21	0	2	0	0
T37	0	4	0	0
T42	0	6	0	0
T43	0	2	0	0
T45	0	3	0	0
T84	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	230960	0	0
T1	17521	14	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	116	0	0
T9	0	133	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	95	0	0
T21	0	97	0	0
T37	0	171	0	0
T42	0	58805	0	0
T43	0	97	0	0
T45	0	96	0	0
T84	0	135	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442723	0	0
T1	17521	10951	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	936	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	3	0	0
T20	17784	1	0	0
T33	12084	0	0	0
T37	9588	0	0	0
T39	519	0	0	0
T52	988	0	0	0
T56	4311	0	0	0
T59	502	0	0	0
T101	0	1	0	0
T105	0	1	0	0
T106	502	0	0	0
T107	511	0	0	0
T108	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	964	0	0
T6	2946	33	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	17	0	0
T20	0	6	0	0
T21	744	10	0	0
T37	0	21	0	0
T42	59353	28	0	0
T43	0	11	0	0
T45	0	5	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T53	0	2	0	0
T54	404	0	0	0
T84	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	133	0	0
T6	2946	3	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	3	0	0
T20	0	2	0	0
T21	744	1	0	0
T37	0	2	0	0
T42	59353	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T53	0	1	0	0
T54	404	0	0	0
T84	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6205085	0	0
T1	17521	10911	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	669	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6207344	0	0
T1	17521	10933	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	672	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	159	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	3	0	0
T9	0	4	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	3	0	0
T21	0	1	0	0
T37	0	2	0	0
T42	0	3	0	0
T43	0	1	0	0
T45	0	2	0	0
T84	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	136	0	0
T6	2946	3	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	3	0	0
T20	0	3	0	0
T21	744	1	0	0
T37	0	2	0	0
T42	59353	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T53	0	1	0	0
T54	404	0	0	0
T84	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	133	0	0
T6	2946	3	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	3	0	0
T20	0	2	0	0
T21	744	1	0	0
T37	0	2	0	0
T42	59353	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T53	0	1	0	0
T54	404	0	0	0
T84	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	133	0	0
T6	2946	3	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	3	0	0
T20	0	2	0	0
T21	744	1	0	0
T37	0	2	0	0
T42	59353	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T53	0	1	0	0
T54	404	0	0	0
T84	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	831	0	0
T6	2946	30	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	14	0	0
T20	0	4	0	0
T21	744	9	0	0
T37	0	19	0	0
T42	59353	25	0	0
T43	0	10	0	0
T45	0	4	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T53	0	1	0	0
T54	404	0	0	0
T84	0	4	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6691	0	0
T1	17521	36	0	0
T2	2509	2	0	0
T3	13827	13	0	0
T4	402	0	0	0
T5	2088	14	0	0
T6	2946	7	0	0
T13	505	3	0	0
T14	8931	27	0	0
T15	407	0	0	0
T16	421	2	0	0
T46	0	5	0	0
T47	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	133	0	0
T6	2946	3	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	3	0	0
T20	0	2	0	0
T21	744	1	0	0
T37	0	2	0	0
T42	59353	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T53	0	1	0	0
T54	404	0	0	0
T84	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T9,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T9,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T9,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T20
1	0	Covered	T1,T5,T2
1	1	Covered	T8,T9,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T20,T52
0	1	Covered	T9,T72,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T20,T52
0	1	Unreachable
1	0	Covered	T8,T20,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T20
DetectSt	168	Covered	T8,T9,T20
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T20,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T20
DebounceSt->IdleSt	163	Covered	T20,T69,T70
DetectSt->IdleSt	186	Covered	T9,T72,T82
DetectSt->StableSt	191	Covered	T8,T20,T52
IdleSt->DebounceSt	148	Covered	T8,T9,T20
StableSt->IdleSt	206	Covered	T8,T20,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T20
0	1	Covered	T8,T9,T20
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T20
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T69,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T20
DetectSt	-	-	-	-	1	-	-	Covered	T9,T72,T82
DetectSt	-	-	-	-	0	1	-	Covered	T8,T20,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T20,T52
StableSt	-	-	-	-	-	-	0	Covered	T8,T20,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	211	0	0
CntIncr_A	7084667	178891	0	0
CntNoWrap_A	7084667	6442804	0	0
DetectStDropOut_A	7084667	26	0	0
DetectedOut_A	7084667	421037	0	0
DetectedPulseOut_A	7084667	45	0	0
DisabledIdleSt_A	7084667	4560962	0	0
DisabledNoDetection_A	7084667	4563277	0	0
EnterDebounceSt_A	7084667	142	0	0
EnterDetectSt_A	7084667	71	0	0
EnterStableSt_A	7084667	45	0	0
PulseIsPulse_A	7084667	45	0	0
StayInStableSt	7084667	420992	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7084667	6691	0	0
gen_low_level_sva.LowLevelEvent_A	7084667	6445335	0	0
gen_sticky_sva.StableStDropOut_A	7084667	478508	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	211	0	0
T8	1125	2	0	0
T9	64549	2	0	0
T20	0	4	0	0
T22	10052	0	0	0
T31	0	2	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	4	0	0
T70	0	3	0	0
T71	0	2	0	0
T72	0	17	0	0
T73	405	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	178891	0	0
T8	1125	76	0	0
T9	64549	37714	0	0
T20	0	140	0	0
T22	10052	0	0	0
T31	0	43	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	22	0	0
T53	0	41	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	72	0	0
T70	0	102	0	0
T71	0	178	0	0
T72	0	603	0	0
T73	405	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442804	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	26	0	0
T9	64549	1	0	0
T22	10052	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T72	0	7	0	0
T73	405	0	0	0
T82	0	2	0	0
T117	0	2	0	0
T118	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	2	0	0
T123	0	3	0	0
T124	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	421037	0	0
T8	1125	70	0	0
T9	64549	0	0	0
T20	0	122	0	0
T22	10052	0	0	0
T31	0	23	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	1	0	0
T53	0	15	0	0
T62	524	0	0	0
T63	522	0	0	0
T72	0	1	0	0
T73	405	0	0	0
T83	0	119	0	0
T113	0	725	0	0
T114	0	457	0	0
T115	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	45	0	0
T8	1125	1	0	0
T9	64549	0	0	0
T20	0	1	0	0
T22	10052	0	0	0
T31	0	1	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T62	524	0	0	0
T63	522	0	0	0
T72	0	1	0	0
T73	405	0	0	0
T83	0	1	0	0
T113	0	2	0	0
T114	0	2	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	4560962	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	4563277	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	142	0	0
T8	1125	1	0	0
T9	64549	1	0	0
T20	0	3	0	0
T22	10052	0	0	0
T31	0	1	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	4	0	0
T70	0	3	0	0
T71	0	2	0	0
T72	0	9	0	0
T73	405	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	71	0	0
T8	1125	1	0	0
T9	64549	1	0	0
T20	0	1	0	0
T22	10052	0	0	0
T31	0	1	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T62	524	0	0	0
T63	522	0	0	0
T72	0	8	0	0
T73	405	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T113	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	45	0	0
T8	1125	1	0	0
T9	64549	0	0	0
T20	0	1	0	0
T22	10052	0	0	0
T31	0	1	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T62	524	0	0	0
T63	522	0	0	0
T72	0	1	0	0
T73	405	0	0	0
T83	0	1	0	0
T113	0	2	0	0
T114	0	2	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	45	0	0
T8	1125	1	0	0
T9	64549	0	0	0
T20	0	1	0	0
T22	10052	0	0	0
T31	0	1	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T62	524	0	0	0
T63	522	0	0	0
T72	0	1	0	0
T73	405	0	0	0
T83	0	1	0	0
T113	0	2	0	0
T114	0	2	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	420992	0	0
T8	1125	69	0	0
T9	64549	0	0	0
T20	0	121	0	0
T22	10052	0	0	0
T31	0	22	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T53	0	14	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T81	0	101	0	0
T83	0	118	0	0
T113	0	723	0	0
T114	0	455	0	0
T115	0	61	0	0
T125	0	372	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6691	0	0
T1	17521	36	0	0
T2	2509	2	0	0
T3	13827	13	0	0
T4	402	0	0	0
T5	2088	14	0	0
T6	2946	7	0	0
T13	505	3	0	0
T14	8931	27	0	0
T15	407	0	0	0
T16	421	2	0	0
T46	0	5	0	0
T47	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	478508	0	0
T8	1125	80	0	0
T9	64549	0	0	0
T20	0	325	0	0
T22	10052	0	0	0
T31	0	27	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	68	0	0
T53	0	27	0	0
T62	524	0	0	0
T63	522	0	0	0
T72	0	29512	0	0
T73	405	0	0	0
T83	0	586	0	0
T113	0	196	0	0
T114	0	116	0	0
T115	0	40	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T9,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T9,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T9,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T20
1	0	Covered	T1,T5,T2
1	1	Covered	T8,T9,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T20
0	1	Covered	T20,T52,T70
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T20
0	1	Unreachable
1	0	Covered	T8,T9,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T20
DetectSt	168	Covered	T8,T9,T20
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T9,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T20
DebounceSt->IdleSt	163	Covered	T20,T53,T70
DetectSt->IdleSt	186	Covered	T20,T52,T70
DetectSt->StableSt	191	Covered	T8,T9,T20
IdleSt->DebounceSt	148	Covered	T8,T9,T20
StableSt->IdleSt	206	Covered	T8,T9,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T20
0	1	Covered	T8,T9,T20
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T20
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T53,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T20
DetectSt	-	-	-	-	1	-	-	Covered	T20,T52,T70
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T20
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	182	0	0
CntIncr_A	7084667	121398	0	0
CntNoWrap_A	7084667	6442833	0	0
DetectStDropOut_A	7084667	12	0	0
DetectedOut_A	7084667	479468	0	0
DetectedPulseOut_A	7084667	53	0	0
DisabledIdleSt_A	7084667	4560962	0	0
DisabledNoDetection_A	7084667	4563277	0	0
EnterDebounceSt_A	7084667	119	0	0
EnterDetectSt_A	7084667	65	0	0
EnterStableSt_A	7084667	53	0	0
PulseIsPulse_A	7084667	53	0	0
StayInStableSt	7084667	479415	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_sticky_sva.StableStDropOut_A	7084667	914051	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	182	0	0
T8	1125	2	0	0
T9	64549	2	0	0
T20	0	5	0	0
T22	10052	0	0	0
T31	0	1	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	2	0	0
T53	0	1	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	4	0	0
T70	0	7	0	0
T71	0	2	0	0
T72	0	6	0	0
T73	405	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	121398	0	0
T8	1125	100	0	0
T9	64549	100	0	0
T20	0	122	0	0
T22	10052	0	0	0
T31	0	14	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	30	0	0
T53	0	28	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	100	0	0
T70	0	100	0	0
T71	0	70	0	0
T72	0	153	0	0
T73	405	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442833	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	12	0	0
T20	17784	1	0	0
T33	12084	0	0	0
T37	9588	0	0	0
T39	519	0	0	0
T52	988	1	0	0
T56	4311	0	0	0
T59	502	0	0	0
T70	0	3	0	0
T106	502	0	0	0
T107	511	0	0	0
T108	404	0	0	0
T122	0	2	0	0
T126	0	1	0	0
T127	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	479468	0	0
T8	1125	98	0	0
T9	64549	57	0	0
T20	0	281	0	0
T22	10052	0	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	201	0	0
T72	0	621	0	0
T73	405	0	0	0
T83	0	506	0	0
T112	0	777	0	0
T113	0	824	0	0
T114	0	292	0	0
T116	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	53	0	0
T8	1125	1	0	0
T9	64549	1	0	0
T20	0	1	0	0
T22	10052	0	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	2	0	0
T72	0	3	0	0
T73	405	0	0	0
T83	0	1	0	0
T112	0	2	0	0
T113	0	2	0	0
T114	0	2	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	4560962	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	4563277	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	119	0	0
T8	1125	1	0	0
T9	64549	1	0	0
T20	0	3	0	0
T22	10052	0	0	0
T31	0	1	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	2	0	0
T70	0	4	0	0
T71	0	2	0	0
T72	0	3	0	0
T73	405	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	65	0	0
T8	1125	1	0	0
T9	64549	1	0	0
T20	0	2	0	0
T22	10052	0	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	1	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	2	0	0
T70	0	3	0	0
T72	0	3	0	0
T73	405	0	0	0
T83	0	1	0	0
T112	0	2	0	0
T113	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	53	0	0
T8	1125	1	0	0
T9	64549	1	0	0
T20	0	1	0	0
T22	10052	0	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	2	0	0
T72	0	3	0	0
T73	405	0	0	0
T83	0	1	0	0
T112	0	2	0	0
T113	0	2	0	0
T114	0	2	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	53	0	0
T8	1125	1	0	0
T9	64549	1	0	0
T20	0	1	0	0
T22	10052	0	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	2	0	0
T72	0	3	0	0
T73	405	0	0	0
T83	0	1	0	0
T112	0	2	0	0
T113	0	2	0	0
T114	0	2	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	479415	0	0
T8	1125	97	0	0
T9	64549	56	0	0
T20	0	280	0	0
T22	10052	0	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	199	0	0
T72	0	618	0	0
T73	405	0	0	0
T83	0	505	0	0
T112	0	775	0	0
T113	0	822	0	0
T114	0	290	0	0
T116	0	34	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	914051	0	0
T8	1125	30	0	0
T9	64549	37667	0	0
T20	0	80	0	0
T22	10052	0	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	113	0	0
T72	0	295017	0	0
T73	405	0	0	0
T83	0	132	0	0
T112	0	404	0	0
T113	0	115	0	0
T114	0	249	0	0
T116	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T20,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T20,T52

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T20,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T20
1	0	Covered	T1,T5,T2
1	1	Covered	T8,T20,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T52,T53
0	1	Covered	T8,T71,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T52,T53
0	1	Unreachable
1	0	Covered	T20,T52,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T20,T52
DetectSt	168	Covered	T8,T20,T52
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T20,T52,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T20,T52
DebounceSt->IdleSt	163	Covered	T31,T71,T83
DetectSt->IdleSt	186	Covered	T8,T71,T81
DetectSt->StableSt	191	Covered	T20,T52,T53
IdleSt->DebounceSt	148	Covered	T8,T20,T52
StableSt->IdleSt	206	Covered	T20,T52,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T20,T52
0	1	Covered	T8,T20,T52
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T20,T52
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T20,T52
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T20,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T71,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T20,T52
DetectSt	-	-	-	-	1	-	-	Covered	T8,T71,T81
DetectSt	-	-	-	-	0	1	-	Covered	T20,T52,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T52,T53
StableSt	-	-	-	-	-	-	0	Covered	T20,T52,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	186	0	0
CntIncr_A	7084667	123335	0	0
CntNoWrap_A	7084667	6442829	0	0
DetectStDropOut_A	7084667	11	0	0
DetectedOut_A	7084667	575311	0	0
DetectedPulseOut_A	7084667	50	0	0
DisabledIdleSt_A	7084667	4560962	0	0
DisabledNoDetection_A	7084667	4563277	0	0
EnterDebounceSt_A	7084667	127	0	0
EnterDetectSt_A	7084667	61	0	0
EnterStableSt_A	7084667	50	0	0
PulseIsPulse_A	7084667	50	0	0
StayInStableSt	7084667	575261	0	0
gen_high_event_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_sticky_sva.StableStDropOut_A	7084667	128745	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	186	0	0
T8	1125	2	0	0
T9	64549	0	0	0
T20	0	4	0	0
T22	10052	0	0	0
T31	0	1	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	4	0	0
T70	0	2	0	0
T71	0	3	0	0
T72	0	6	0	0
T73	405	0	0	0
T82	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	123335	0	0
T8	1125	30	0	0
T9	64549	0	0	0
T20	0	106	0	0
T22	10052	0	0	0
T31	0	44	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	57	0	0
T53	0	29	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	58	0	0
T70	0	48	0	0
T71	0	190	0	0
T72	0	48204	0	0
T73	405	0	0	0
T82	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442829	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	11	0	0
T8	1125	1	0	0
T9	64549	0	0	0
T22	10052	0	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T71	0	1	0	0
T73	405	0	0	0
T81	0	1	0	0
T120	0	1	0	0
T128	0	5	0	0
T129	0	1	0	0
T130	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	575311	0	0
T20	17784	325	0	0
T33	12084	0	0	0
T37	9588	0	0	0
T39	519	0	0	0
T52	988	23	0	0
T53	0	27	0	0
T56	4311	0	0	0
T59	502	0	0	0
T69	0	73	0	0
T70	0	267	0	0
T72	0	247491	0	0
T82	0	35	0	0
T106	502	0	0	0
T107	511	0	0	0
T108	404	0	0	0
T112	0	384	0	0
T113	0	106	0	0
T114	0	279	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	50	0	0
T20	17784	2	0	0
T33	12084	0	0	0
T37	9588	0	0	0
T39	519	0	0	0
T52	988	1	0	0
T53	0	1	0	0
T56	4311	0	0	0
T59	502	0	0	0
T69	0	2	0	0
T70	0	1	0	0
T72	0	3	0	0
T82	0	1	0	0
T106	502	0	0	0
T107	511	0	0	0
T108	404	0	0	0
T112	0	2	0	0
T113	0	2	0	0
T114	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	4560962	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	4563277	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	127	0	0
T8	1125	1	0	0
T9	64549	0	0	0
T20	0	2	0	0
T22	10052	0	0	0
T31	0	1	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	3	0	0
T73	405	0	0	0
T82	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	61	0	0
T8	1125	1	0	0
T9	64549	0	0	0
T20	0	2	0	0
T22	10052	0	0	0
T43	1625	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T62	524	0	0	0
T63	522	0	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	3	0	0
T73	405	0	0	0
T82	0	1	0	0
T112	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	50	0	0
T20	17784	2	0	0
T33	12084	0	0	0
T37	9588	0	0	0
T39	519	0	0	0
T52	988	1	0	0
T53	0	1	0	0
T56	4311	0	0	0
T59	502	0	0	0
T69	0	2	0	0
T70	0	1	0	0
T72	0	3	0	0
T82	0	1	0	0
T106	502	0	0	0
T107	511	0	0	0
T108	404	0	0	0
T112	0	2	0	0
T113	0	2	0	0
T114	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	50	0	0
T20	17784	2	0	0
T33	12084	0	0	0
T37	9588	0	0	0
T39	519	0	0	0
T52	988	1	0	0
T53	0	1	0	0
T56	4311	0	0	0
T59	502	0	0	0
T69	0	2	0	0
T70	0	1	0	0
T72	0	3	0	0
T82	0	1	0	0
T106	502	0	0	0
T107	511	0	0	0
T108	404	0	0	0
T112	0	2	0	0
T113	0	2	0	0
T114	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	575261	0	0
T20	17784	323	0	0
T33	12084	0	0	0
T37	9588	0	0	0
T39	519	0	0	0
T52	988	22	0	0
T53	0	26	0	0
T56	4311	0	0	0
T59	502	0	0	0
T69	0	71	0	0
T70	0	266	0	0
T72	0	247488	0	0
T82	0	34	0	0
T106	502	0	0	0
T107	511	0	0	0
T108	404	0	0	0
T112	0	382	0	0
T113	0	104	0	0
T114	0	277	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	128745	0	0
T20	17784	398	0	0
T33	12084	0	0	0
T37	9588	0	0	0
T39	519	0	0	0
T52	988	27	0	0
T53	0	41	0	0
T56	4311	0	0	0
T59	502	0	0	0
T69	0	295	0	0
T70	0	183	0	0
T72	0	130	0	0
T82	0	15409	0	0
T106	502	0	0	0
T107	511	0	0	0
T108	404	0	0	0
T112	0	861	0	0
T113	0	1002	0	0
T114	0	320	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T35,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T40,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T35,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T39
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T40,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T35,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T35,T41
0	1	Covered	T40,T41,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T35,T41
1	-	Covered	T40,T41,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T40,T35
DetectSt	168	Covered	T40,T35,T41
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T40,T35,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T35,T41
DebounceSt->IdleSt	163	Covered	T1,T74,T75
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T35,T41
IdleSt->DebounceSt	148	Covered	T1,T40,T35
StableSt->IdleSt	206	Covered	T40,T41,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T35,T41
0	1	Covered	T1,T40,T35
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T35,T41
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T40,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T35,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T40,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T35,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T41,T36
StableSt	-	-	-	-	-	-	0	Covered	T40,T35,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	84	0	0
CntIncr_A	7084667	23049	0	0
CntNoWrap_A	7084667	6442931	0	0
DetectStDropOut_A	7084667	0	0	0
DetectedOut_A	7084667	19605	0	0
DetectedPulseOut_A	7084667	41	0	0
DisabledIdleSt_A	7084667	6341450	0	0
DisabledNoDetection_A	7084667	6343717	0	0
EnterDebounceSt_A	7084667	44	0	0
EnterDetectSt_A	7084667	41	0	0
EnterStableSt_A	7084667	41	0	0
PulseIsPulse_A	7084667	41	0	0
StayInStableSt	7084667	19543	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	84	0	0
T35	0	2	0	0
T36	0	2	0	0
T40	7580	4	0	0
T41	0	4	0	0
T85	402	0	0	0
T86	14944	0	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T90	8888	0	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T137	523	0	0	0
T138	1375	0	0	0
T139	708	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	23049	0	0
T1	17521	36	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T35	0	66	0	0
T36	0	22	0	0
T40	0	4238	0	0
T41	0	50	0	0
T131	0	11	0	0
T132	0	88	0	0
T133	0	60	0	0
T134	0	39	0	0
T135	0	95	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442931	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	19605	0	0
T35	0	39	0	0
T36	0	59	0	0
T40	7580	82	0	0
T41	0	92	0	0
T85	402	0	0	0
T86	14944	0	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T90	8888	0	0	0
T131	0	56	0	0
T132	0	137	0	0
T133	0	37	0	0
T134	0	41	0	0
T135	0	44	0	0
T136	0	38	0	0
T137	523	0	0	0
T138	1375	0	0	0
T139	708	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	41	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	7580	2	0	0
T41	0	2	0	0
T85	402	0	0	0
T86	14944	0	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T90	8888	0	0	0
T131	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	523	0	0	0
T138	1375	0	0	0
T139	708	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6341450	0	0
T1	17521	10732	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6343717	0	0
T1	17521	10753	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	44	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T131	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	41	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	7580	2	0	0
T41	0	2	0	0
T85	402	0	0	0
T86	14944	0	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T90	8888	0	0	0
T131	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	523	0	0	0
T138	1375	0	0	0
T139	708	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	41	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	7580	2	0	0
T41	0	2	0	0
T85	402	0	0	0
T86	14944	0	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T90	8888	0	0	0
T131	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	523	0	0	0
T138	1375	0	0	0
T139	708	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	41	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	7580	2	0	0
T41	0	2	0	0
T85	402	0	0	0
T86	14944	0	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T90	8888	0	0	0
T131	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	523	0	0	0
T138	1375	0	0	0
T139	708	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	19543	0	0
T35	0	37	0	0
T36	0	58	0	0
T40	7580	79	0	0
T41	0	89	0	0
T85	402	0	0	0
T86	14944	0	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T90	8888	0	0	0
T131	0	55	0	0
T132	0	134	0	0
T133	0	35	0	0
T134	0	39	0	0
T135	0	42	0	0
T136	0	36	0	0
T137	523	0	0	0
T138	1375	0	0	0
T139	708	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	20	0	0
T36	0	1	0	0
T40	7580	1	0	0
T41	0	1	0	0
T85	402	0	0	0
T86	14944	0	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T90	8888	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T137	523	0	0	0
T138	1375	0	0	0
T139	708	0	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T12
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T31
0	1	Covered	T1,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T31
0	1	Covered	T9,T31,T131
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T31
1	-	Covered	T9,T31,T131

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T12
DetectSt	168	Covered	T1,T9,T12
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T12,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T12
DebounceSt->IdleSt	163	Covered	T40,T77,T134
DetectSt->IdleSt	186	Covered	T1,T77
DetectSt->StableSt	191	Covered	T9,T12,T31
IdleSt->DebounceSt	148	Covered	T1,T9,T12
StableSt->IdleSt	206	Covered	T9,T31,T131

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T12
0	1	Covered	T1,T9,T12
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T12
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T77,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T1,T77
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T31,T131
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	111	0	0
CntIncr_A	7084667	9397	0	0
CntNoWrap_A	7084667	6442904	0	0
DetectStDropOut_A	7084667	2	0	0
DetectedOut_A	7084667	3988	0	0
DetectedPulseOut_A	7084667	50	0	0
DisabledIdleSt_A	7084667	6414361	0	0
DisabledNoDetection_A	7084667	6416640	0	0
EnterDebounceSt_A	7084667	59	0	0
EnterDetectSt_A	7084667	52	0	0
EnterStableSt_A	7084667	50	0	0
PulseIsPulse_A	7084667	50	0	0
StayInStableSt	7084667	3915	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7084667	2593	0	0
gen_low_level_sva.LowLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	111	0	0
T1	17521	2	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	4	0	0
T12	0	2	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	4	0	0
T40	0	2	0	0
T77	0	5	0	0
T115	0	4	0	0
T131	0	4	0	0
T132	0	4	0	0
T145	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	9397	0	0
T1	17521	60	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	162	0	0
T12	0	54	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	84	0	0
T40	0	4238	0	0
T77	0	42	0	0
T115	0	60	0	0
T131	0	22	0	0
T132	0	88	0	0
T145	0	41	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442904	0	0
T1	17521	10950	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	2	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T77	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	3988	0	0
T9	64549	444	0	0
T12	0	45	0	0
T22	10052	0	0	0
T31	0	145	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	51	0	0
T115	0	104	0	0
T124	424	0	0	0
T131	0	103	0	0
T132	0	49	0	0
T135	0	37	0	0
T145	0	40	0	0
T146	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	50	0	0
T9	64549	2	0	0
T12	0	1	0	0
T22	10052	0	0	0
T31	0	2	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	1	0	0
T115	0	2	0	0
T124	424	0	0	0
T131	0	2	0	0
T132	0	2	0	0
T135	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6414361	0	0
T1	17521	10850	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6416640	0	0
T1	17521	10872	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	59	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	2	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T40	0	2	0	0
T77	0	3	0	0
T115	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0
T145	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	52	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	2	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T77	0	2	0	0
T115	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	50	0	0
T9	64549	2	0	0
T12	0	1	0	0
T22	10052	0	0	0
T31	0	2	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	1	0	0
T115	0	2	0	0
T124	424	0	0	0
T131	0	2	0	0
T132	0	2	0	0
T135	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	50	0	0
T9	64549	2	0	0
T12	0	1	0	0
T22	10052	0	0	0
T31	0	2	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	1	0	0
T115	0	2	0	0
T124	424	0	0	0
T131	0	2	0	0
T132	0	2	0	0
T135	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	3915	0	0
T9	64549	441	0	0
T12	0	43	0	0
T22	10052	0	0	0
T31	0	143	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	49	0	0
T115	0	101	0	0
T124	424	0	0	0
T131	0	100	0	0
T132	0	47	0	0
T135	0	35	0	0
T145	0	39	0	0
T146	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	2593	0	0
T1	17521	27	0	0
T2	2509	1	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	6	0	0
T6	2946	6	0	0
T7	0	5	0	0
T9	0	41	0	0
T13	505	7	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T46	0	7	0	0
T47	0	5	0	0
T49	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	27	0	0
T9	64549	1	0	0
T22	10052	0	0	0
T31	0	2	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T115	0	1	0	0
T124	424	0	0	0
T131	0	1	0	0
T132	0	2	0	0
T136	0	1	0	0
T140	0	2	0	0
T142	0	1	0	0
T145	0	1	0	0
T147	0	1	0	0