Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T39,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T9,T39,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T38,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T39,T53
1	0	Covered	T1,T5,T2
1	1	Covered	T9,T39,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T38,T31
0	1	Covered	T31,T77,T143
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T38,T31
0	1	Covered	T9,T31,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T38,T31
1	-	Covered	T9,T31,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T39,T38
DetectSt	168	Covered	T9,T38,T31
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T38,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T38,T31
DebounceSt->IdleSt	163	Covered	T39,T77,T74
DetectSt->IdleSt	186	Covered	T31,T77,T143
DetectSt->StableSt	191	Covered	T9,T38,T31
IdleSt->DebounceSt	148	Covered	T9,T39,T38
StableSt->IdleSt	206	Covered	T9,T31,T86

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T39,T38
0	1	Covered	T9,T39,T38
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T38,T31
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T39,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T38,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T77,T142
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T39,T38
DetectSt	-	-	-	-	1	-	-	Covered	T31,T77,T143
DetectSt	-	-	-	-	0	1	-	Covered	T9,T38,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T31,T35
StableSt	-	-	-	-	-	-	0	Covered	T9,T38,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	130	0	0
CntIncr_A	7084667	38850	0	0
CntNoWrap_A	7084667	6442885	0	0
DetectStDropOut_A	7084667	5	0	0
DetectedOut_A	7084667	32627	0	0
DetectedPulseOut_A	7084667	56	0	0
DisabledIdleSt_A	7084667	6345838	0	0
DisabledNoDetection_A	7084667	6348109	0	0
EnterDebounceSt_A	7084667	71	0	0
EnterDetectSt_A	7084667	61	0	0
EnterStableSt_A	7084667	56	0	0
PulseIsPulse_A	7084667	56	0	0
StayInStableSt	7084667	32549	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	130	0	0
T9	64549	4	0	0
T22	10052	0	0	0
T31	0	6	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	5	0	0
T86	0	2	0	0
T124	424	0	0	0
T195	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	38850	0	0
T9	64549	38	0	0
T22	10052	0	0	0
T31	0	126	0	0
T35	0	66	0	0
T36	0	22	0	0
T38	0	74	0	0
T39	0	33	0	0
T41	0	25	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	42	0	0
T86	0	96	0	0
T124	424	0	0	0
T195	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442885	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	5	0	0
T31	35439	1	0	0
T40	7580	0	0	0
T77	0	1	0	0
T85	402	0	0	0
T86	14944	0	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T109	443	0	0	0
T110	438	0	0	0
T111	527	0	0	0
T143	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	32627	0	0
T9	64549	85	0	0
T22	10052	0	0	0
T31	0	50	0	0
T35	0	14	0	0
T36	0	10	0	0
T38	0	43	0	0
T41	0	3	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	76	0	0
T86	0	40	0	0
T124	424	0	0	0
T176	0	40	0	0
T195	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	56	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T31	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	1	0	0
T86	0	1	0	0
T124	424	0	0	0
T176	0	1	0	0
T195	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6345838	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6348109	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	71	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T31	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	3	0	0
T86	0	1	0	0
T124	424	0	0	0
T195	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	61	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T31	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	2	0	0
T86	0	1	0	0
T124	424	0	0	0
T176	0	1	0	0
T195	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	56	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T31	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	1	0	0
T86	0	1	0	0
T124	424	0	0	0
T176	0	1	0	0
T195	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	56	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T31	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	1	0	0
T86	0	1	0	0
T124	424	0	0	0
T176	0	1	0	0
T195	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	32549	0	0
T9	64549	82	0	0
T22	10052	0	0	0
T31	0	48	0	0
T35	0	13	0	0
T36	0	9	0	0
T38	0	41	0	0
T41	0	2	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	74	0	0
T86	0	38	0	0
T124	424	0	0	0
T176	0	39	0	0
T195	0	45	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	34	0	0
T9	64549	1	0	0
T22	10052	0	0	0
T31	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T41	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T161	0	1	0	0
T176	0	1	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T37,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T12,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T37,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T12,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T35
0	1	Covered	T77,T140,T171
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T37,T35
1	-	Covered	T77,T140,T171

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T37
DetectSt	168	Covered	T12,T37,T35
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T12,T37,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T37,T35
DebounceSt->IdleSt	163	Covered	T1,T74,T142
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T37,T35
IdleSt->DebounceSt	148	Covered	T1,T12,T37
StableSt->IdleSt	206	Covered	T37,T77,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T37,T35
0	1	Covered	T1,T12,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T37,T35
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T37,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T142,T199,T200
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T37,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T77,T140,T171
StableSt	-	-	-	-	-	-	0	Covered	T12,T37,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	81	0	0
CntIncr_A	7084667	18758	0	0
CntNoWrap_A	7084667	6442934	0	0
DetectStDropOut_A	7084667	0	0	0
DetectedOut_A	7084667	2879	0	0
DetectedPulseOut_A	7084667	38	0	0
DisabledIdleSt_A	7084667	6346942	0	0
DisabledNoDetection_A	7084667	6349205	0	0
EnterDebounceSt_A	7084667	44	0	0
EnterDetectSt_A	7084667	38	0	0
EnterStableSt_A	7084667	38	0	0
PulseIsPulse_A	7084667	38	0	0
StayInStableSt	7084667	2821	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7084667	6159	0	0
gen_low_level_sva.LowLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	81	0	0
T12	511	2	0	0
T20	17784	0	0	0
T23	8414	0	0	0
T29	33527	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T39	519	0	0	0
T41	0	2	0	0
T45	739	0	0	0
T58	495	0	0	0
T77	0	4	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	2	0	0
T149	504	0	0	0
T150	441	0	0	0
T151	502	0	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	18758	0	0
T1	17521	36	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T12	0	54	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T35	0	66	0	0
T36	0	22	0	0
T37	0	27	0	0
T41	0	25	0	0
T77	0	28	0	0
T131	0	11	0	0
T132	0	44	0	0
T176	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442934	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	2879	0	0
T12	511	46	0	0
T20	17784	0	0	0
T23	8414	0	0	0
T29	33527	0	0	0
T35	0	39	0	0
T36	0	127	0	0
T37	0	38	0	0
T39	519	0	0	0
T41	0	167	0	0
T45	739	0	0	0
T58	495	0	0	0
T77	0	82	0	0
T131	0	183	0	0
T132	0	235	0	0
T133	0	37	0	0
T149	504	0	0	0
T150	441	0	0	0
T151	502	0	0	0
T176	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	38	0	0
T12	511	1	0	0
T20	17784	0	0	0
T23	8414	0	0	0
T29	33527	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	519	0	0	0
T41	0	1	0	0
T45	739	0	0	0
T58	495	0	0	0
T77	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T149	504	0	0	0
T150	441	0	0	0
T151	502	0	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6346942	0	0
T1	17521	10732	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6349205	0	0
T1	17521	10753	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	44	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T77	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	38	0	0
T12	511	1	0	0
T20	17784	0	0	0
T23	8414	0	0	0
T29	33527	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	519	0	0	0
T41	0	1	0	0
T45	739	0	0	0
T58	495	0	0	0
T77	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T149	504	0	0	0
T150	441	0	0	0
T151	502	0	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	38	0	0
T12	511	1	0	0
T20	17784	0	0	0
T23	8414	0	0	0
T29	33527	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	519	0	0	0
T41	0	1	0	0
T45	739	0	0	0
T58	495	0	0	0
T77	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T149	504	0	0	0
T150	441	0	0	0
T151	502	0	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	38	0	0
T12	511	1	0	0
T20	17784	0	0	0
T23	8414	0	0	0
T29	33527	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	519	0	0	0
T41	0	1	0	0
T45	739	0	0	0
T58	495	0	0	0
T77	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T149	504	0	0	0
T150	441	0	0	0
T151	502	0	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	2821	0	0
T12	511	44	0	0
T20	17784	0	0	0
T23	8414	0	0	0
T29	33527	0	0	0
T35	0	37	0	0
T36	0	125	0	0
T37	0	36	0	0
T39	519	0	0	0
T41	0	165	0	0
T45	739	0	0	0
T58	495	0	0	0
T77	0	80	0	0
T131	0	181	0	0
T132	0	233	0	0
T133	0	35	0	0
T149	504	0	0	0
T150	441	0	0	0
T151	502	0	0	0
T176	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6159	0	0
T1	17521	30	0	0
T2	2509	1	0	0
T3	13827	13	0	0
T4	402	0	0	0
T5	2088	7	0	0
T6	2946	7	0	0
T13	505	5	0	0
T14	8931	26	0	0
T15	407	0	0	0
T16	421	2	0	0
T46	0	4	0	0
T47	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	18	0	0
T41	2781	0	0	0
T77	2884	2	0	0
T82	16728	0	0	0
T140	0	1	0	0
T147	0	2	0	0
T153	0	1	0	0
T171	0	1	0	0
T192	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	694	0	0	0
T206	759	0	0	0
T207	19691	0	0	0
T208	11304	0	0	0
T209	449	0	0	0
T210	10694	0	0	0
T211	507	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T212,T213
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T9,T31,T77
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T6
1	-	Covered	T9,T31,T77

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T6
DetectSt	168	Covered	T1,T2,T6
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T6
DebounceSt->IdleSt	163	Covered	T1,T175,T74
DetectSt->IdleSt	186	Covered	T212,T213
DetectSt->StableSt	191	Covered	T1,T2,T6
IdleSt->DebounceSt	148	Covered	T1,T2,T6
StableSt->IdleSt	206	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T173,T214
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T212,T213
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T31,T77
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	126	0	0
CntIncr_A	7084667	68553	0	0
CntNoWrap_A	7084667	6442889	0	0
DetectStDropOut_A	7084667	2	0	0
DetectedOut_A	7084667	77438	0	0
DetectedPulseOut_A	7084667	59	0	0
DisabledIdleSt_A	7084667	6159614	0	0
DisabledNoDetection_A	7084667	6161882	0	0
EnterDebounceSt_A	7084667	67	0	0
EnterDetectSt_A	7084667	61	0	0
EnterStableSt_A	7084667	59	0	0
PulseIsPulse_A	7084667	59	0	0
StayInStableSt	7084667	77351	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	126	0	0
T1	17521	2	0	0
T2	2509	2	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	2	0	0
T9	0	4	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T53	0	2	0	0
T195	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	68553	0	0
T1	17521	63	0	0
T2	2509	76	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	83	0	0
T9	0	38	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	84	0	0
T38	0	74	0	0
T39	0	33	0	0
T40	0	2119	0	0
T53	0	59	0	0
T195	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442889	0	0
T1	17521	10950	0	0
T2	2509	503	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	940	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	2	0	0
T126	2465	0	0	0
T212	799	1	0	0
T213	0	1	0	0
T215	16829	0	0	0
T216	5072	0	0	0
T217	1651	0	0	0
T218	19300	0	0	0
T219	876	0	0	0
T220	15505	0	0	0
T221	13481	0	0	0
T222	2293	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	77438	0	0
T1	17521	40	0	0
T2	2509	172	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	39	0	0
T9	0	46	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	87	0	0
T38	0	160	0	0
T39	0	43	0	0
T40	0	2931	0	0
T53	0	42	0	0
T195	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	59	0	0
T1	17521	1	0	0
T2	2509	1	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T9	0	2	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	0	1	0	0
T195	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6159614	0	0
T1	17521	10732	0	0
T2	2509	253	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	476	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6161882	0	0
T1	17521	10753	0	0
T2	2509	256	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	479	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	67	0	0
T1	17521	2	0	0
T2	2509	1	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T9	0	2	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	0	1	0	0
T195	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	61	0	0
T1	17521	1	0	0
T2	2509	1	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T9	0	2	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	0	1	0	0
T195	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	59	0	0
T1	17521	1	0	0
T2	2509	1	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T9	0	2	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	0	1	0	0
T195	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	59	0	0
T1	17521	1	0	0
T2	2509	1	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T9	0	2	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	0	1	0	0
T195	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	77351	0	0
T1	17521	38	0	0
T2	2509	170	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	37	0	0
T9	0	44	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	84	0	0
T38	0	158	0	0
T39	0	41	0	0
T40	0	2929	0	0
T53	0	40	0	0
T195	0	44	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	31	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T31	0	1	0	0
T41	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T77	0	1	0	0
T124	424	0	0	0
T132	0	1	0	0
T135	0	1	0	0
T140	0	2	0	0
T145	0	1	0	0
T161	0	1	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T9,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T56
1	0	Covered	T1,T5,T2
1	1	Covered	T9,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T35,T36
0	1	Covered	T135,T148,T140
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T35,T36
0	1	Covered	T9,T177,T131
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T35,T36
1	-	Covered	T9,T177,T131

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T35,T36
DetectSt	168	Covered	T9,T35,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T35,T36
DebounceSt->IdleSt	163	Covered	T74,T75
DetectSt->IdleSt	186	Covered	T135,T148,T140
DetectSt->StableSt	191	Covered	T9,T35,T36
IdleSt->DebounceSt	148	Covered	T9,T35,T36
StableSt->IdleSt	206	Covered	T9,T36,T177

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T35,T36
0	1	Covered	T9,T35,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T35,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T35,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T135,T148,T140
DetectSt	-	-	-	-	0	1	-	Covered	T9,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T177,T131
StableSt	-	-	-	-	-	-	0	Covered	T9,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	72	0	0
CntIncr_A	7084667	18436	0	0
CntNoWrap_A	7084667	6442943	0	0
DetectStDropOut_A	7084667	3	0	0
DetectedOut_A	7084667	19314	0	0
DetectedPulseOut_A	7084667	32	0	0
DisabledIdleSt_A	7084667	6334854	0	0
DisabledNoDetection_A	7084667	6337127	0	0
EnterDebounceSt_A	7084667	37	0	0
EnterDetectSt_A	7084667	35	0	0
EnterStableSt_A	7084667	32	0	0
PulseIsPulse_A	7084667	32	0	0
StayInStableSt	7084667	19260	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7084667	5996	0	0
gen_low_level_sva.LowLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	72	0	0
T9	64549	4	0	0
T22	10052	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	4	0	0
T135	0	6	0	0
T140	0	4	0	0
T145	0	2	0	0
T148	0	2	0	0
T177	0	2	0	0
T198	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	18436	0	0
T9	64549	38	0	0
T22	10052	0	0	0
T35	0	66	0	0
T36	0	22	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	22	0	0
T135	0	158	0	0
T140	0	186	0	0
T145	0	41	0	0
T148	0	69	0	0
T177	0	40	0	0
T198	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442943	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	3	0	0
T135	11404	1	0	0
T136	2608	0	0	0
T140	0	1	0	0
T148	0	1	0	0
T223	1140	0	0	0
T224	1627	0	0	0
T225	442	0	0	0
T226	504	0	0	0
T227	12039	0	0	0
T228	503	0	0	0
T229	1569	0	0	0
T230	19852	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	19314	0	0
T9	64549	106	0	0
T22	10052	0	0	0
T35	0	39	0	0
T36	0	65	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	63	0	0
T135	0	80	0	0
T140	0	45	0	0
T145	0	41	0	0
T177	0	6	0	0
T198	0	38	0	0
T231	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	32	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	2	0	0
T135	0	2	0	0
T140	0	1	0	0
T145	0	1	0	0
T177	0	1	0	0
T198	0	1	0	0
T231	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6334854	0	0
T1	17521	10850	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6337127	0	0
T1	17521	10872	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	37	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	2	0	0
T135	0	3	0	0
T140	0	2	0	0
T145	0	1	0	0
T148	0	1	0	0
T177	0	1	0	0
T198	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	35	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	2	0	0
T135	0	3	0	0
T140	0	2	0	0
T145	0	1	0	0
T148	0	1	0	0
T177	0	1	0	0
T198	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	32	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	2	0	0
T135	0	2	0	0
T140	0	1	0	0
T145	0	1	0	0
T177	0	1	0	0
T198	0	1	0	0
T231	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	32	0	0
T9	64549	2	0	0
T22	10052	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	2	0	0
T135	0	2	0	0
T140	0	1	0	0
T145	0	1	0	0
T177	0	1	0	0
T198	0	1	0	0
T231	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	19260	0	0
T9	64549	103	0	0
T22	10052	0	0	0
T35	0	37	0	0
T36	0	63	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	60	0	0
T135	0	77	0	0
T140	0	43	0	0
T145	0	39	0	0
T177	0	5	0	0
T198	0	36	0	0
T231	0	100	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	5996	0	0
T1	17521	25	0	0
T2	2509	2	0	0
T3	13827	13	0	0
T4	402	0	0	0
T5	2088	8	0	0
T6	2946	4	0	0
T13	505	6	0	0
T14	8931	31	0	0
T15	407	0	0	0
T16	421	1	0	0
T46	0	4	0	0
T47	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	10	0	0
T9	64549	1	0	0
T22	10052	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T124	424	0	0	0
T131	0	1	0	0
T135	0	1	0	0
T153	0	1	0	0
T177	0	1	0	0
T201	0	1	0	0
T214	0	1	0	0
T232	0	1	0	0
T233	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T10,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T39
0	1	Covered	T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T39
0	1	Covered	T10,T31,T77
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T39
1	-	Covered	T10,T31,T77

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T12
DetectSt	168	Covered	T1,T10,T39
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T10,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T39
DebounceSt->IdleSt	163	Covered	T12,T74,T153
DetectSt->IdleSt	186	Covered	T196
DetectSt->StableSt	191	Covered	T1,T10,T39
IdleSt->DebounceSt	148	Covered	T1,T10,T12
StableSt->IdleSt	206	Covered	T1,T10,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T12
0	1	Covered	T1,T10,T12
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T39
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T153,T214
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T196
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T31,T77
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	115	0	0
CntIncr_A	7084667	36487	0	0
CntNoWrap_A	7084667	6442900	0	0
DetectStDropOut_A	7084667	1	0	0
DetectedOut_A	7084667	16036	0	0
DetectedPulseOut_A	7084667	54	0	0
DisabledIdleSt_A	7084667	6349218	0	0
DisabledNoDetection_A	7084667	6351491	0	0
EnterDebounceSt_A	7084667	60	0	0
EnterDetectSt_A	7084667	55	0	0
EnterStableSt_A	7084667	54	0	0
PulseIsPulse_A	7084667	54	0	0
StayInStableSt	7084667	15960	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	115	0	0
T1	17521	2	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T10	0	2	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	4	0	0
T39	0	2	0	0
T41	0	2	0	0
T77	0	4	0	0
T86	0	2	0	0
T176	0	2	0	0
T234	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	36487	0	0
T1	17521	28	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T10	0	51	0	0
T12	0	54	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	84	0	0
T39	0	33	0	0
T41	0	25	0	0
T77	0	28	0	0
T86	0	96	0	0
T176	0	93	0	0
T234	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442900	0	0
T1	17521	10950	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	1	0	0
T172	2248	0	0	0
T196	45106	1	0	0
T235	865	0	0	0
T236	402	0	0	0
T237	12863	0	0	0
T238	494	0	0	0
T239	504	0	0	0
T240	407	0	0	0
T241	30315	0	0	0
T242	635	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	16036	0	0
T1	17521	85	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T10	0	21	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	118	0	0
T39	0	43	0	0
T41	0	22	0	0
T77	0	92	0	0
T86	0	225	0	0
T131	0	9	0	0
T176	0	43	0	0
T234	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	54	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T10	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T77	0	2	0	0
T86	0	1	0	0
T131	0	1	0	0
T176	0	1	0	0
T234	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6349218	0	0
T1	17521	10732	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6351491	0	0
T1	17521	10753	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	60	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T77	0	2	0	0
T86	0	1	0	0
T176	0	1	0	0
T234	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	55	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T10	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T77	0	2	0	0
T86	0	1	0	0
T131	0	1	0	0
T176	0	1	0	0
T234	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	54	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T10	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T77	0	2	0	0
T86	0	1	0	0
T131	0	1	0	0
T176	0	1	0	0
T234	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	54	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T10	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T77	0	2	0	0
T86	0	1	0	0
T131	0	1	0	0
T176	0	1	0	0
T234	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	15960	0	0
T1	17521	83	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T10	0	20	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T31	0	116	0	0
T39	0	41	0	0
T41	0	21	0	0
T77	0	90	0	0
T86	0	223	0	0
T131	0	8	0	0
T176	0	41	0	0
T234	0	55	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	32	0	0
T10	580	1	0	0
T11	902	0	0	0
T12	511	0	0	0
T23	8414	0	0	0
T29	33527	0	0	0
T31	0	2	0	0
T41	0	1	0	0
T45	739	0	0	0
T57	495	0	0	0
T58	495	0	0	0
T77	0	2	0	0
T131	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T135	0	1	0	0
T141	0	1	0	0
T149	504	0	0	0
T150	441	0	0	0
T152	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T5,T2
1	1	Covered	T6,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T10
0	1	Covered	T135
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T10
0	1	Covered	T9,T132,T231
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T10
1	-	Covered	T9,T132,T231

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T10
DetectSt	168	Covered	T6,T9,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T10
DebounceSt->IdleSt	163	Covered	T74,T202,T75
DetectSt->IdleSt	186	Covered	T135
DetectSt->StableSt	191	Covered	T6,T9,T10
IdleSt->DebounceSt	148	Covered	T6,T9,T10
StableSt->IdleSt	206	Covered	T6,T9,T132

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T10
0	1	Covered	T6,T9,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T202
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T135
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T132,T231
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	71	0	0
CntIncr_A	7084667	40349	0	0
CntNoWrap_A	7084667	6442944	0	0
DetectStDropOut_A	7084667	1	0	0
DetectedOut_A	7084667	80718	0	0
DetectedPulseOut_A	7084667	33	0	0
DisabledIdleSt_A	7084667	6251947	0	0
DisabledNoDetection_A	7084667	6254210	0	0
EnterDebounceSt_A	7084667	37	0	0
EnterDetectSt_A	7084667	34	0	0
EnterStableSt_A	7084667	33	0	0
PulseIsPulse_A	7084667	33	0	0
StayInStableSt	7084667	80663	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7084667	6691	0	0
gen_low_level_sva.LowLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	71	0	0
T6	2946	2	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T21	744	0	0	0
T40	0	2	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T131	0	2	0	0
T132	0	4	0	0
T161	0	2	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	40349	0	0
T6	2946	83	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	19	0	0
T10	0	51	0	0
T11	0	53	0	0
T12	0	54	0	0
T21	744	0	0	0
T40	0	2119	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T131	0	11	0	0
T132	0	88	0	0
T161	0	31	0	0
T183	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442944	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	940	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	1	0	0
T135	11404	1	0	0
T136	2608	0	0	0
T223	1140	0	0	0
T224	1627	0	0	0
T225	442	0	0	0
T226	504	0	0	0
T227	12039	0	0	0
T228	503	0	0	0
T229	1569	0	0	0
T230	19852	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	80718	0	0
T6	2946	251	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	44	0	0
T10	0	46	0	0
T11	0	105	0	0
T12	0	45	0	0
T21	744	0	0	0
T40	0	39	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T131	0	182	0	0
T132	0	133	0	0
T161	0	176	0	0
T183	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	33	0	0
T6	2946	1	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T21	744	0	0	0
T40	0	1	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T131	0	1	0	0
T132	0	2	0	0
T161	0	1	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6251947	0	0
T1	17521	10732	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	476	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6254210	0	0
T1	17521	10753	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	479	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	37	0	0
T6	2946	1	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T21	744	0	0	0
T40	0	1	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T131	0	1	0	0
T132	0	2	0	0
T161	0	1	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	34	0	0
T6	2946	1	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T21	744	0	0	0
T40	0	1	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T131	0	1	0	0
T132	0	2	0	0
T161	0	1	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	33	0	0
T6	2946	1	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T21	744	0	0	0
T40	0	1	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T131	0	1	0	0
T132	0	2	0	0
T161	0	1	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	33	0	0
T6	2946	1	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T21	744	0	0	0
T40	0	1	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T131	0	1	0	0
T132	0	2	0	0
T161	0	1	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	80663	0	0
T6	2946	249	0	0
T7	2264	0	0	0
T8	1125	0	0	0
T9	0	43	0	0
T10	0	44	0	0
T11	0	103	0	0
T12	0	43	0	0
T21	744	0	0	0
T40	0	37	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T131	0	180	0	0
T132	0	130	0	0
T161	0	174	0	0
T183	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6691	0	0
T1	17521	36	0	0
T2	2509	2	0	0
T3	13827	13	0	0
T4	402	0	0	0
T5	2088	14	0	0
T6	2946	7	0	0
T13	505	3	0	0
T14	8931	27	0	0
T15	407	0	0	0
T16	421	2	0	0
T46	0	5	0	0
T47	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	11	0	0
T9	64549	1	0	0
T22	10052	0	0	0
T44	684	0	0	0
T50	524	0	0	0
T51	691	0	0	0
T55	598	0	0	0
T62	524	0	0	0
T63	522	0	0	0
T73	405	0	0	0
T122	0	1	0	0
T124	424	0	0	0
T132	0	1	0	0
T144	0	1	0	0
T162	0	1	0	0
T200	0	1	0	0
T203	0	1	0	0
T231	0	1	0	0
T232	0	1	0	0
T243	0	1	0	0