Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T22,T23
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T22,T23
1	0	Covered	T14,T22,T23
1	1	Covered	T14,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T23
0	1	Covered	T65,T92,T93
1	0	Covered	T244,T245,T92

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T23
0	1	Covered	T14,T22,T23
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T22,T23
1	-	Covered	T14,T22,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T22,T23
DetectSt	168	Covered	T14,T22,T23
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T14,T22,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T22,T23
DebounceSt->IdleSt	163	Covered	T74,T97,T246
DetectSt->IdleSt	186	Covered	T65,T244,T245
DetectSt->StableSt	191	Covered	T14,T22,T23
IdleSt->DebounceSt	148	Covered	T14,T22,T23
StableSt->IdleSt	206	Covered	T14,T22,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T22,T23
0	1	Covered	T14,T22,T23
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T22,T23
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T14,T22,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T74,T97,T246
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T65,T244,T245
DetectSt	-	-	-	-	0	1	-	Covered	T14,T22,T23
DetectSt	-	-	-	-	0	0	-	Covered	T14,T22,T23
StableSt	-	-	-	-	-	-	1	Covered	T14,T22,T23
StableSt	-	-	-	-	-	-	0	Covered	T14,T22,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	2994	0	0
CntIncr_A	7084667	98255	0	0
CntNoWrap_A	7084667	6440021	0	0
DetectStDropOut_A	7084667	389	0	0
DetectedOut_A	7084667	68680	0	0
DetectedPulseOut_A	7084667	905	0	0
DisabledIdleSt_A	7084667	6006482	0	0
DisabledNoDetection_A	7084667	6008609	0	0
EnterDebounceSt_A	7084667	1514	0	0
EnterDetectSt_A	7084667	1481	0	0
EnterStableSt_A	7084667	905	0	0
PulseIsPulse_A	7084667	905	0	0
StayInStableSt	7084667	67671	0	0
gen_high_event_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	797	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	2994	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	18	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	28	0	0
T23	0	40	0	0
T30	0	2	0	0
T33	0	60	0	0
T34	0	42	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	26	0	0
T66	0	50	0	0
T67	0	24	0	0
T68	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	98255	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	648	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	1050	0	0
T23	0	780	0	0
T30	0	52	0	0
T33	0	1500	0	0
T34	0	1260	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	514	0	0
T66	0	1300	0	0
T67	0	852	0	0
T68	0	497	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6440021	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8512	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	389	0	0
T31	35439	0	0	0
T38	644	0	0	0
T65	4622	13	0	0
T74	0	1	0	0
T92	0	6	0	0
T93	0	11	0	0
T94	0	14	0	0
T95	0	4	0	0
T97	0	5	0	0
T98	0	28	0	0
T216	0	31	0	0
T247	0	5	0	0
T248	405	0	0	0
T249	422	0	0	0
T250	523	0	0	0
T251	1194	0	0	0
T252	695	0	0	0
T253	519	0	0	0
T254	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	68680	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	275	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	637	0	0
T23	0	2263	0	0
T30	0	5	0	0
T33	0	1850	0	0
T34	0	2305	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	1856	0	0
T67	0	697	0	0
T68	0	702	0	0
T255	0	27	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	905	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	9	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	14	0	0
T23	0	20	0	0
T30	0	1	0	0
T33	0	30	0	0
T34	0	21	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	25	0	0
T67	0	12	0	0
T68	0	7	0	0
T255	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6006482	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	3294	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6008609	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	3294	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	1514	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	9	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	14	0	0
T23	0	20	0	0
T30	0	1	0	0
T33	0	30	0	0
T34	0	21	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	13	0	0
T66	0	25	0	0
T67	0	12	0	0
T68	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	1481	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	9	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	14	0	0
T23	0	20	0	0
T30	0	1	0	0
T33	0	30	0	0
T34	0	21	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	13	0	0
T66	0	25	0	0
T67	0	12	0	0
T68	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	905	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	9	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	14	0	0
T23	0	20	0	0
T30	0	1	0	0
T33	0	30	0	0
T34	0	21	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	25	0	0
T67	0	12	0	0
T68	0	7	0	0
T255	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	905	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	9	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	14	0	0
T23	0	20	0	0
T30	0	1	0	0
T33	0	30	0	0
T34	0	21	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	25	0	0
T67	0	12	0	0
T68	0	7	0	0
T255	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	67671	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	266	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	623	0	0
T23	0	2243	0	0
T30	0	4	0	0
T33	0	1820	0	0
T34	0	2279	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	1831	0	0
T67	0	681	0	0
T68	0	694	0	0
T255	0	25	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	797	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	9	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	14	0	0
T23	0	20	0	0
T30	0	1	0	0
T33	0	30	0	0
T34	0	16	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	25	0	0
T67	0	8	0	0
T68	0	6	0	0
T78	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T86,T90
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T1,T2,T9
DetectSt->IdleSt	186	Covered	T31,T86,T90
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T9
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T31,T86,T90
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	935	0	0
CntIncr_A	7084667	45974	0	0
CntNoWrap_A	7084667	6442080	0	0
DetectStDropOut_A	7084667	33	0	0
DetectedOut_A	7084667	14896	0	0
DetectedPulseOut_A	7084667	388	0	0
DisabledIdleSt_A	7084667	6083751	0	0
DisabledNoDetection_A	7084667	6085376	0	0
EnterDebounceSt_A	7084667	511	0	0
EnterDetectSt_A	7084667	425	0	0
EnterStableSt_A	7084667	388	0	0
PulseIsPulse_A	7084667	388	0	0
StayInStableSt	7084667	14486	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	363	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	935	0	0
T1	17521	3	0	0
T2	2509	3	0	0
T3	13827	18	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	2	0	0
T7	0	2	0	0
T9	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	2	0	0
T23	0	1	0	0
T29	0	4	0	0
T56	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	45974	0	0
T1	17521	171	0	0
T2	2509	45	0	0
T3	13827	819	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	25	0	0
T7	0	25	0	0
T9	0	20	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	129	0	0
T23	0	25	0	0
T29	0	172	0	0
T56	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442080	0	0
T1	17521	10949	0	0
T2	2509	502	0	0
T3	13827	13400	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	940	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	33	0	0
T31	35439	3	0	0
T40	7580	0	0	0
T85	402	0	0	0
T86	14944	1	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T90	0	2	0	0
T91	0	2	0	0
T96	0	1	0	0
T99	0	7	0	0
T100	0	1	0	0
T102	0	2	0	0
T103	0	3	0	0
T104	0	7	0	0
T109	443	0	0	0
T110	438	0	0	0
T111	527	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	14896	0	0
T1	17521	9	0	0
T2	2509	4	0	0
T3	13827	327	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	3	0	0
T7	0	3	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	77	0	0
T29	0	134	0	0
T32	0	262	0	0
T34	0	389	0	0
T56	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	388	0	0
T1	17521	1	0	0
T2	2509	1	0	0
T3	13827	9	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T7	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	1	0	0
T29	0	2	0	0
T32	0	9	0	0
T34	0	5	0	0
T56	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6083751	0	0
T1	17521	10094	0	0
T2	2509	392	0	0
T3	13827	10073	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	868	0	0
T13	505	104	0	0
T14	8931	8255	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6085376	0	0
T1	17521	10113	0	0
T2	2509	394	0	0
T3	13827	10073	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	871	0	0
T13	505	105	0	0
T14	8931	8256	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	511	0	0
T1	17521	2	0	0
T2	2509	2	0	0
T3	13827	9	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	1	0	0
T23	0	1	0	0
T29	0	2	0	0
T56	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	425	0	0
T1	17521	1	0	0
T2	2509	1	0	0
T3	13827	9	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T7	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	1	0	0
T29	0	2	0	0
T32	0	9	0	0
T34	0	5	0	0
T56	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	388	0	0
T1	17521	1	0	0
T2	2509	1	0	0
T3	13827	9	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T7	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	1	0	0
T29	0	2	0	0
T32	0	9	0	0
T34	0	5	0	0
T56	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	388	0	0
T1	17521	1	0	0
T2	2509	1	0	0
T3	13827	9	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T7	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	1	0	0
T29	0	2	0	0
T32	0	9	0	0
T34	0	5	0	0
T56	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	14486	0	0
T1	17521	8	0	0
T2	2509	3	0	0
T3	13827	318	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	2	0	0
T7	0	2	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	76	0	0
T29	0	132	0	0
T32	0	253	0	0
T34	0	384	0	0
T56	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	363	0	0
T1	17521	1	0	0
T2	2509	1	0	0
T3	13827	9	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	1	0	0
T7	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	1	0	0
T29	0	2	0	0
T32	0	9	0	0
T34	0	5	0	0
T56	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T22,T23
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T22,T23
1	0	Covered	T14,T22,T23
1	1	Covered	T14,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T23
0	1	Covered	T34,T65,T169
1	0	Covered	T34,T68,T244

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T23
0	1	Covered	T14,T22,T23
1	0	Covered	T75,T256

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T22,T23
1	-	Covered	T14,T22,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T22,T23
DetectSt	168	Covered	T14,T22,T23
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T14,T22,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T22,T23
DebounceSt->IdleSt	163	Covered	T74,T97,T246
DetectSt->IdleSt	186	Covered	T34,T65,T68
DetectSt->StableSt	191	Covered	T14,T22,T23
IdleSt->DebounceSt	148	Covered	T14,T22,T23
StableSt->IdleSt	206	Covered	T14,T22,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T22,T23
0	1	Covered	T14,T22,T23
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T22,T23
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T14,T22,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T74,T97,T246
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T34,T65,T68
DetectSt	-	-	-	-	0	1	-	Covered	T14,T22,T23
DetectSt	-	-	-	-	0	0	-	Covered	T14,T22,T23
StableSt	-	-	-	-	-	-	1	Covered	T14,T22,T23
StableSt	-	-	-	-	-	-	0	Covered	T14,T22,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	2829	0	0
CntIncr_A	7084667	96287	0	0
CntNoWrap_A	7084667	6440186	0	0
DetectStDropOut_A	7084667	373	0	0
DetectedOut_A	7084667	71211	0	0
DetectedPulseOut_A	7084667	787	0	0
DisabledIdleSt_A	7084667	6004607	0	0
DisabledNoDetection_A	7084667	6006746	0	0
EnterDebounceSt_A	7084667	1430	0	0
EnterDetectSt_A	7084667	1402	0	0
EnterStableSt_A	7084667	787	0	0
PulseIsPulse_A	7084667	787	0	0
StayInStableSt	7084667	70333	0	0
gen_high_event_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	694	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	2829	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	16	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	48	0	0
T23	0	38	0	0
T30	0	26	0	0
T33	0	6	0	0
T34	0	28	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	14	0	0
T66	0	6	0	0
T67	0	50	0	0
T68	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	96287	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	464	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	2304	0	0
T23	0	988	0	0
T30	0	429	0	0
T33	0	147	0	0
T34	0	1477	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	274	0	0
T66	0	165	0	0
T67	0	1375	0	0
T68	0	3689	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6440186	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8514	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	373	0	0
T34	26689	4	0	0
T60	492	0	0	0
T61	494	0	0	0
T65	0	7	0	0
T69	1192	0	0	0
T70	2161	0	0	0
T74	0	1	0	0
T92	0	10	0	0
T93	0	24	0	0
T94	0	26	0	0
T95	0	6	0	0
T98	0	14	0	0
T169	0	17	0	0
T257	0	8	0	0
T258	427	0	0	0
T259	4850	0	0	0
T260	38402	0	0	0
T261	1905	0	0	0
T262	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	71211	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	356	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	1987	0	0
T23	0	844	0	0
T30	0	952	0	0
T33	0	83	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	42	0	0
T67	0	2380	0	0
T78	0	5248	0	0
T245	0	733	0	0
T263	0	1804	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	787	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	8	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	24	0	0
T23	0	19	0	0
T30	0	13	0	0
T33	0	3	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	3	0	0
T67	0	25	0	0
T78	0	13	0	0
T245	0	25	0	0
T263	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6004607	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	3305	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6006746	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	3305	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	1430	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	8	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	24	0	0
T23	0	19	0	0
T30	0	13	0	0
T33	0	3	0	0
T34	0	14	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	7	0	0
T66	0	3	0	0
T67	0	25	0	0
T68	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	1402	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	8	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	24	0	0
T23	0	19	0	0
T30	0	13	0	0
T33	0	3	0	0
T34	0	14	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	7	0	0
T66	0	3	0	0
T67	0	25	0	0
T68	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	787	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	8	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	24	0	0
T23	0	19	0	0
T30	0	13	0	0
T33	0	3	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	3	0	0
T67	0	25	0	0
T78	0	13	0	0
T245	0	25	0	0
T263	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	787	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	8	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	24	0	0
T23	0	19	0	0
T30	0	13	0	0
T33	0	3	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	3	0	0
T67	0	25	0	0
T78	0	13	0	0
T245	0	25	0	0
T263	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	70333	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	348	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	1963	0	0
T23	0	825	0	0
T30	0	937	0	0
T33	0	80	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	39	0	0
T67	0	2348	0	0
T78	0	5231	0	0
T245	0	708	0	0
T263	0	1782	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	694	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	8	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	24	0	0
T23	0	19	0	0
T30	0	11	0	0
T33	0	3	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T66	0	3	0	0
T67	0	18	0	0
T78	0	9	0	0
T245	0	25	0	0
T263	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T3,T9,T32
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T30
0	1	Covered	T1,T29,T30
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T29,T30
1	-	Covered	T1,T29,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T9
DetectSt	168	Covered	T1,T3,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T29,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T9
DebounceSt->IdleSt	163	Covered	T9,T31,T208
DetectSt->IdleSt	186	Covered	T3,T9,T32
DetectSt->StableSt	191	Covered	T1,T29,T30
IdleSt->DebounceSt	148	Covered	T1,T3,T9
StableSt->IdleSt	206	Covered	T1,T29,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T31,T208
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T3,T9,T32
DetectSt	-	-	-	-	0	1	-	Covered	T1,T29,T30
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T29,T30
StableSt	-	-	-	-	-	-	0	Covered	T1,T29,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	810	0	0
CntIncr_A	7084667	44275	0	0
CntNoWrap_A	7084667	6442205	0	0
DetectStDropOut_A	7084667	51	0	0
DetectedOut_A	7084667	14314	0	0
DetectedPulseOut_A	7084667	333	0	0
DisabledIdleSt_A	7084667	6087386	0	0
DisabledNoDetection_A	7084667	6089080	0	0
EnterDebounceSt_A	7084667	423	0	0
EnterDetectSt_A	7084667	389	0	0
EnterStableSt_A	7084667	333	0	0
PulseIsPulse_A	7084667	333	0	0
StayInStableSt	7084667	13952	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	299	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	810	0	0
T1	17521	6	0	0
T2	2509	0	0	0
T3	13827	12	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	5	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T29	0	26	0	0
T30	0	4	0	0
T31	0	13	0	0
T32	0	4	0	0
T86	0	2	0	0
T90	0	4	0	0
T264	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	44275	0	0
T1	17521	399	0	0
T2	2509	0	0	0
T3	13827	764	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	345	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T29	0	1885	0	0
T30	0	118	0	0
T31	0	405	0	0
T32	0	342	0	0
T86	0	82	0	0
T90	0	160	0	0
T264	0	852	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442205	0	0
T1	17521	10946	0	0
T2	2509	505	0	0
T3	13827	13406	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	51	0	0
T3	13827	6	0	0
T6	2946	0	0	0
T7	2264	0	0	0
T9	0	2	0	0
T21	744	0	0	0
T32	0	2	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T86	0	1	0	0
T175	0	2	0	0
T188	0	9	0	0
T191	0	6	0	0
T207	0	1	0	0
T230	0	6	0	0
T265	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	14314	0	0
T1	17521	84	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T29	0	116	0	0
T30	0	81	0	0
T31	0	322	0	0
T67	0	207	0	0
T90	0	30	0	0
T208	0	5	0	0
T210	0	20	0	0
T264	0	60	0	0
T266	0	190	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	333	0	0
T1	17521	3	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T29	0	13	0	0
T30	0	2	0	0
T31	0	6	0	0
T67	0	7	0	0
T90	0	2	0	0
T208	0	1	0	0
T210	0	3	0	0
T264	0	6	0	0
T266	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6087386	0	0
T1	17521	10134	0	0
T2	2509	505	0	0
T3	13827	10073	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8174	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6089080	0	0
T1	17521	10154	0	0
T2	2509	509	0	0
T3	13827	10073	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8175	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	423	0	0
T1	17521	3	0	0
T2	2509	0	0	0
T3	13827	6	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	3	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T29	0	13	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	2	0	0
T86	0	1	0	0
T90	0	2	0	0
T264	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	389	0	0
T1	17521	3	0	0
T2	2509	0	0	0
T3	13827	6	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	2	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T29	0	13	0	0
T30	0	2	0	0
T31	0	6	0	0
T32	0	2	0	0
T86	0	1	0	0
T90	0	2	0	0
T264	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	333	0	0
T1	17521	3	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T29	0	13	0	0
T30	0	2	0	0
T31	0	6	0	0
T67	0	7	0	0
T90	0	2	0	0
T208	0	1	0	0
T210	0	3	0	0
T264	0	6	0	0
T266	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	333	0	0
T1	17521	3	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T29	0	13	0	0
T30	0	2	0	0
T31	0	6	0	0
T67	0	7	0	0
T90	0	2	0	0
T208	0	1	0	0
T210	0	3	0	0
T264	0	6	0	0
T266	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	13952	0	0
T1	17521	81	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T29	0	103	0	0
T30	0	79	0	0
T31	0	316	0	0
T67	0	200	0	0
T90	0	28	0	0
T208	0	4	0	0
T210	0	17	0	0
T264	0	54	0	0
T266	0	187	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	299	0	0
T1	17521	3	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T29	0	13	0	0
T30	0	2	0	0
T31	0	6	0	0
T67	0	7	0	0
T90	0	2	0	0
T208	0	1	0	0
T210	0	3	0	0
T264	0	6	0	0
T266	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T22,T23
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T22,T23
1	0	Covered	T14,T22,T23
1	1	Covered	T14,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T23
0	1	Covered	T30,T65,T66
1	0	Covered	T23,T30,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T33
0	1	Covered	T14,T22,T33
1	0	Covered	T79,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T22,T33
1	-	Covered	T14,T22,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T22,T23
DetectSt	168	Covered	T14,T22,T23
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T14,T22,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T22,T23
DebounceSt->IdleSt	163	Covered	T74,T97,T246
DetectSt->IdleSt	186	Covered	T23,T30,T65
DetectSt->StableSt	191	Covered	T14,T22,T33
IdleSt->DebounceSt	148	Covered	T14,T22,T23
StableSt->IdleSt	206	Covered	T14,T22,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T22,T23
0	1	Covered	T14,T22,T23
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T22,T23
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T14,T22,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T74,T97,T246
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T23,T30,T65
DetectSt	-	-	-	-	0	1	-	Covered	T14,T22,T33
DetectSt	-	-	-	-	0	0	-	Covered	T14,T22,T23
StableSt	-	-	-	-	-	-	1	Covered	T14,T22,T33
StableSt	-	-	-	-	-	-	0	Covered	T14,T22,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	3130	0	0
CntIncr_A	7084667	99716	0	0
CntNoWrap_A	7084667	6439885	0	0
DetectStDropOut_A	7084667	438	0	0
DetectedOut_A	7084667	76482	0	0
DetectedPulseOut_A	7084667	884	0	0
DisabledIdleSt_A	7084667	6003128	0	0
DisabledNoDetection_A	7084667	6005239	0	0
EnterDebounceSt_A	7084667	1582	0	0
EnterDetectSt_A	7084667	1549	0	0
EnterStableSt_A	7084667	884	0	0
PulseIsPulse_A	7084667	884	0	0
StayInStableSt	7084667	75479	0	0
gen_high_event_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	760	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	3130	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	24	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	4	0	0
T23	0	38	0	0
T30	0	48	0	0
T33	0	4	0	0
T34	0	18	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	36	0	0
T66	0	16	0	0
T67	0	28	0	0
T68	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	99716	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	816	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	152	0	0
T23	0	1396	0	0
T30	0	1304	0	0
T33	0	114	0	0
T34	0	774	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	719	0	0
T66	0	540	0	0
T67	0	826	0	0
T68	0	1924	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6439885	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8506	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	438	0	0
T30	12885	14	0	0
T38	644	0	0	0
T65	4622	18	0	0
T66	0	1	0	0
T74	0	1	0	0
T79	0	17	0	0
T93	0	24	0	0
T94	0	14	0	0
T95	0	24	0	0
T169	0	5	0	0
T248	405	0	0	0
T249	422	0	0	0
T250	523	0	0	0
T251	1194	0	0	0
T252	695	0	0	0
T253	519	0	0	0
T254	425	0	0	0
T267	0	17	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	76482	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	415	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	90	0	0
T33	0	38	0	0
T34	0	908	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	803	0	0
T68	0	2887	0	0
T78	0	4035	0	0
T244	0	718	0	0
T263	0	264	0	0
T268	0	2579	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	884	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	12	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	2	0	0
T33	0	2	0	0
T34	0	9	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	14	0	0
T68	0	26	0	0
T78	0	8	0	0
T244	0	15	0	0
T263	0	2	0	0
T268	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6003128	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	3288	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6005239	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	3288	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	1582	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	12	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	2	0	0
T23	0	19	0	0
T30	0	24	0	0
T33	0	2	0	0
T34	0	9	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	18	0	0
T66	0	8	0	0
T67	0	14	0	0
T68	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	1549	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	12	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	2	0	0
T23	0	19	0	0
T30	0	24	0	0
T33	0	2	0	0
T34	0	9	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	18	0	0
T66	0	8	0	0
T67	0	14	0	0
T68	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	884	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	12	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	2	0	0
T33	0	2	0	0
T34	0	9	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	14	0	0
T68	0	26	0	0
T78	0	8	0	0
T244	0	15	0	0
T263	0	2	0	0
T268	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	884	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	12	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	2	0	0
T33	0	2	0	0
T34	0	9	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	14	0	0
T68	0	26	0	0
T78	0	8	0	0
T244	0	15	0	0
T263	0	2	0	0
T268	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	75479	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	403	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	88	0	0
T33	0	36	0	0
T34	0	897	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	786	0	0
T68	0	2858	0	0
T78	0	4025	0	0
T244	0	702	0	0
T263	0	261	0	0
T268	0	2557	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	760	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	12	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	2	0	0
T33	0	2	0	0
T34	0	7	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	11	0	0
T68	0	23	0	0
T78	0	6	0	0
T244	0	14	0	0
T263	0	1	0	0
T268	0	20	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T208,T269
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T20
0	1	Covered	T3,T9,T20
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T20
1	-	Covered	T3,T9,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T9
DetectSt	168	Covered	T1,T3,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T9,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T9
DebounceSt->IdleSt	163	Covered	T31,T90,T270
DetectSt->IdleSt	186	Covered	T1,T208,T269
DetectSt->StableSt	191	Covered	T3,T9,T20
IdleSt->DebounceSt	148	Covered	T1,T3,T9
StableSt->IdleSt	206	Covered	T3,T9,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T90,T270
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T1,T208,T269
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T20
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T20
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	783	0	0
CntIncr_A	7084667	41325	0	0
CntNoWrap_A	7084667	6442232	0	0
DetectStDropOut_A	7084667	31	0	0
DetectedOut_A	7084667	14612	0	0
DetectedPulseOut_A	7084667	335	0	0
DisabledIdleSt_A	7084667	6088355	0	0
DisabledNoDetection_A	7084667	6090043	0	0
EnterDebounceSt_A	7084667	413	0	0
EnterDetectSt_A	7084667	370	0	0
EnterStableSt_A	7084667	335	0	0
PulseIsPulse_A	7084667	335	0	0
StayInStableSt	7084667	14244	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	300	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	783	0	0
T1	17521	2	0	0
T2	2509	0	0	0
T3	13827	6	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	2	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	2	0	0
T31	0	6	0	0
T32	0	6	0	0
T34	0	4	0	0
T90	0	15	0	0
T264	0	6	0	0
T270	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	41325	0	0
T1	17521	160	0	0
T2	2509	0	0	0
T3	13827	354	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	131	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	174	0	0
T31	0	236	0	0
T32	0	471	0	0
T34	0	96	0	0
T90	0	702	0	0
T264	0	246	0	0
T270	0	547	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442232	0	0
T1	17521	10950	0	0
T2	2509	505	0	0
T3	13827	13412	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	31	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	0	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T100	0	3	0	0
T175	0	1	0	0
T196	0	6	0	0
T208	0	3	0	0
T230	0	9	0	0
T269	0	2	0	0
T271	0	1	0	0
T272	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	14612	0	0
T3	13827	27	0	0
T6	2946	0	0	0
T7	2264	0	0	0
T9	0	10	0	0
T20	0	32	0	0
T21	744	0	0	0
T31	0	84	0	0
T32	0	44	0	0
T34	0	177	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T90	0	32	0	0
T264	0	210	0	0
T266	0	37	0	0
T270	0	69	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	335	0	0
T3	13827	3	0	0
T6	2946	0	0	0
T7	2264	0	0	0
T9	0	1	0	0
T20	0	1	0	0
T21	744	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T34	0	2	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T90	0	7	0	0
T264	0	3	0	0
T266	0	5	0	0
T270	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6088355	0	0
T1	17521	10134	0	0
T2	2509	505	0	0
T3	13827	10073	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8115	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6090043	0	0
T1	17521	10154	0	0
T2	2509	509	0	0
T3	13827	10073	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8116	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	413	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	3	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	1	0	0
T31	0	4	0	0
T32	0	3	0	0
T34	0	2	0	0
T90	0	8	0	0
T264	0	3	0	0
T270	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	370	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	3	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	1	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	1	0	0
T31	0	2	0	0
T32	0	3	0	0
T34	0	2	0	0
T90	0	7	0	0
T264	0	3	0	0
T270	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	335	0	0
T3	13827	3	0	0
T6	2946	0	0	0
T7	2264	0	0	0
T9	0	1	0	0
T20	0	1	0	0
T21	744	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T34	0	2	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T90	0	7	0	0
T264	0	3	0	0
T266	0	5	0	0
T270	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	335	0	0
T3	13827	3	0	0
T6	2946	0	0	0
T7	2264	0	0	0
T9	0	1	0	0
T20	0	1	0	0
T21	744	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T34	0	2	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T90	0	7	0	0
T264	0	3	0	0
T266	0	5	0	0
T270	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	14244	0	0
T3	13827	24	0	0
T6	2946	0	0	0
T7	2264	0	0	0
T9	0	9	0	0
T20	0	31	0	0
T21	744	0	0	0
T31	0	82	0	0
T32	0	41	0	0
T34	0	175	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T90	0	25	0	0
T264	0	207	0	0
T266	0	32	0	0
T270	0	68	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	300	0	0
T3	13827	3	0	0
T6	2946	0	0	0
T7	2264	0	0	0
T9	0	1	0	0
T20	0	1	0	0
T21	744	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T34	0	2	0	0
T42	59353	0	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T54	404	0	0	0
T90	0	7	0	0
T264	0	3	0	0
T266	0	5	0	0
T270	0	1	0	0