Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T22,T23
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T22,T23
1	0	Covered	T14,T22,T23
1	1	Covered	T14,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T23
0	1	Covered	T65,T268,T92
1	0	Covered	T66,T268,T245

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T22,T23
0	1	Covered	T14,T22,T23
1	0	Covered	T78,T256,T273

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T22,T23
1	-	Covered	T14,T22,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T22,T23
DetectSt	168	Covered	T14,T22,T23
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T14,T22,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T22,T23
DebounceSt->IdleSt	163	Covered	T74,T97,T246
DetectSt->IdleSt	186	Covered	T65,T66,T268
DetectSt->StableSt	191	Covered	T14,T22,T23
IdleSt->DebounceSt	148	Covered	T14,T22,T23
StableSt->IdleSt	206	Covered	T14,T22,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T22,T23
0	1	Covered	T14,T22,T23
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T22,T23
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T14,T22,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T74,T97,T246
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T22,T23
DetectSt	-	-	-	-	1	-	-	Covered	T65,T66,T268
DetectSt	-	-	-	-	0	1	-	Covered	T14,T22,T23
DetectSt	-	-	-	-	0	0	-	Covered	T14,T22,T23
StableSt	-	-	-	-	-	-	1	Covered	T14,T22,T23
StableSt	-	-	-	-	-	-	0	Covered	T14,T22,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	2975	0	0
CntIncr_A	7084667	102117	0	0
CntNoWrap_A	7084667	6440040	0	0
DetectStDropOut_A	7084667	360	0	0
DetectedOut_A	7084667	80532	0	0
DetectedPulseOut_A	7084667	924	0	0
DisabledIdleSt_A	7084667	6005580	0	0
DisabledNoDetection_A	7084667	6007691	0	0
EnterDebounceSt_A	7084667	1501	0	0
EnterDetectSt_A	7084667	1474	0	0
EnterStableSt_A	7084667	924	0	0
PulseIsPulse_A	7084667	924	0	0
StayInStableSt	7084667	79490	0	0
gen_high_event_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	794	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	2975	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	56	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	42	0	0
T23	0	28	0	0
T30	0	28	0	0
T33	0	48	0	0
T34	0	44	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	10	0	0
T66	0	6	0	0
T67	0	66	0	0
T68	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	102117	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	1680	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	1701	0	0
T23	0	518	0	0
T30	0	728	0	0
T33	0	1728	0	0
T34	0	1188	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	195	0	0
T66	0	202	0	0
T67	0	1617	0	0
T68	0	2106	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6440040	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8474	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	360	0	0
T31	35439	0	0	0
T38	644	0	0	0
T65	4622	5	0	0
T74	0	1	0	0
T92	0	7	0	0
T93	0	4	0	0
T94	0	25	0	0
T95	0	11	0	0
T97	0	11	0	0
T248	405	0	0	0
T249	422	0	0	0
T250	523	0	0	0
T251	1194	0	0	0
T252	695	0	0	0
T253	519	0	0	0
T254	425	0	0	0
T267	0	14	0	0
T268	0	2	0	0
T274	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	80532	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	2404	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	839	0	0
T23	0	534	0	0
T30	0	804	0	0
T33	0	653	0	0
T34	0	2895	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	2733	0	0
T68	0	2801	0	0
T78	0	5990	0	0
T244	0	2372	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	924	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	28	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	21	0	0
T23	0	14	0	0
T30	0	14	0	0
T33	0	24	0	0
T34	0	22	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	33	0	0
T68	0	26	0	0
T78	0	29	0	0
T244	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6005580	0	0
T1	17521	10952	0	0
T2	2509	505	0	0
T3	13827	13418	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	2031	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6007691	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	2031	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	1501	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	28	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	21	0	0
T23	0	14	0	0
T30	0	14	0	0
T33	0	24	0	0
T34	0	22	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	5	0	0
T66	0	3	0	0
T67	0	33	0	0
T68	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	1474	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	28	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	21	0	0
T23	0	14	0	0
T30	0	14	0	0
T33	0	24	0	0
T34	0	22	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T65	0	5	0	0
T66	0	3	0	0
T67	0	33	0	0
T68	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	924	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	28	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	21	0	0
T23	0	14	0	0
T30	0	14	0	0
T33	0	24	0	0
T34	0	22	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	33	0	0
T68	0	26	0	0
T78	0	29	0	0
T244	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	924	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	28	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	21	0	0
T23	0	14	0	0
T30	0	14	0	0
T33	0	24	0	0
T34	0	22	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	33	0	0
T68	0	26	0	0
T78	0	29	0	0
T244	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	79490	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	2376	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	818	0	0
T23	0	520	0	0
T30	0	789	0	0
T33	0	627	0	0
T34	0	2868	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	2689	0	0
T68	0	2772	0	0
T78	0	5961	0	0
T244	0	2343	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	794	0	0
T3	13827	0	0	0
T6	2946	0	0	0
T14	8931	28	0	0
T15	407	0	0	0
T16	421	0	0	0
T21	744	0	0	0
T22	0	21	0	0
T23	0	14	0	0
T30	0	13	0	0
T33	0	22	0	0
T34	0	17	0	0
T46	502	0	0	0
T47	523	0	0	0
T48	4408	0	0	0
T49	422	0	0	0
T67	0	22	0	0
T68	0	23	0	0
T78	0	21	0	0
T244	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T31,T90,T264
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
1	0	Covered	T74,T76,T275

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T9
1	-	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T9
DetectSt	168	Covered	T1,T3,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T9
DebounceSt->IdleSt	163	Covered	T9,T32,T31
DetectSt->IdleSt	186	Covered	T31,T90,T264
DetectSt->StableSt	191	Covered	T1,T3,T9
IdleSt->DebounceSt	148	Covered	T1,T3,T9
StableSt->IdleSt	206	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T32,T31
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T31,T90,T264
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7084667	853	0	0
CntIncr_A	7084667	47019	0	0
CntNoWrap_A	7084667	6442162	0	0
DetectStDropOut_A	7084667	60	0	0
DetectedOut_A	7084667	15592	0	0
DetectedPulseOut_A	7084667	342	0	0
DisabledIdleSt_A	7084667	6073483	0	0
DisabledNoDetection_A	7084667	6075149	0	0
EnterDebounceSt_A	7084667	447	0	0
EnterDetectSt_A	7084667	407	0	0
EnterStableSt_A	7084667	342	0	0
PulseIsPulse_A	7084667	342	0	0
StayInStableSt	7084667	15219	0	0
gen_high_level_sva.HighLevelEvent_A	7084667	6445335	0	0
gen_not_sticky_sva.StableStDropOut_A	7084667	302	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	853	0	0
T1	17521	2	0	0
T2	2509	0	0	0
T3	13827	6	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	7	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	6	0	0
T30	0	2	0	0
T31	0	15	0	0
T32	0	22	0	0
T33	0	4	0	0
T34	0	8	0	0
T86	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	47019	0	0
T1	17521	119	0	0
T2	2509	0	0	0
T3	13827	279	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	350	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	342	0	0
T30	0	34	0	0
T31	0	650	0	0
T32	0	1710	0	0
T33	0	90	0	0
T34	0	324	0	0
T86	0	130	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6442162	0	0
T1	17521	10950	0	0
T2	2509	505	0	0
T3	13827	13412	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	8530	0	0
T15	407	6	0	0
T16	421	20	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	60	0	0
T31	35439	1	0	0
T36	0	1	0	0
T40	7580	0	0	0
T85	402	0	0	0
T86	14944	0	0	0
T87	494	0	0	0
T88	745	0	0	0
T89	854	0	0	0
T90	0	2	0	0
T109	443	0	0	0
T110	438	0	0	0
T111	527	0	0	0
T163	0	5	0	0
T191	0	6	0	0
T207	0	2	0	0
T208	0	5	0	0
T210	0	2	0	0
T264	0	4	0	0
T266	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	15592	0	0
T1	17521	41	0	0
T2	2509	0	0	0
T3	13827	102	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	139	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	277	0	0
T30	0	65	0	0
T31	0	68	0	0
T32	0	163	0	0
T33	0	164	0	0
T34	0	225	0	0
T86	0	32	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	342	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	3	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	3	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	3	0	0
T30	0	1	0	0
T31	0	6	0	0
T32	0	9	0	0
T33	0	2	0	0
T34	0	4	0	0
T86	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6073483	0	0
T1	17521	10134	0	0
T2	2509	505	0	0
T3	13827	10073	0	0
T4	402	1	0	0
T5	2088	886	0	0
T6	2946	942	0	0
T13	505	104	0	0
T14	8931	6126	0	0
T15	407	6	0	0
T16	421	20	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6075149	0	0
T1	17521	10154	0	0
T2	2509	509	0	0
T3	13827	10073	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	6127	0	0
T15	407	7	0	0
T16	421	21	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	447	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	3	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	4	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	3	0	0
T30	0	1	0	0
T31	0	8	0	0
T32	0	13	0	0
T33	0	2	0	0
T34	0	4	0	0
T86	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	407	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	3	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	3	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	3	0	0
T30	0	1	0	0
T31	0	7	0	0
T32	0	9	0	0
T33	0	2	0	0
T34	0	4	0	0
T86	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	342	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	3	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	3	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	3	0	0
T30	0	1	0	0
T31	0	6	0	0
T32	0	9	0	0
T33	0	2	0	0
T34	0	4	0	0
T86	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	342	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	3	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	3	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	3	0	0
T30	0	1	0	0
T31	0	6	0	0
T32	0	9	0	0
T33	0	2	0	0
T34	0	4	0	0
T86	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	15219	0	0
T1	17521	40	0	0
T2	2509	0	0	0
T3	13827	99	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	136	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	274	0	0
T30	0	64	0	0
T31	0	62	0	0
T32	0	154	0	0
T33	0	162	0	0
T34	0	221	0	0
T86	0	30	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	6445335	0	0
T1	17521	10975	0	0
T2	2509	509	0	0
T3	13827	13423	0	0
T4	402	2	0	0
T5	2088	888	0	0
T6	2946	946	0	0
T13	505	105	0	0
T14	8931	8531	0	0
T15	407	7	0	0
T16	421	21	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7084667	302	0	0
T1	17521	1	0	0
T2	2509	0	0	0
T3	13827	3	0	0
T4	402	0	0	0
T5	2088	0	0	0
T6	2946	0	0	0
T9	0	3	0	0
T13	505	0	0	0
T14	8931	0	0	0
T15	407	0	0	0
T16	421	0	0	0
T20	0	3	0	0
T30	0	1	0	0
T31	0	6	0	0
T32	0	9	0	0
T33	0	2	0	0
T34	0	4	0	0
T86	0	2	0	0