Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1095202918	10012	0	0
auto_block_debounce_ctl_rd_A	1095202918	1089	0	0
auto_block_out_ctl_rd_A	1095202918	1441	0	0
com_det_ctl_0_rd_A	1095202918	2973	0	0
com_det_ctl_1_rd_A	1095202918	3183	0	0
com_det_ctl_2_rd_A	1095202918	3074	0	0
com_det_ctl_3_rd_A	1095202918	2923	0	0
com_out_ctl_0_rd_A	1095202918	3267	0	0
com_out_ctl_1_rd_A	1095202918	3232	0	0
com_out_ctl_2_rd_A	1095202918	3153	0	0
com_out_ctl_3_rd_A	1095202918	3355	0	0
com_pre_det_ctl_0_rd_A	1095202918	789	0	0
com_pre_det_ctl_1_rd_A	1095202918	904	0	0
com_pre_det_ctl_2_rd_A	1095202918	821	0	0
com_pre_det_ctl_3_rd_A	1095202918	787	0	0
com_pre_sel_ctl_0_rd_A	1095202918	3098	0	0
com_pre_sel_ctl_1_rd_A	1095202918	3252	0	0
com_pre_sel_ctl_2_rd_A	1095202918	3077	0	0
com_pre_sel_ctl_3_rd_A	1095202918	3166	0	0
com_sel_ctl_0_rd_A	1095202918	3419	0	0
com_sel_ctl_1_rd_A	1095202918	3497	0	0
com_sel_ctl_2_rd_A	1095202918	3107	0	0
com_sel_ctl_3_rd_A	1095202918	3279	0	0
ec_rst_ctl_rd_A	1095202918	1864	0	0
intr_enable_rd_A	1095202918	1336	0	0
key_intr_ctl_rd_A	1095202918	1596	0	0
key_intr_debounce_ctl_rd_A	1095202918	915	0	0
key_invert_ctl_rd_A	1095202918	3205	0	0
pin_allowed_ctl_rd_A	1095202918	3993	0	0
pin_out_ctl_rd_A	1095202918	3392	0	0
pin_out_value_rd_A	1095202918	3569	0	0
regwen_rd_A	1095202918	867	0	0
ulp_ac_debounce_ctl_rd_A	1095202918	1006	0	0
ulp_ctl_rd_A	1095202918	947	0	0
ulp_lid_debounce_ctl_rd_A	1095202918	1099	0	0
ulp_pwrb_debounce_ctl_rd_A	1095202918	968	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	10012	0	0
T1	833451	14	0	0
T2	522915	0	0	0
T3	165934	0	0	0
T4	189095	0	0	0
T5	164412	0	0	0
T6	122275	0	0	0
T9	0	25	0	0
T13	63126	0	0	0
T14	218825	0	0	0
T15	36607	0	0	0
T16	52639	0	0	0
T20	0	15	0	0
T31	0	15	0	0
T36	0	4	0	0
T37	0	19	0	0
T56	0	6	0	0
T71	0	2	0	0
T86	0	8	0	0
T210	0	11	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	1089	0	0
T7	554876	0	0	0
T8	57990	0	0	0
T9	145787	0	0	0
T21	115397	16	0	0
T42	148383	0	0	0
T43	406360	9	0	0
T44	311401	0	0	0
T45	0	18	0	0
T50	130956	0	0	0
T51	96768	0	0	0
T54	74810	0	0	0
T71	0	10	0	0
T86	0	22	0	0
T140	0	10	0	0
T206	0	7	0	0
T293	0	7	0	0
T294	0	5	0	0
T295	0	7	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	1441	0	0
T7	554876	0	0	0
T8	57990	0	0	0
T9	145787	0	0	0
T21	115397	6	0	0
T42	148383	0	0	0
T43	406360	11	0	0
T44	311401	0	0	0
T45	0	8	0	0
T50	130956	0	0	0
T51	96768	0	0	0
T54	74810	0	0	0
T71	0	12	0	0
T86	0	29	0	0
T140	0	21	0	0
T206	0	10	0	0
T293	0	9	0	0
T294	0	7	0	0
T295	0	10	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	2973	0	0
T20	183406	0	0	0
T23	294519	34	0	0
T29	435857	34	0	0
T30	0	45	0	0
T32	0	65	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	1	0	0
T86	0	38	0	0
T92	0	78	0	0
T106	246199	0	0	0
T140	0	4	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	50	0	0
T245	0	18	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3183	0	0
T20	183406	0	0	0
T23	294519	32	0	0
T29	435857	55	0	0
T30	0	75	0	0
T32	0	43	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T86	0	26	0	0
T92	0	77	0	0
T106	246199	0	0	0
T140	0	4	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	41	0	0
T245	0	23	0	0
T257	0	28	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3074	0	0
T20	183406	0	0	0
T23	294519	42	0	0
T29	435857	35	0	0
T30	0	51	0	0
T32	0	62	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	6	0	0
T86	0	40	0	0
T92	0	73	0	0
T106	246199	0	0	0
T140	0	13	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	44	0	0
T245	0	31	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	2923	0	0
T20	183406	0	0	0
T23	294519	31	0	0
T29	435857	59	0	0
T30	0	34	0	0
T32	0	59	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	3	0	0
T86	0	33	0	0
T92	0	56	0	0
T106	246199	0	0	0
T140	0	9	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	44	0	0
T245	0	19	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3267	0	0
T20	183406	0	0	0
T23	294519	51	0	0
T29	435857	53	0	0
T30	0	68	0	0
T32	0	28	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	6	0	0
T86	0	60	0	0
T92	0	50	0	0
T106	246199	0	0	0
T140	0	11	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	17	0	0
T245	0	24	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3232	0	0
T20	183406	0	0	0
T23	294519	46	0	0
T29	435857	45	0	0
T30	0	35	0	0
T32	0	48	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	3	0	0
T86	0	33	0	0
T92	0	55	0	0
T106	246199	0	0	0
T140	0	10	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	49	0	0
T245	0	19	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3153	0	0
T20	183406	0	0	0
T23	294519	40	0	0
T29	435857	31	0	0
T30	0	74	0	0
T32	0	67	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	2	0	0
T86	0	48	0	0
T92	0	65	0	0
T106	246199	0	0	0
T140	0	2	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	22	0	0
T245	0	18	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3355	0	0
T20	183406	0	0	0
T23	294519	56	0	0
T29	435857	52	0	0
T30	0	60	0	0
T32	0	67	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	3	0	0
T86	0	35	0	0
T92	0	59	0	0
T106	246199	0	0	0
T140	0	14	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	50	0	0
T245	0	36	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	789	0	0
T71	0	8	0	0
T86	662874	46	0	0
T87	61895	0	0	0
T88	89567	0	0	0
T89	81109	0	0	0
T90	933268	0	0	0
T100	0	30	0	0
T101	0	7	0	0
T118	0	15	0	0
T137	175266	0	0	0
T138	303814	0	0	0
T139	33357	0	0	0
T140	0	14	0	0
T241	0	10	0	0
T296	0	12	0	0
T297	0	31	0	0
T298	0	24	0	0
T299	63332	0	0	0
T300	49013	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	904	0	0
T71	0	1	0	0
T86	662874	17	0	0
T87	61895	0	0	0
T88	89567	0	0	0
T89	81109	0	0	0
T90	933268	0	0	0
T100	0	12	0	0
T101	0	19	0	0
T118	0	11	0	0
T137	175266	0	0	0
T138	303814	0	0	0
T139	33357	0	0	0
T140	0	4	0	0
T241	0	29	0	0
T296	0	9	0	0
T297	0	19	0	0
T298	0	16	0	0
T299	63332	0	0	0
T300	49013	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	821	0	0
T86	662874	21	0	0
T87	61895	0	0	0
T88	89567	0	0	0
T89	81109	0	0	0
T90	933268	0	0	0
T100	0	31	0	0
T101	0	14	0	0
T118	0	14	0	0
T137	175266	0	0	0
T138	303814	0	0	0
T139	33357	0	0	0
T140	0	5	0	0
T141	0	3	0	0
T241	0	15	0	0
T296	0	3	0	0
T297	0	32	0	0
T298	0	7	0	0
T299	63332	0	0	0
T300	49013	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	787	0	0
T71	0	17	0	0
T86	662874	17	0	0
T87	61895	0	0	0
T88	89567	0	0	0
T89	81109	0	0	0
T90	933268	0	0	0
T100	0	27	0	0
T101	0	20	0	0
T118	0	10	0	0
T137	175266	0	0	0
T138	303814	0	0	0
T139	33357	0	0	0
T141	0	9	0	0
T241	0	14	0	0
T296	0	12	0	0
T297	0	23	0	0
T298	0	1	0	0
T299	63332	0	0	0
T300	49013	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3098	0	0
T20	183406	0	0	0
T23	294519	31	0	0
T29	435857	28	0	0
T30	0	37	0	0
T32	0	35	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	6	0	0
T86	0	30	0	0
T92	0	75	0	0
T106	246199	0	0	0
T140	0	10	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	29	0	0
T245	0	25	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3252	0	0
T20	183406	0	0	0
T23	294519	47	0	0
T29	435857	26	0	0
T30	0	66	0	0
T32	0	26	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	2	0	0
T86	0	33	0	0
T92	0	73	0	0
T106	246199	0	0	0
T140	0	12	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	53	0	0
T245	0	25	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3077	0	0
T20	183406	0	0	0
T23	294519	39	0	0
T29	435857	47	0	0
T30	0	73	0	0
T32	0	45	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	3	0	0
T86	0	37	0	0
T92	0	49	0	0
T106	246199	0	0	0
T140	0	10	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	32	0	0
T245	0	14	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3166	0	0
T20	183406	0	0	0
T23	294519	38	0	0
T29	435857	47	0	0
T30	0	66	0	0
T32	0	36	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	9	0	0
T86	0	37	0	0
T92	0	49	0	0
T106	246199	0	0	0
T140	0	14	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	35	0	0
T245	0	18	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3419	0	0
T20	183406	0	0	0
T23	294519	55	0	0
T29	435857	40	0	0
T30	0	46	0	0
T32	0	45	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	11	0	0
T86	0	54	0	0
T92	0	53	0	0
T106	246199	0	0	0
T140	0	6	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	32	0	0
T245	0	9	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3497	0	0
T20	183406	0	0	0
T23	294519	63	0	0
T29	435857	47	0	0
T30	0	74	0	0
T32	0	23	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T86	0	49	0	0
T92	0	53	0	0
T106	246199	0	0	0
T140	0	8	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	34	0	0
T245	0	14	0	0
T257	0	43	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3107	0	0
T20	183406	0	0	0
T23	294519	36	0	0
T29	435857	26	0	0
T30	0	55	0	0
T32	0	39	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	13	0	0
T86	0	29	0	0
T92	0	45	0	0
T106	246199	0	0	0
T140	0	1	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	51	0	0
T245	0	8	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3279	0	0
T20	183406	0	0	0
T23	294519	59	0	0
T29	435857	51	0	0
T30	0	35	0	0
T32	0	62	0	0
T39	72737	0	0	0
T45	184787	0	0	0
T58	44604	0	0	0
T71	0	13	0	0
T86	0	31	0	0
T92	0	53	0	0
T106	246199	0	0	0
T140	0	13	0	0
T149	121011	0	0	0
T150	152255	0	0	0
T151	251066	0	0	0
T164	0	28	0	0
T245	0	34	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	1864	0	0
T10	40654	0	0	0
T22	482514	0	0	0
T29	0	27	0	0
T30	0	22	0	0
T32	0	43	0	0
T44	311401	0	0	0
T51	96768	5	0	0
T55	290563	0	0	0
T62	18378	0	0	0
T63	261244	0	0	0
T64	40881	0	0	0
T65	0	1	0	0
T71	0	5	0	0
T73	87134	0	0	0
T86	0	65	0	0
T124	50983	0	0	0
T164	0	4	0	0
T301	0	4	0	0
T302	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	1336	0	0
T9	145787	0	0	0
T22	482514	0	0	0
T43	406360	15	0	0
T44	311401	0	0	0
T50	130956	0	0	0
T51	96768	0	0	0
T55	290563	0	0	0
T62	18378	0	0	0
T63	261244	0	0	0
T71	0	5	0	0
T73	87134	0	0	0
T86	0	29	0	0
T118	0	19	0	0
T140	0	39	0	0
T141	0	11	0	0
T171	0	18	0	0
T241	0	17	0	0
T296	0	9	0	0
T297	0	54	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	1596	0	0
T2	522915	4	0	0
T3	165934	0	0	0
T6	122275	0	0	0
T13	63126	0	0	0
T14	218825	0	0	0
T15	36607	0	0	0
T16	52639	0	0	0
T35	0	3	0	0
T38	0	3	0	0
T46	246069	0	0	0
T47	130809	0	0	0
T48	551065	0	0	0
T71	0	6	0	0
T86	0	36	0	0
T136	0	3	0	0
T145	0	4	0	0
T152	0	3	0	0
T177	0	8	0	0
T234	0	7	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	915	0	0
T71	0	7	0	0
T86	662874	26	0	0
T87	61895	0	0	0
T88	89567	0	0	0
T89	81109	0	0	0
T90	933268	0	0	0
T100	0	37	0	0
T101	0	13	0	0
T118	0	8	0	0
T137	175266	0	0	0
T138	303814	0	0	0
T139	33357	0	0	0
T140	0	1	0	0
T241	0	20	0	0
T297	0	33	0	0
T298	0	5	0	0
T299	63332	0	0	0
T300	49013	0	0	0
T303	0	31	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3205	0	0
T2	522915	0	0	0
T3	165934	0	0	0
T5	164412	74	0	0
T6	122275	0	0	0
T13	63126	0	0	0
T14	218825	0	0	0
T15	36607	0	0	0
T16	52639	0	0	0
T46	246069	0	0	0
T47	130809	0	0	0
T59	0	62	0	0
T60	0	65	0	0
T71	0	7	0	0
T86	0	107	0	0
T140	0	70	0	0
T145	0	66	0	0
T304	0	86	0	0
T305	0	57	0	0
T306	0	65	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3993	0	0
T3	165934	0	0	0
T6	122275	0	0	0
T13	63126	37	0	0
T14	218825	0	0	0
T15	36607	0	0	0
T16	52639	0	0	0
T46	246069	0	0	0
T47	130809	0	0	0
T48	551065	0	0	0
T49	206930	0	0	0
T71	0	38	0	0
T86	0	16	0	0
T145	0	74	0	0
T167	0	41	0	0
T261	0	222	0	0
T293	0	68	0	0
T307	0	55	0	0
T308	0	80	0	0
T309	0	70	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3392	0	0
T3	165934	0	0	0
T6	122275	0	0	0
T13	63126	71	0	0
T14	218825	0	0	0
T15	36607	0	0	0
T16	52639	0	0	0
T46	246069	0	0	0
T47	130809	0	0	0
T48	551065	0	0	0
T49	206930	0	0	0
T71	0	42	0	0
T86	0	32	0	0
T145	0	59	0	0
T167	0	37	0	0
T261	0	216	0	0
T293	0	60	0	0
T307	0	44	0	0
T308	0	52	0	0
T309	0	56	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	3569	0	0
T3	165934	0	0	0
T6	122275	0	0	0
T13	63126	29	0	0
T14	218825	0	0	0
T15	36607	0	0	0
T16	52639	0	0	0
T46	246069	0	0	0
T47	130809	0	0	0
T48	551065	0	0	0
T49	206930	0	0	0
T71	0	56	0	0
T86	0	35	0	0
T145	0	67	0	0
T167	0	44	0	0
T261	0	193	0	0
T293	0	60	0	0
T307	0	36	0	0
T308	0	70	0	0
T309	0	40	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	867	0	0
T71	0	6	0	0
T86	662874	23	0	0
T87	61895	0	0	0
T88	89567	0	0	0
T89	81109	0	0	0
T90	933268	0	0	0
T100	0	25	0	0
T101	0	11	0	0
T118	0	12	0	0
T137	175266	0	0	0
T138	303814	0	0	0
T139	33357	0	0	0
T140	0	6	0	0
T241	0	23	0	0
T296	0	7	0	0
T297	0	29	0	0
T298	0	10	0	0
T299	63332	0	0	0
T300	49013	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	1006	0	0
T2	522915	6	0	0
T3	165934	0	0	0
T5	164412	4	0	0
T6	122275	0	0	0
T13	63126	0	0	0
T14	218825	0	0	0
T15	36607	0	0	0
T16	52639	0	0	0
T46	246069	0	0	0
T47	130809	0	0	0
T52	0	12	0	0
T69	0	8	0	0
T71	0	4	0	0
T72	0	5	0	0
T86	0	36	0	0
T114	0	2	0	0
T125	0	3	0	0
T251	0	5	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	947	0	0
T2	522915	4	0	0
T3	165934	0	0	0
T5	164412	6	0	0
T6	122275	0	0	0
T13	63126	0	0	0
T14	218825	0	0	0
T15	36607	0	0	0
T16	52639	0	0	0
T46	246069	0	0	0
T47	130809	0	0	0
T52	0	4	0	0
T69	0	9	0	0
T71	0	20	0	0
T72	0	14	0	0
T86	0	37	0	0
T116	0	1	0	0
T139	0	7	0	0
T251	0	3	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	1099	0	0
T2	522915	2	0	0
T3	165934	0	0	0
T5	164412	6	0	0
T6	122275	0	0	0
T13	63126	0	0	0
T14	218825	0	0	0
T15	36607	0	0	0
T16	52639	0	0	0
T46	246069	0	0	0
T47	130809	0	0	0
T52	0	18	0	0
T69	0	19	0	0
T71	0	3	0	0
T72	0	8	0	0
T86	0	37	0	0
T114	0	9	0	0
T116	0	9	0	0
T251	0	2	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095202918	968	0	0
T2	522915	1	0	0
T3	165934	0	0	0
T5	164412	5	0	0
T6	122275	0	0	0
T13	63126	0	0	0
T14	218825	0	0	0
T15	36607	0	0	0
T16	52639	0	0	0
T46	246069	0	0	0
T47	130809	0	0	0
T52	0	5	0	0
T69	0	12	0	0
T71	0	4	0	0
T72	0	13	0	0
T86	0	37	0	0
T114	0	9	0	0
T139	0	10	0	0
T251	0	7	0	0