Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1752

1

T18

4

T2

6

T3

34

auto[1]

555

1

T2

4

T3

6

T9

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1755

1

T18

3

T2

8

T3

31

auto[1]

552

1

T18

1

T2

2

T3

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1775

1

T18

3

T3

35

T7

6

auto[1]

532

1

T18

1

T2

10

T3

5

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1758

1

T18

4

T2

6

T3

32

auto[1]

549

1

T2

4

T3

8

T7

9

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2125

1

T18

3

T2

10

T3

32

auto[1]

182

1

T18

1

T3

8

T42

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2169

1

T18

4

T2

10

T3

39

auto[1]

138

1

T3

1

T42

1

T35

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2078

1

T18

4

T2

10

T3

36

auto[1]

229

1

T3

4

T9

2

T49

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2116

1

T18

4

T2

10

T3

34

auto[1]

191

1

T3

6

T9

2

T42

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2170

1

T18

4

T2

10

T3

31

auto[1]

137

1

T3

9

T9

7

T35

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1761

1

T18

4

T3

40

T7

6

auto[1]

546

1

T2

10

T7

3

T10

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	911	1			T2	10		T7	9		T10	2
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	72	1			T18	1		T42	3		T71	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	34	1			T9	6		T75	4		T359	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	14	1			T3	4		T84	4		T360	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	41	1			T72	4		T75	3		T361	12
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	18	1			T257	18		-	-		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	25	1			T3	5		T71	4		T362	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T74	1		T359	1		T241	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	66	1			T89	5		T251	2		T212	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	9	1			T3	4		T181	2		T93	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	20	1			T181	5		T248	1		T360	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T49	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	56	1			T9	1		T75	2		T357	32
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	8	1			T356	6		T363	2		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T9	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	25	1			T35	4		T250	1		T258	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	22	1			T75	1		T364	11		T365	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	8	1			T49	4		T366	1		T367	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	15	1			T42	1		T368	4		T257	6
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	3	1			T369	3		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T370	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T35	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	25	1			T351	2		T356	13		T371	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	7	1			T364	5		T363	2		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	10	1			T241	3		T356	7		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T241	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

142

1

T9

1

T42

1

T359

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

124

1

T75

3

T361

4

T368

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

42

1

T260

4

T294

6

T225

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

111

1

T3

4

T42

3

T116

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

48

1

T252

7

T264

5

T181

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

69

1

T251

2

T96

4

T351

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T95

3

T161

2

T371

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

102

1

T35

2

T49

4

T74

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

62

1

T34

5

T116

6

T40

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T359

1

T294

4

T96

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T2

4

T259

2

T346

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

65

1

T222

8

T87

4

T84

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T34

3

T250

1

T262

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23

1

T2

4

T35

4

T116

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T230

4

T372

1

T194

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

127

1

T9

1

T34

12

T49

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

73

1

T3

5

T116

5

T89

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T264

4

T214

3

T222

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T116

2

T75

3

T214

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T7

6

T9

6

T75

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T212

2

T262

2

T96

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T40

1

T181

2

T347

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T373

1

T350

2

T374

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

27

1

T18

1

T71

2

T72

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T87

3

T260

1

T81

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T2

2

T10

2

T71

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T171

1

T253

2

T346

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

19

1

T3

4

T116

2

T261

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T171

2

T294

2

T81

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T7

3

T87

1

T174

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T264

1

T214

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded