Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1010

1

T1

12

T4

10

T14

11

auto[1]

1034

1

T1

8

T4

10

T14

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

477

1

T1

6

T4

5

T14

3

from_0to1

476

1

T1

5

T4

5

T14

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T1

11

T4

9

T14

7

auto[1]

1025

1

T1

9

T4

11

T14

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1014

1

T1

7

T4

6

T14

9

auto[1]

1030

1

T1

13

T4

14

T14

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T1

1

T4

1

T70

2

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T1

1

T4

2

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T1

1

T25

1

T28

1

auto[0]

from_1to0

auto[1]

auto[1]

48

1

T14

1

T55

1

T70

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T1

1

T55

1

T70

2

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T1

1

T14

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T1

1

T25

3

T69

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T1

1

T4

1

T25

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T14

1

T55

1

T61

2

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T1

2

T14

1

T25

2

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T55

1

T70

1

T28

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T1

1

T4

2

T55

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T28

1

T69

1

T61

3

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T4

1

T55

2

T70

3

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T4

1

T14

2

T55

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T1

1

T4

2

T14

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T1

9

T4

13

T14

10

auto[1]

1025

1

T1

11

T4

7

T14

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

483

1

T1

5

T4

4

T14

5

from_0to1

483

1

T1

5

T4

4

T14

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T1

7

T4

15

T14

7

auto[1]

1072

1

T1

13

T4

5

T14

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1017

1

T1

8

T4

8

T14

10

auto[1]

1027

1

T1

12

T4

12

T14

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T70

2

T25

2

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T1

1

T4

3

T14

2

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T1

2

T14

1

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T55

1

T25

1

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T4

1

T25

2

T61

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T4

1

T70

1

T69

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T1

1

T4

1

T14

2

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T1

1

T14

2

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T14

1

T55

1

T70

2

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T61

1

T385

1

T386

2

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T14

1

T55

1

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T1

2

T4

1

T25

3

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T14

1

T70

1

T25

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T1

1

T55

2

T70

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T1

1

T14

1

T55

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T1

1

T4

1

T25

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

998

1

T1

8

T4

8

T14

11

auto[1]

1046

1

T1

12

T4

12

T14

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

492

1

T1

4

T4

4

T14

4

from_0to1

489

1

T1

4

T4

4

T14

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003

1

T1

13

T4

7

T14

14

auto[1]

1041

1

T1

7

T4

13

T14

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020

1

T1

12

T4

12

T14

10

auto[1]

1024

1

T1

8

T4

8

T14

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T4

2

T14

1

T70

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T1

1

T55

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T14

1

T55

2

T28

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T14

1

T70

1

T25

1

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T70

1

T25

2

T28

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T1

1

T14

1

T25

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T1

2

T4

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T25

1

T61

1

T387

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T55

1

T70

2

T69

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T4

2

T14

1

T55

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T1

2

T25

5

T28

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T1

1

T55

1

T70

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T1

1

T14

1

T55

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T14

1

T55

2

T70

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T4

1

T14

1

T55

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T4

2

T55

1

T388

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T1

9

T4

6

T14

11

auto[1]

1016

1

T1

11

T4

14

T14

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

483

1

T1

3

T4

4

T14

3

from_0to1

484

1

T1

4

T4

4

T14

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1012

1

T1

11

T4

6

T14

6

auto[1]

1032

1

T1

9

T4

14

T14

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T1

11

T4

8

T14

10

auto[1]

1012

1

T1

9

T4

12

T14

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T70

1

T25

3

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T55

3

T70

1

T25

2

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T4

1

T28

2

T69

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T1

1

T14

1

T55

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T55

1

T25

2

T69

2

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T14

1

T70

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T1

1

T14

1

T55

2

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T4

1

T61

1

T385

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T1

1

T4

1

T70

2

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T4

1

T14

1

T25

3

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T4

1

T14

1

T55

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T1

1

T28

1

T69

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T1

3

T4

1

T70

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T70

1

T25

3

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T25

1

T61

2

T40

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T4

2

T14

1

T55

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003

1

T1

10

T4

9

T14

10

auto[1]

1041

1

T1

10

T4

11

T14

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T1

5

T4

2

T14

7

from_0to1

501

1

T1

5

T4

3

T14

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T1

12

T4

11

T14

14

auto[1]

1012

1

T1

8

T4

9

T14

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T1

9

T4

10

T14

13

auto[1]

971

1

T1

11

T4

10

T14

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T1

1

T14

3

T55

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T14

1

T55

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T14

1

T70

2

T25

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T1

2

T55

2

T25

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T1

1

T4

1

T55

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T14

1

T70

1

T25

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T4

1

T14

2

T25

2

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T55

3

T70

1

T25

3

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T1

1

T4

1

T55

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T1

1

T14

1

T70

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T4

1

T70

1

T25

1

auto[1]

from_1to0

auto[1]

auto[1]

51

1

T14

1

T61

2

T387

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T14

1

T55

1

T70

2

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T1

3

T14

2

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T14

1

T61

2

T40

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T1

1

T4

1

T25

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T1

6

T4

9

T14

11

auto[1]

984

1

T1

14

T4

11

T14

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

493

1

T1

5

T4

6

T14

4

from_0to1

493

1

T1

5

T4

5

T14

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T1

12

T4

12

T14

9

auto[1]

990

1

T1

8

T4

8

T14

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T1

7

T4

7

T14

7

auto[1]

1026

1

T1

13

T4

13

T14

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T55

1

T70

1

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

85

1

T1

2

T4

1

T14

2

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T4

1

T70

1

T40

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T4

2

T25

2

T28

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T70

1

T69

1

T40

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T14

1

T55

2

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T14

1

T55

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T1

1

T4

1

T14

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T1

1

T14

1

T25

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T1

2

T4

1

T55

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T55

1

T25

3

T28

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T4

1

T14

1

T70

2

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T1

1

T4

2

T25

2

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T1

1

T4

1

T70

1

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T1

1

T14

1

T55

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T1

1

T4

1

T70

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T1

12

T4

12

T14

8

auto[1]

972

1

T1

8

T4

8

T14

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T1

5

T4

4

T14

4

from_0to1

472

1

T1

5

T4

3

T14

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T1

12

T4

10

T14

12

auto[1]

1016

1

T1

8

T4

10

T14

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T1

12

T4

12

T14

12

auto[1]

983

1

T1

8

T4

8

T14

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T1

1

T4

2

T55

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T1

1

T25

2

T61

2

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T1

2

T14

1

T55

2

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T4

1

T25

4

T69

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T1

2

T14

1

T55

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T55

1

T70

2

T25

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T4

1

T25

2

T387

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T4

1

T14

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T14

1

T25

1

T28

3

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T4

1

T70

1

T25

1

auto[1]

from_1to0

auto[1]

auto[0]

47

1

T1

1

T14

1

T55

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T14

1

T55

1

T70

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T1

1

T14

1

T70

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T1

2

T14

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T4

1

T55

1

T25

2

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T55

2

T25

1

T61

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T1

8

T4

9

T14

11

auto[1]

1010

1

T1

12

T4

11

T14

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

498

1

T1

4

T4

5

T14

3

from_0to1

493

1

T1

4

T4

4

T14

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1024

1

T1

13

T4

6

T14

10

auto[1]

1020

1

T1

7

T4

14

T14

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T1

10

T4

8

T14

9

auto[1]

1001

1

T1

10

T4

12

T14

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T1

1

T61

2

T40

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T70

2

T25

1

T69

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T4

2

T14

1

T55

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T14

1

T28

1

T61

2

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T70

2

T25

1

T388

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T1

1

T55

2

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T1

1

T4

1

T14

2

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T25

2

T28

1

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T1

2

T70

1

T25

2

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T55

1

T70

2

T25

2

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T25

1

T69

1

T61

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T1

1

T4

3

T14

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T4

1

T14

1

T55

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T1

1

T4

1

T14

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T1

1

T70

1

T25

2

auto[1]

from_0to1

auto[1]

auto[1]

45

1

T4

1

T40

2

T387

1