Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157851	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119144

1

T1

90

T4

53

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143665	1			T1	89		T4	62		T5	2
values[0x0]	65922	1			T1	77		T4	33		T13	3
values[0x1]	67408	1			T1	64		T4	28		T13	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127671	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149324

1

T1

110

T4

70

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	815	1			T3	8		T7	1		T9	1
valid_sources[0x01]	983	1			T1	2		T19	1		T53	2
valid_sources[0x02]	935	1			T43	1		T3	3		T7	3
valid_sources[0x03]	964	1			T1	2		T43	1		T2	11
valid_sources[0x04]	825	1			T19	3		T3	1		T53	1
valid_sources[0x05]	1028	1			T1	3		T2	9		T3	2
valid_sources[0x06]	1101	1			T1	3		T3	8		T7	1
valid_sources[0x07]	1213	1			T3	8		T7	3		T42	2
valid_sources[0x08]	766	1			T1	5		T7	1		T70	3
valid_sources[0x09]	1319	1			T14	2		T3	15		T9	6
valid_sources[0x0a]	720	1			T3	9		T51	4		T7	3
valid_sources[0x0b]	932	1			T1	1		T3	17		T7	2
valid_sources[0x0c]	925	1			T3	1		T7	1		T9	8
valid_sources[0x0d]	1472	1			T3	13		T70	3		T9	1
valid_sources[0x0e]	1509	1			T7	1		T25	3		T9	2
valid_sources[0x0f]	806	1			T1	2		T3	14		T9	7
valid_sources[0x10]	1009	1			T1	2		T14	6		T50	1
valid_sources[0x11]	1055	1			T1	3		T3	17		T7	3
valid_sources[0x12]	906	1			T2	10		T3	4		T7	2
valid_sources[0x13]	1055	1			T14	3		T7	1		T9	5
valid_sources[0x14]	1025	1			T1	1		T14	7		T3	18
valid_sources[0x15]	770	1			T17	3		T3	3		T7	1
valid_sources[0x16]	2098	1			T14	1		T3	2		T7	3
valid_sources[0x17]	1095	1			T1	5		T14	5		T3	3
valid_sources[0x18]	1167	1			T1	1		T2	6		T3	2
valid_sources[0x19]	701	1			T3	2		T7	2		T9	5
valid_sources[0x1a]	1731	1			T1	2		T3	3		T7	1
valid_sources[0x1b]	1168	1			T1	4		T2	50		T3	4
valid_sources[0x1c]	848	1			T1	2		T3	5		T7	4
valid_sources[0x1d]	860	1			T1	1		T19	2		T3	6
valid_sources[0x1e]	856	1			T14	5		T3	8		T51	2
valid_sources[0x1f]	1121	1			T70	2		T9	6		T10	3
valid_sources[0x20]	828	1			T14	1		T3	3		T53	1
valid_sources[0x21]	905	1			T3	5		T9	7		T10	4
valid_sources[0x22]	897	1			T4	22		T2	1		T7	2
valid_sources[0x23]	1405	1			T2	9		T7	2		T70	3
valid_sources[0x24]	883	1			T14	3		T2	3		T3	2
valid_sources[0x25]	667	1			T1	3		T2	2		T7	2
valid_sources[0x26]	854	1			T1	1		T3	2		T7	6
valid_sources[0x27]	2020	1			T7	3		T25	1		T9	1
valid_sources[0x28]	1239	1			T1	1		T4	59		T19	1
valid_sources[0x29]	751	1			T4	7		T2	10		T3	7
valid_sources[0x2a]	1012	1			T1	2		T3	9		T7	5
valid_sources[0x2b]	1620	1			T1	1		T3	8		T7	5
valid_sources[0x2c]	809	1			T14	1		T3	1		T51	4
valid_sources[0x2d]	1033	1			T14	2		T3	3		T9	5
valid_sources[0x2e]	1027	1			T1	1		T2	4		T3	2
valid_sources[0x2f]	895	1			T14	6		T3	8		T7	2
valid_sources[0x30]	984	1			T1	3		T3	2		T7	2
valid_sources[0x31]	1025	1			T3	1		T7	1		T70	2
valid_sources[0x32]	684	1			T14	1		T2	1		T3	2
valid_sources[0x33]	1087	1			T3	1		T25	3		T9	7
valid_sources[0x34]	1536	1			T43	1		T2	6		T3	3
valid_sources[0x35]	850	1			T13	18		T43	1		T3	7
valid_sources[0x36]	1005	1			T3	30		T53	1		T7	2
valid_sources[0x37]	832	1			T2	1		T3	10		T9	4
valid_sources[0x38]	983	1			T3	10		T7	2		T70	3
valid_sources[0x39]	1026	1			T1	1		T2	4		T7	1
valid_sources[0x3a]	1484	1			T1	3		T3	4		T7	2
valid_sources[0x3b]	1304	1			T2	7		T3	3		T7	5
valid_sources[0x3c]	775	1			T7	1		T25	1		T9	3
valid_sources[0x3d]	828	1			T19	1		T3	2		T7	1
valid_sources[0x3e]	1438	1			T14	1		T50	1		T3	6
valid_sources[0x3f]	838	1			T3	3		T7	2		T25	1
valid_sources[0x40]	1068	1			T1	1		T19	1		T2	10
valid_sources[0x41]	1038	1			T1	2		T19	1		T3	4
valid_sources[0x42]	919	1			T1	2		T14	1		T3	6
valid_sources[0x43]	855	1			T1	1		T3	5		T7	5
valid_sources[0x44]	1936	1			T2	12		T3	4		T53	1
valid_sources[0x45]	1034	1			T1	1		T2	5		T3	10
valid_sources[0x46]	679	1			T19	1		T3	6		T7	2
valid_sources[0x47]	880	1			T1	1		T3	3		T6	15
valid_sources[0x48]	1191	1			T1	3		T2	11		T51	7
valid_sources[0x49]	1065	1			T1	5		T3	6		T7	3
valid_sources[0x4a]	788	1			T19	1		T7	2		T25	8
valid_sources[0x4b]	865	1			T1	1		T50	1		T7	1
valid_sources[0x4c]	698	1			T1	1		T2	10		T3	3
valid_sources[0x4d]	704	1			T14	3		T50	1		T3	1
valid_sources[0x4e]	993	1			T1	6		T3	13		T51	1
valid_sources[0x4f]	1213	1			T1	1		T7	1		T70	1
valid_sources[0x50]	904	1			T14	1		T2	5		T3	2
valid_sources[0x51]	1556	1			T3	7		T7	1		T9	5
valid_sources[0x52]	989	1			T1	2		T3	11		T51	1
valid_sources[0x53]	1113	1			T2	6		T7	2		T9	7
valid_sources[0x54]	753	1			T17	10		T3	3		T7	1
valid_sources[0x55]	2078	1			T19	1		T3	6		T53	1
valid_sources[0x56]	730	1			T1	2		T3	3		T7	4
valid_sources[0x57]	929	1			T1	8		T3	4		T9	5
valid_sources[0x58]	1697	1			T1	2		T3	7		T53	1
valid_sources[0x59]	1068	1			T1	1		T3	5		T7	2
valid_sources[0x5a]	1278	1			T2	1		T3	22		T51	1
valid_sources[0x5b]	872	1			T14	7		T3	13		T7	1
valid_sources[0x5c]	1690	1			T18	801		T3	4		T9	1
valid_sources[0x5d]	782	1			T2	1		T7	2		T9	3
valid_sources[0x5e]	1129	1			T3	4		T7	2		T9	6
valid_sources[0x5f]	1330	1			T1	3		T3	3		T9	4
valid_sources[0x60]	970	1			T1	1		T51	2		T7	2
valid_sources[0x61]	1112	1			T2	9		T3	3		T9	3
valid_sources[0x62]	949	1			T1	1		T14	2		T3	5
valid_sources[0x63]	1453	1			T14	1		T3	6		T7	1
valid_sources[0x64]	2131	1			T1	1		T3	16		T7	1
valid_sources[0x65]	1054	1			T1	2		T3	12		T53	1
valid_sources[0x66]	896	1			T3	11		T7	2		T9	2
valid_sources[0x67]	1050	1			T1	1		T14	3		T3	4
valid_sources[0x68]	820	1			T7	2		T25	2		T9	5
valid_sources[0x69]	1648	1			T1	1		T3	8		T51	4
valid_sources[0x6a]	978	1			T2	3		T3	2		T9	8
valid_sources[0x6b]	1084	1			T4	17		T14	2		T3	11
valid_sources[0x6c]	952	1			T1	2		T3	12		T7	1
valid_sources[0x6d]	1893	1			T1	2		T2	13		T3	3
valid_sources[0x6e]	1075	1			T3	4		T7	2		T9	3
valid_sources[0x6f]	1842	1			T1	2		T3	3		T51	1
valid_sources[0x70]	777	1			T3	7		T9	3		T10	2
valid_sources[0x71]	826	1			T1	3		T3	3		T7	1
valid_sources[0x72]	691	1			T1	1		T3	1		T7	2
valid_sources[0x73]	916	1			T7	1		T9	4		T42	4
valid_sources[0x74]	1185	1			T3	4		T7	2		T9	2
valid_sources[0x75]	905	1			T2	11		T3	8		T7	2
valid_sources[0x76]	838	1			T1	3		T3	6		T9	4
valid_sources[0x77]	783	1			T3	19		T7	1		T25	8
valid_sources[0x78]	917	1			T1	3		T7	7		T25	1
valid_sources[0x79]	1004	1			T3	3		T7	3		T9	7
valid_sources[0x7a]	1838	1			T14	4		T3	6		T7	4
valid_sources[0x7b]	1155	1			T3	20		T51	3		T7	1
valid_sources[0x7c]	883	1			T14	2		T2	10		T3	11
valid_sources[0x7d]	899	1			T53	1		T7	2		T9	9
valid_sources[0x7e]	1215	1			T5	2		T3	2		T9	7
valid_sources[0x7f]	739	1			T1	1		T2	26		T3	12
valid_sources[0x80]	1000	1			T3	6		T44	15		T70	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64536

1

T1

44

T4

34

T5

1

values[0x0]

all_enables

biggest_size

31880

1

T1

34

T4

16

T13

2

values[0x1]

all_enables

biggest_size

22728

1

T1

12

T4

3

T13

2