Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1161874828	9458	0	0
auto_block_debounce_ctl_rd_A	1161874828	2096	0	0
auto_block_out_ctl_rd_A	1161874828	2770	0	0
com_det_ctl_0_rd_A	1161874828	4156	0	0
com_det_ctl_1_rd_A	1161874828	4391	0	0
com_det_ctl_2_rd_A	1161874828	4197	0	0
com_det_ctl_3_rd_A	1161874828	4301	0	0
com_out_ctl_0_rd_A	1161874828	4578	0	0
com_out_ctl_1_rd_A	1161874828	4785	0	0
com_out_ctl_2_rd_A	1161874828	4779	0	0
com_out_ctl_3_rd_A	1161874828	4716	0	0
com_pre_det_ctl_0_rd_A	1161874828	1866	0	0
com_pre_det_ctl_1_rd_A	1161874828	1861	0	0
com_pre_det_ctl_2_rd_A	1161874828	1831	0	0
com_pre_det_ctl_3_rd_A	1161874828	1896	0	0
com_pre_sel_ctl_0_rd_A	1161874828	4945	0	0
com_pre_sel_ctl_1_rd_A	1161874828	4919	0	0
com_pre_sel_ctl_2_rd_A	1161874828	4800	0	0
com_pre_sel_ctl_3_rd_A	1161874828	4963	0	0
com_sel_ctl_0_rd_A	1161874828	4860	0	0
com_sel_ctl_1_rd_A	1161874828	4748	0	0
com_sel_ctl_2_rd_A	1161874828	4650	0	0
com_sel_ctl_3_rd_A	1161874828	4965	0	0
ec_rst_ctl_rd_A	1161874828	2878	0	0
intr_enable_rd_A	1161874828	2737	0	0
key_intr_ctl_rd_A	1161874828	3710	0	0
key_intr_debounce_ctl_rd_A	1161874828	1804	0	0
key_invert_ctl_rd_A	1161874828	5091	0	0
pin_allowed_ctl_rd_A	1161874828	5638	0	0
pin_out_ctl_rd_A	1161874828	4330	0	0
pin_out_value_rd_A	1161874828	4688	0	0
regwen_rd_A	1161874828	2309	0	0
ulp_ac_debounce_ctl_rd_A	1161874828	1904	0	0
ulp_ctl_rd_A	1161874828	1878	0	0
ulp_lid_debounce_ctl_rd_A	1161874828	1949	0	0
ulp_pwrb_debounce_ctl_rd_A	1161874828	1939	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	9458	0	0
T33	109636	15	0	0
T35	108081	0	0	0
T37	0	31	0	0
T40	0	4	0	0
T61	0	8	0	0
T65	67237	0	0	0
T66	42127	0	0	0
T87	0	5	0	0
T118	0	7	0	0
T121	0	7	0	0
T124	429310	0	0	0
T132	411329	0	0	0
T133	180780	0	0	0
T134	24340	0	0	0
T135	211020	0	0	0
T136	461324	0	0	0
T153	0	5	0	0
T171	0	4	0	0
T184	0	8	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	2096	0	0
T7	151100	0	0	0
T8	33564	0	0	0
T9	976617	0	0	0
T25	695771	0	0	0
T28	60916	0	0	0
T44	140071	14	0	0
T45	315487	0	0	0
T46	0	13	0	0
T55	40560	0	0	0
T70	50675	0	0	0
T87	0	19	0	0
T118	0	60	0	0
T124	0	20	0	0
T169	202896	0	0	0
T170	0	49	0	0
T213	0	11	0	0
T263	0	41	0	0
T296	0	5	0	0
T297	0	9	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	2770	0	0
T7	151100	0	0	0
T8	33564	0	0	0
T9	976617	0	0	0
T25	695771	0	0	0
T28	60916	0	0	0
T44	140071	4	0	0
T45	315487	0	0	0
T46	0	13	0	0
T55	40560	0	0	0
T70	50675	0	0	0
T87	0	21	0	0
T118	0	52	0	0
T124	0	26	0	0
T131	0	3	0	0
T169	202896	0	0	0
T170	0	38	0	0
T263	0	26	0	0
T296	0	15	0	0
T297	0	3	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4156	0	0
T2	762504	62	0	0
T3	141079	84	0	0
T6	82378	0	0	0
T7	151100	57	0	0
T35	0	27	0	0
T44	140071	0	0	0
T49	0	97	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	70	0	0
T72	0	48	0	0
T74	0	18	0	0
T75	0	55	0	0
T89	0	39	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4391	0	0
T2	762504	55	0	0
T3	141079	90	0	0
T6	82378	0	0	0
T7	151100	76	0	0
T35	0	34	0	0
T44	140071	0	0	0
T49	0	64	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	66	0	0
T72	0	58	0	0
T74	0	24	0	0
T75	0	68	0	0
T89	0	41	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4197	0	0
T2	762504	41	0	0
T3	141079	99	0	0
T6	82378	0	0	0
T7	151100	62	0	0
T35	0	40	0	0
T44	140071	0	0	0
T49	0	75	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	78	0	0
T72	0	22	0	0
T74	0	21	0	0
T75	0	67	0	0
T89	0	52	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4301	0	0
T2	762504	79	0	0
T3	141079	100	0	0
T6	82378	0	0	0
T7	151100	71	0	0
T35	0	32	0	0
T44	140071	0	0	0
T49	0	52	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	52	0	0
T72	0	31	0	0
T74	0	8	0	0
T75	0	77	0	0
T89	0	71	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4578	0	0
T2	762504	55	0	0
T3	141079	84	0	0
T6	82378	0	0	0
T7	151100	67	0	0
T35	0	42	0	0
T44	140071	0	0	0
T49	0	77	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	47	0	0
T72	0	48	0	0
T74	0	27	0	0
T75	0	66	0	0
T89	0	63	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4785	0	0
T2	762504	69	0	0
T3	141079	116	0	0
T6	82378	0	0	0
T7	151100	66	0	0
T35	0	20	0	0
T44	140071	0	0	0
T49	0	76	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	89	0	0
T72	0	38	0	0
T74	0	25	0	0
T75	0	49	0	0
T89	0	53	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4779	0	0
T2	762504	75	0	0
T3	141079	104	0	0
T6	82378	0	0	0
T7	151100	74	0	0
T35	0	33	0	0
T44	140071	0	0	0
T49	0	67	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	60	0	0
T72	0	38	0	0
T74	0	29	0	0
T75	0	62	0	0
T89	0	67	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4716	0	0
T2	762504	59	0	0
T3	141079	107	0	0
T6	82378	0	0	0
T7	151100	84	0	0
T35	0	53	0	0
T44	140071	0	0	0
T49	0	55	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	65	0	0
T72	0	49	0	0
T74	0	34	0	0
T75	0	60	0	0
T89	0	45	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	1866	0	0
T87	0	19	0	0
T99	0	16	0	0
T118	486023	45	0	0
T147	0	8	0	0
T149	0	36	0	0
T170	0	22	0	0
T174	0	16	0	0
T184	267884	0	0	0
T198	0	20	0	0
T219	13959	0	0	0
T220	333942	0	0	0
T221	165013	0	0	0
T222	129683	0	0	0
T223	202535	0	0	0
T263	0	9	0	0
T298	0	28	0	0
T299	26637	0	0	0
T300	135345	0	0	0
T301	254734	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	1861	0	0
T87	0	32	0	0
T99	0	11	0	0
T118	486023	58	0	0
T131	0	7	0	0
T147	0	16	0	0
T149	0	12	0	0
T170	0	19	0	0
T184	267884	0	0	0
T198	0	13	0	0
T219	13959	0	0	0
T220	333942	0	0	0
T221	165013	0	0	0
T222	129683	0	0	0
T223	202535	0	0	0
T263	0	6	0	0
T298	0	55	0	0
T299	26637	0	0	0
T300	135345	0	0	0
T301	254734	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	1831	0	0
T87	0	17	0	0
T99	0	10	0	0
T118	486023	30	0	0
T131	0	5	0	0
T147	0	9	0	0
T149	0	11	0	0
T170	0	23	0	0
T184	267884	0	0	0
T198	0	23	0	0
T219	13959	0	0	0
T220	333942	0	0	0
T221	165013	0	0	0
T222	129683	0	0	0
T223	202535	0	0	0
T263	0	9	0	0
T298	0	29	0	0
T299	26637	0	0	0
T300	135345	0	0	0
T301	254734	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	1896	0	0
T87	0	22	0	0
T118	486023	47	0	0
T131	0	12	0	0
T147	0	9	0	0
T149	0	38	0	0
T170	0	25	0	0
T184	267884	0	0	0
T198	0	4	0	0
T219	13959	0	0	0
T220	333942	0	0	0
T221	165013	0	0	0
T222	129683	0	0	0
T223	202535	0	0	0
T263	0	9	0	0
T298	0	48	0	0
T299	26637	0	0	0
T300	135345	0	0	0
T301	254734	0	0	0
T302	0	7	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4945	0	0
T2	762504	87	0	0
T3	141079	114	0	0
T6	82378	0	0	0
T7	151100	65	0	0
T35	0	35	0	0
T44	140071	0	0	0
T49	0	74	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	61	0	0
T72	0	32	0	0
T74	0	22	0	0
T75	0	58	0	0
T89	0	32	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4919	0	0
T2	762504	64	0	0
T3	141079	111	0	0
T6	82378	0	0	0
T7	151100	74	0	0
T35	0	37	0	0
T44	140071	0	0	0
T49	0	63	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	79	0	0
T72	0	43	0	0
T74	0	14	0	0
T75	0	62	0	0
T89	0	55	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4800	0	0
T2	762504	55	0	0
T3	141079	120	0	0
T6	82378	0	0	0
T7	151100	66	0	0
T35	0	32	0	0
T44	140071	0	0	0
T49	0	56	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	72	0	0
T72	0	42	0	0
T74	0	25	0	0
T75	0	66	0	0
T89	0	53	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4963	0	0
T2	762504	79	0	0
T3	141079	106	0	0
T6	82378	0	0	0
T7	151100	58	0	0
T35	0	31	0	0
T44	140071	0	0	0
T49	0	70	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	91	0	0
T72	0	46	0	0
T74	0	15	0	0
T75	0	80	0	0
T89	0	44	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4860	0	0
T2	762504	59	0	0
T3	141079	102	0	0
T6	82378	0	0	0
T7	151100	68	0	0
T35	0	27	0	0
T44	140071	0	0	0
T49	0	60	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	68	0	0
T72	0	15	0	0
T74	0	16	0	0
T75	0	45	0	0
T89	0	48	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4748	0	0
T2	762504	75	0	0
T3	141079	82	0	0
T6	82378	0	0	0
T7	151100	77	0	0
T35	0	33	0	0
T44	140071	0	0	0
T49	0	50	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	76	0	0
T72	0	44	0	0
T74	0	26	0	0
T75	0	54	0	0
T89	0	55	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4650	0	0
T2	762504	74	0	0
T3	141079	109	0	0
T6	82378	0	0	0
T7	151100	69	0	0
T35	0	19	0	0
T44	140071	0	0	0
T49	0	75	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	81	0	0
T72	0	28	0	0
T74	0	23	0	0
T75	0	55	0	0
T89	0	56	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4965	0	0
T2	762504	82	0	0
T3	141079	81	0	0
T6	82378	0	0	0
T7	151100	79	0	0
T35	0	44	0	0
T44	140071	0	0	0
T49	0	80	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T71	0	87	0	0
T72	0	28	0	0
T74	0	27	0	0
T75	0	63	0	0
T89	0	53	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	2878	0	0
T2	762504	23	0	0
T3	141079	40	0	0
T6	82378	0	0	0
T7	151100	27	0	0
T35	0	10	0	0
T44	140071	0	0	0
T49	0	29	0	0
T50	121254	0	0	0
T51	261389	0	0	0
T52	50916	0	0	0
T53	53091	0	0	0
T55	40560	0	0	0
T59	0	1	0	0
T71	0	15	0	0
T72	0	17	0	0
T74	0	6	0	0
T132	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	2737	0	0
T87	0	26	0	0
T118	486023	28	0	0
T131	0	8	0	0
T147	0	10	0	0
T149	0	28	0	0
T170	0	22	0	0
T184	267884	0	0	0
T198	0	9	0	0
T219	13959	0	0	0
T220	333942	0	0	0
T221	165013	0	0	0
T222	129683	0	0	0
T223	202535	0	0	0
T232	0	23	0	0
T263	0	87	0	0
T299	26637	0	0	0
T300	135345	0	0	0
T301	254734	0	0	0
T302	0	17	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	3710	0	0
T39	35565	2	0	0
T40	245393	0	0	0
T74	826092	0	0	0
T75	441083	0	0	0
T87	0	23	0	0
T105	57541	0	0	0
T106	55431	0	0	0
T107	207068	0	0	0
T118	0	40	0	0
T131	0	6	0	0
T147	0	10	0	0
T154	0	4	0	0
T170	0	52	0	0
T178	0	1	0	0
T192	0	2	0	0
T263	0	15	0	0
T303	211232	0	0	0
T304	607538	0	0	0
T305	212958	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	1804	0	0
T87	0	10	0	0
T99	0	11	0	0
T118	486023	31	0	0
T147	0	8	0	0
T149	0	30	0	0
T170	0	22	0	0
T184	267884	0	0	0
T198	0	22	0	0
T219	13959	0	0	0
T220	333942	0	0	0
T221	165013	0	0	0
T222	129683	0	0	0
T223	202535	0	0	0
T263	0	10	0	0
T298	0	44	0	0
T299	26637	0	0	0
T300	135345	0	0	0
T301	254734	0	0	0
T302	0	4	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	5091	0	0
T9	976617	0	0	0
T10	177628	0	0	0
T25	695771	54	0	0
T28	60916	0	0	0
T45	315487	0	0	0
T46	81432	0	0	0
T47	85761	0	0	0
T56	22687	0	0	0
T65	0	51	0	0
T68	202572	0	0	0
T69	53187	0	0	0
T77	0	42	0	0
T87	0	28	0	0
T118	0	38	0	0
T170	0	86	0	0
T217	0	57	0	0
T306	0	58	0	0
T307	0	98	0	0
T308	0	15	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	5638	0	0
T4	145797	63	0	0
T5	103759	0	0	0
T13	200292	0	0	0
T14	251194	0	0	0
T15	50795	0	0	0
T16	65926	0	0	0
T17	94000	0	0	0
T18	458713	0	0	0
T19	91237	0	0	0
T25	0	164	0	0
T43	92128	0	0	0
T69	0	57	0	0
T87	0	19	0	0
T118	0	40	0	0
T170	0	165	0	0
T240	0	51	0	0
T309	0	26	0	0
T310	0	51	0	0
T311	0	67	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4330	0	0
T4	145797	57	0	0
T5	103759	0	0	0
T13	200292	0	0	0
T14	251194	0	0	0
T15	50795	0	0	0
T16	65926	0	0	0
T17	94000	0	0	0
T18	458713	0	0	0
T19	91237	0	0	0
T25	0	139	0	0
T43	92128	0	0	0
T69	0	77	0	0
T87	0	23	0	0
T118	0	48	0	0
T170	0	173	0	0
T240	0	73	0	0
T309	0	49	0	0
T310	0	45	0	0
T311	0	45	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	4688	0	0
T4	145797	52	0	0
T5	103759	0	0	0
T13	200292	0	0	0
T14	251194	0	0	0
T15	50795	0	0	0
T16	65926	0	0	0
T17	94000	0	0	0
T18	458713	0	0	0
T19	91237	0	0	0
T25	0	159	0	0
T43	92128	0	0	0
T69	0	77	0	0
T87	0	17	0	0
T118	0	58	0	0
T170	0	169	0	0
T240	0	67	0	0
T309	0	61	0	0
T310	0	53	0	0
T311	0	78	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	2309	0	0
T87	0	22	0	0
T118	486023	40	0	0
T131	0	11	0	0
T147	0	15	0	0
T149	0	21	0	0
T170	0	32	0	0
T184	267884	0	0	0
T198	0	16	0	0
T219	13959	0	0	0
T220	333942	0	0	0
T221	165013	0	0	0
T222	129683	0	0	0
T223	202535	0	0	0
T263	0	11	0	0
T298	0	42	0	0
T299	26637	0	0	0
T300	135345	0	0	0
T301	254734	0	0	0
T302	0	4	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	1904	0	0
T24	125492	12	0	0
T34	189389	0	0	0
T48	197483	0	0	0
T58	104045	0	0	0
T59	0	2	0	0
T63	211630	0	0	0
T87	0	22	0	0
T118	0	51	0	0
T120	0	12	0	0
T131	0	14	0	0
T137	285202	0	0	0
T138	51043	0	0	0
T139	315279	0	0	0
T140	15548	0	0	0
T141	163010	0	0	0
T170	0	37	0	0
T263	0	1	0	0
T312	0	2	0	0
T313	0	4	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	1878	0	0
T27	161485	0	0	0
T33	109636	0	0	0
T59	142338	4	0	0
T64	234906	0	0	0
T87	0	25	0	0
T118	0	42	0	0
T120	0	4	0	0
T124	429310	0	0	0
T126	0	5	0	0
T132	411329	0	0	0
T133	180780	0	0	0
T147	0	19	0	0
T170	0	29	0	0
T263	0	5	0	0
T312	0	3	0	0
T314	0	9	0	0
T315	63252	0	0	0
T316	206923	0	0	0
T317	329311	0	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	1949	0	0
T24	125492	5	0	0
T34	189389	0	0	0
T48	197483	0	0	0
T58	104045	0	0	0
T59	0	9	0	0
T63	211630	0	0	0
T87	0	21	0	0
T118	0	46	0	0
T120	0	4	0	0
T131	0	16	0	0
T137	285202	0	0	0
T138	51043	0	0	0
T139	315279	0	0	0
T140	15548	0	0	0
T141	163010	0	0	0
T170	0	38	0	0
T263	0	4	0	0
T312	0	4	0	0
T313	0	1	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161874828	1939	0	0
T24	125492	9	0	0
T34	189389	0	0	0
T48	197483	0	0	0
T58	104045	0	0	0
T63	211630	0	0	0
T77	0	4	0	0
T87	0	23	0	0
T118	0	44	0	0
T120	0	10	0	0
T131	0	12	0	0
T137	285202	0	0	0
T138	51043	0	0	0
T139	315279	0	0	0
T140	15548	0	0	0
T141	163010	0	0	0
T170	0	32	0	0
T263	0	9	0	0
T312	0	4	0	0
T313	0	4	0	0