07b417ef03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 6.300s | 2.113ms | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 7.980s | 2.482ms | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 5.750s | 2.408ms | 5 | 5 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 2.310s | 2.567ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 12.700s | 6.017ms | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 6.140s | 2.067ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 5.461m | 75.804ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 11.770s | 3.008ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 6.280s | 2.060ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 6.140s | 2.067ms | 20 | 20 | 100.00 |
| sysrst_ctrl_csr_aliasing | 11.770s | 3.008ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 165 | 165 | 100.00 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 8.968m | 219.414ms | 49 | 50 | 98.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 8.960m | 208.944ms | 92 | 100 | 92.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 12.508m | 304.276ms | 50 | 50 | 100.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 3.664m | 239.066ms | 50 | 50 | 100.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 7.530s | 2.512ms | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 6.490s | 2.194ms | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 14.020m | 643.423ms | 50 | 50 | 100.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 7.810s | 2.611ms | 50 | 50 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 16.427m | 3.420s | 48 | 50 | 96.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 42.450s | 35.197ms | 2 | 2 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 10.326m | 225.625ms | 47 | 50 | 94.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 6.000s | 2.014ms | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 6.120s | 2.015ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 7.590s | 2.142ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 7.590s | 2.142ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 12.700s | 6.017ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 6.140s | 2.067ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 11.770s | 3.008ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 42.980s | 10.039ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 12.700s | 6.017ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 6.140s | 2.067ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 11.770s | 3.008ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 42.980s | 10.039ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 678 | 692 | 97.98 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 54.700s | 22.012ms | 5 | 5 | 100.00 |
| sysrst_ctrl_tl_intg_err | 1.985m | 42.473ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 1.985m | 42.473ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 4.768m | 607.618ms | 43 | 50 | 86.00 |
| V3 | TOTAL | 43 | 50 | 86.00 | |||
| TOTAL | 911 | 932 | 97.75 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 15 | 15 | 11 | 73.33 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.78 | 99.29 | 96.78 | 100.00 | 96.79 | 98.71 | 99.52 | 93.40 |
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 6 failures:
Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.
9.sysrst_ctrl_stress_all_with_rand_reset.41864469320450426245309100087214251424825637721340632669708441380700592125288
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9302281478 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 9594781478 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 9594781478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.sysrst_ctrl_stress_all_with_rand_reset.62090485710426888547040025035751286173311955657710326027660457244844621124149
Line 716, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 621624665477 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 623732165477 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 623732165477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_ultra_low_pwr has 2 failures.
11.sysrst_ctrl_ultra_low_pwr.21622314049995879922686646824279154694025968205400763498753694611836109235307
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 4788817163 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 5171317163 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 8916317163 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 11306317163 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 11318426195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
35.sysrst_ctrl_ultra_low_pwr.111156760407771632733066234817783555157970513541027661514084054878939824071703
Line 560, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 6776229781 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 6903729781 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 8603729781 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 8643817234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_stress_all has 2 failures.
17.sysrst_ctrl_stress_all.58946260775153219814637178699331105983385751971984708375927336437142344113217
Line 568, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 9977303083 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 11824803083 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 11824803083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.sysrst_ctrl_stress_all.57887881896079615503876020630243406689587636552942616223933014801229123127703
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 4168549518 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 4691049518 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4691049518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 2 failures:
7.sysrst_ctrl_stress_all_with_rand_reset.8506337123867501754995986552217490088427239324846692557387061425861652163305
Line 565, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7067088443 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 7068011125 ps: (cip_base_vseq.sv:767) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Stress w/ reset is done for run 1/10
UVM_INFO @ 7068506651 ps: (dv_base_reg.sv:332) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds 1 val
UVM_INFO @ 7071166373 ps: (cip_base_vseq.sv:712) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 2/10
23.sysrst_ctrl_stress_all_with_rand_reset.5265762507176721825877959141885178958334597844925978785153841149236046399371
Line 613, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20388369781 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 20388369781 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
UVM_INFO @ 20388369781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 2 failures:
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
29.sysrst_ctrl_stress_all_with_rand_reset.33492177977173862416954634733992039155371026049472210227363969025159480198090
Line 590, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 15840770998 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 15840770998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_stress_all has 1 failures.
44.sysrst_ctrl_stress_all.75530619848807587578115648405585555789027226739942173098191884458351817349207
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest/run.log
UVM_FATAL @ 4333218322 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 4333218322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 2 failures:
57.sysrst_ctrl_combo_detect_with_pre_cond.35426000942565475704378874937408178762298792761533714588391891886602224342247
Line 593, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 41973085828 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 42228195928 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8])
UVM_INFO @ 42228195928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
84.sysrst_ctrl_combo_detect_with_pre_cond.28835662786655595862385153613407154963368457148862732649822508557856178532630
Line 600, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 86476631682 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 87166701321 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8])
UVM_INFO @ 87166701321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:115) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (* [*] vs * [*]) has 1 failures:
11.sysrst_ctrl_stress_all_with_rand_reset.20060855893251345304751931282748909897518804377348519606070430429263082878947
Line 647, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 40162879756 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 40166688428 ps: (cip_base_vseq.sv:767) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Stress w/ reset is done for run 4/5
UVM_INFO @ 40173375443 ps: (dv_base_reg.sv:332) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds 1 val
UVM_INFO @ 40178083814 ps: (cip_base_vseq.sv:712) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 5/5
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_combo_detect_vseq] time out waiting for ec_rst == * has 1 failures:
19.sysrst_ctrl_combo_detect.66177883741980319428795825993648643169287443092111030293054440774227420430956
Line 567, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest/run.log
UVM_FATAL @ 28727750434 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 28727750434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (* [*] vs * [*]) has 1 failures:
31.sysrst_ctrl_combo_detect_with_pre_cond.60051388589512275692935631218329967378345782403530068189726539026072366369100
Line 572, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 14395319528 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (2 [0x2] vs 6 [0x6])
UVM_INFO @ 24508945778 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2c
UVM_INFO @ 24509127596 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32
UVM_INFO @ 25135099146 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
UVM_INFO @ 25135099146 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:
38.sysrst_ctrl_stress_all_with_rand_reset.50865508131218969081517287962378970598870681547466354076927777157035590582308
Line 595, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18129125060 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 18129125060 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
UVM_INFO @ 18129125060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-* has 1 failures:
50.sysrst_ctrl_combo_detect_with_pre_cond.23161908509949720387792234017184931166839137720917775034334198462319436090818
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 13278398534 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-4
UVM_ERROR @ 13278398534 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(3) +/-4
UVM_INFO @ 13278398534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == *) Unexpected H2L transition of ec_rst_l_o has 1 failures:
64.sysrst_ctrl_combo_detect_with_pre_cond.14095420303299031064353062455312948329842922727136727263515983046678537660408
Line 590, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 36040083222 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o
UVM_INFO @ 36130083222 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :0
UVM_INFO @ 36130083222 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :2
UVM_ERROR @ 36130083222 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 36130083222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:
73.sysrst_ctrl_combo_detect_with_pre_cond.25034899596010008351470946119142245841147767021298963326957180189025994755268
Line 643, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 89429177110 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 89539177110 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 89559177110 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 99722336449 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d
UVM_INFO @ 99722583202 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xf
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:
83.sysrst_ctrl_combo_detect_with_pre_cond.64362250514706091847521379481091484989079819822019946871820901263258654043083
Line 586, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 69327028371 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 80081885146 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x89
UVM_INFO @ 80082048410 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x10
UVM_INFO @ 81197028371 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
UVM_INFO @ 81197774178 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o has 1 failures:
96.sysrst_ctrl_combo_detect_with_pre_cond.55211274645656301374398783213269391129963573255753461600052250808147500296777
Line 619, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 52909916332 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == 1) Unexpected L2H transition of ec_rst_l_o
UVM_INFO @ 52944916332 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 52964916332 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_ERROR @ 53030119056 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (4 [0x4] vs 12 [0xc])
UVM_INFO @ 53030119056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]