| | | | | | |
| tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 1535643129 | 2554851 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 1535642565 | 7286 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 1535643129 | 18072740 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 1535643129 | 191503 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 1535642565 | 7820 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 1535643129 | 20436162 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 1535643129 | 623215 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 1535643129 | 20436162 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 1535643129 | 623215 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 1535643129 | 623215 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 1535643129 | 623215 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 1535642565 | 4509 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 1535642565 | 4012 | 0 | 0 |
|
| tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.u_reg.en2addrHit
| 0 | 0 | 1535642565 | 267982 | 0 | 0 |
|
| tb.dut.u_reg.reAfterRv
| 0 | 0 | 1535642565 | 267981 | 0 | 0 |
|
| tb.dut.u_reg.rePulse
| 0 | 0 | 1535642565 | 140235 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1319904 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1380 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1380 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1380 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1294 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1390 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1195787 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1231 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1231 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1231 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1145 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1240 | 0 | 0 |
|
| tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1835244 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1978 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1978 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1978 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1893 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1984 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1793718 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1928 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1928 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1928 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1845 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1937 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1803796 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1952 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1952 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1952 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1870 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1960 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1778857 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1932 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1932 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1932 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1851 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1943 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1829688 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1974 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1974 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1974 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1891 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1984 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1796864 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1962 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1962 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1962 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1878 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1972 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1796810 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1953 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1953 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1953 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1867 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1961 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1806431 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1968 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1968 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1968 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1885 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1977 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1290883 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1323 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1323 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1323 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1239 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1332 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1280555 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1314 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1314 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1314 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1230 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1323 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1235988 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1280 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1280 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1280 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1196 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1289 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1279805 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1333 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1333 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1333 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1246 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1341 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 6501105 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 6928 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 6928 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 6928 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 6843 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 6938 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 6522438 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 6933 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 6933 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 6933 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 6847 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 6941 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 6312996 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 6801 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 6801 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 6801 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 6722 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 6809 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 6548135 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 7053 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 7053 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 7053 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 6969 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 7061 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 7119808 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 7609 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 7609 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 7609 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 7526 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 7618 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 7056978 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 7513 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 7513 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 7513 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 7426 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 7520 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 6866518 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 7424 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 7424 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 7424 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 7338 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 7433 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 7112186 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 7663 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 7663 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 7663 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 7576 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 7670 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1917285 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 2110 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 2110 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 2110 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 2024 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 2119 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1062812 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1098 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1098 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1098 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1015 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1107 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1902072 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 2081 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 2081 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 2081 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 2002 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 2089 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 2985306 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 3017 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 3017 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 3017 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 2937 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 3025 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 5782423 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 6803 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 6803 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 6803 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 6718 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 6814 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 6957920 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 8025 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 8025 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 8025 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 7942 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 8037 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 5764148 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 6732 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 6732 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 6732 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 6644 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 6744 | 0 | 0 |
|
| tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 908 | 908 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1042739 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1073 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1073 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1073 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 989 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1082 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1046186 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1053 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1053 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1053 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 972 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1063 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1060526 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1083 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1083 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1083 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1000 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1091 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1055125 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1077 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1535642565 | 1077 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 8555646 | 1077 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 994 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1085 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.BusySrcReqChk_A
| 0 | 0 | 1535642565 | 1099792 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.DstReqKnown_A
| 0 | 0 | 8555646 | 7695950 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.SrcAckBusyChk_A
| 0 | 0 | 1535642565 | 1227 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.SrcBusyKnown_A
| 0 | 0 | 1535642565 | 1535176145 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 8555646 | 839 | 0 | 907 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 8555646 | 839 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 1535642565 | 2066 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 8555646 | 1100 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 8555646 | 1140 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1535642565 | 1236 | 0 | 0 |
|
| tb.dut.u_reg.wePulse
| 0 | 0 | 1535642565 | 127746 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntClr_A
| 0 | 0 | 8299801 | 260 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntIncr_A
| 0 | 0 | 8299801 | 245578 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntNoWrap_A
| 0 | 0 | 8299801 | 7623404 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectStDropOut_A
| 0 | 0 | 8299801 | 2 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectedOut_A
| 0 | 0 | 8299801 | 886 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectedPulseOut_A
| 0 | 0 | 8299801 | 118 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DisabledIdleSt_A
| 0 | 0 | 8299801 | 7371982 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DisabledNoDetection_A
| 0 | 0 | 8299801 | 7374405 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.EnterDebounceSt_A
| 0 | 0 | 8299801 | 143 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.EnterDetectSt_A
| 0 | 0 | 8299801 | 120 | 0 | 0 |
|