Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T14,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T14,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T46
0	1	Covered	T102,T103
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T46
0	1	Covered	T1,T14,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T14,T46
1	-	Covered	T1,T14,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T26
DetectSt	168	Covered	T1,T14,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T14,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T46
DebounceSt->IdleSt	163	Covered	T26,T49,T71
DetectSt->IdleSt	186	Covered	T102,T103
DetectSt->StableSt	191	Covered	T1,T14,T46
IdleSt->DebounceSt	148	Covered	T1,T14,T26
StableSt->IdleSt	206	Covered	T1,T14,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T14,T26
0	1	Covered	T1,T14,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T128,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T26
DetectSt	-	-	-	-	1	-	-	Covered	T102,T103
DetectSt	-	-	-	-	0	1	-	Covered	T1,T14,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T14,T46
StableSt	-	-	-	-	-	-	0	Covered	T1,T14,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	260	0	0
CntIncr_A	8299801	245578	0	0
CntNoWrap_A	8299801	7623404	0	0
DetectStDropOut_A	8299801	2	0	0
DetectedOut_A	8299801	886	0	0
DetectedPulseOut_A	8299801	118	0	0
DisabledIdleSt_A	8299801	7371982	0	0
DisabledNoDetection_A	8299801	7374405	0	0
EnterDebounceSt_A	8299801	143	0	0
EnterDetectSt_A	8299801	120	0	0
EnterStableSt_A	8299801	118	0	0
PulseIsPulse_A	8299801	118	0	0
StayInStableSt	8299801	768	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8299801	6937	0	0
gen_low_level_sva.LowLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	118	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	260	0	0
T1	132641	6	0	0
T2	28822	0	0	0
T14	632	4	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	1	0	0
T46	0	2	0	0
T48	0	4	0	0
T49	0	3	0	0
T53	0	2	0	0
T87	0	2	0	0
T88	0	2	0	0
T89	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	245578	0	0
T1	132641	198	0	0
T2	28822	0	0	0
T14	632	98	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	10	0	0
T46	0	14	0	0
T48	0	119	0	0
T49	0	77	0	0
T53	0	45	0	0
T87	0	77	0	0
T88	0	43	0	0
T89	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623404	0	0
T1	132641	128127	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	227	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2	0	0
T102	14521	1	0	0
T103	0	1	0	0
T109	11335	0	0	0
T110	522	0	0	0
T111	425	0	0	0
T112	748	0	0	0
T113	1068	0	0	0
T114	16141	0	0	0
T115	443	0	0	0
T116	2286	0	0	0
T117	46639	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	886	0	0
T1	132641	33	0	0
T2	28822	0	0	0
T14	632	19	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T46	0	5	0	0
T48	0	11	0	0
T49	0	5	0	0
T53	0	3	0	0
T87	0	6	0	0
T88	0	10	0	0
T89	0	7	0	0
T121	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	118	0	0
T1	132641	3	0	0
T2	28822	0	0	0
T14	632	2	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T53	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T121	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7371982	0	0
T1	132641	127800	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	47	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7374405	0	0
T1	132641	127811	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	48	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	143	0	0
T1	132641	3	0	0
T2	28822	0	0	0
T14	632	2	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T53	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	120	0	0
T1	132641	3	0	0
T2	28822	0	0	0
T14	632	2	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T53	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	118	0	0
T1	132641	3	0	0
T2	28822	0	0	0
T14	632	2	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T53	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T121	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	118	0	0
T1	132641	3	0	0
T2	28822	0	0	0
T14	632	2	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T53	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T121	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	768	0	0
T1	132641	30	0	0
T2	28822	0	0	0
T14	632	17	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T46	0	4	0	0
T48	0	9	0	0
T49	0	4	0	0
T53	0	2	0	0
T87	0	5	0	0
T88	0	9	0	0
T89	0	6	0	0
T121	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	6937	0	0
T1	132641	22	0	0
T2	28822	10	0	0
T4	522	7	0	0
T5	8262	28	0	0
T6	444	5	0	0
T14	632	3	0	0
T15	426	4	0	0
T16	526	5	0	0
T17	504	7	0	0
T22	527	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	118	0	0
T1	132641	3	0	0
T2	28822	0	0	0
T14	632	2	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T53	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T26,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T26,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T26,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T26,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T12
0	1	Covered	T72,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T12
0	1	Unreachable
1	0	Covered	T1,T3,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T26,T3
DetectSt	168	Covered	T1,T3,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T12
DebounceSt->IdleSt	163	Covered	T26,T13,T72
DetectSt->IdleSt	186	Covered	T72,T84,T85
DetectSt->StableSt	191	Covered	T1,T3,T12
IdleSt->DebounceSt	148	Covered	T1,T26,T3
StableSt->IdleSt	206	Covered	T1,T3,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T26,T3
0	1	Covered	T1,T26,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T26,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T72,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T26,T3
DetectSt	-	-	-	-	1	-	-	Covered	T72,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	190	0	0
CntIncr_A	8299801	24078	0	0
CntNoWrap_A	8299801	7623474	0	0
DetectStDropOut_A	8299801	20	0	0
DetectedOut_A	8299801	37239	0	0
DetectedPulseOut_A	8299801	47	0	0
DisabledIdleSt_A	8299801	5905558	0	0
DisabledNoDetection_A	8299801	5908028	0	0
EnterDebounceSt_A	8299801	123	0	0
EnterDetectSt_A	8299801	67	0	0
EnterStableSt_A	8299801	47	0	0
PulseIsPulse_A	8299801	47	0	0
StayInStableSt	8299801	37192	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8299801	6937	0	0
gen_low_level_sva.LowLevelEvent_A	8299801	7626136	0	0
gen_sticky_sva.StableStDropOut_A	8299801	1004729	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	190	0	0
T1	132641	2	0	0
T2	28822	0	0	0
T3	0	2	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	2	0	0
T58	0	4	0	0
T71	0	2	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	24078	0	0
T1	132641	33	0	0
T2	28822	0	0	0
T3	0	92	0	0
T12	0	82	0	0
T13	0	500	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	53	0	0
T58	0	80	0	0
T71	0	30	0	0
T72	0	124	0	0
T73	0	52	0	0
T74	0	284	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623474	0	0
T1	132641	128131	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	20	0	0
T33	7622	0	0	0
T39	94785	0	0	0
T53	649	0	0	0
T63	494	0	0	0
T72	626	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	33077	0	0	0
T103	0	3	0	0
T130	0	5	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	2	0	0
T134	0	4	0	0
T135	819	0	0	0
T136	526	0	0	0
T137	94455	0	0	0
T138	449	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	37239	0	0
T1	132641	132	0	0
T2	28822	0	0	0
T3	0	509	0	0
T12	0	186	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	430	0	0
T73	0	135	0	0
T85	0	1	0	0
T124	0	97	0	0
T125	0	267	0	0
T126	0	376	0	0
T127	0	380	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	47	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	2	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T73	0	1	0	0
T85	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	2	0	0
T127	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	5905558	0	0
T1	132641	127753	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	5908028	0	0
T1	132641	127765	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	123	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	2	0	0
T13	0	5	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	2	0	0
T58	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	67	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	2	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T84	0	2	0	0
T85	0	2	0	0
T124	0	1	0	0
T125	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	47	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	2	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T73	0	1	0	0
T85	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	2	0	0
T127	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	47	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	2	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T73	0	1	0	0
T85	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	2	0	0
T127	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	37192	0	0
T1	132641	131	0	0
T2	28822	0	0	0
T3	0	508	0	0
T12	0	184	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	428	0	0
T73	0	134	0	0
T124	0	96	0	0
T125	0	266	0	0
T126	0	374	0	0
T127	0	378	0	0
T139	0	112	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	6937	0	0
T1	132641	22	0	0
T2	28822	10	0	0
T4	522	7	0	0
T5	8262	28	0	0
T6	444	5	0	0
T14	632	3	0	0
T15	426	4	0	0
T16	526	5	0	0
T17	504	7	0	0
T22	527	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1004729	0	0
T1	132641	191	0	0
T2	28822	0	0	0
T3	0	73099	0	0
T12	0	215758	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	259	0	0
T73	0	84	0	0
T85	0	39	0	0
T124	0	645	0	0
T125	0	35	0	0
T126	0	192	0	0
T127	0	120	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T22

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T22
1	1	Covered	T4,T6,T22

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T26,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T26,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T26,T3
1	0	Covered	T4,T6,T22
1	1	Covered	T1,T26,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T12
0	1	Covered	T58,T72,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T12
0	1	Unreachable
1	0	Covered	T1,T3,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T26,T3
DetectSt	168	Covered	T1,T3,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T12
DebounceSt->IdleSt	163	Covered	T26,T58,T72
DetectSt->IdleSt	186	Covered	T58,T72,T83
DetectSt->StableSt	191	Covered	T1,T3,T12
IdleSt->DebounceSt	148	Covered	T1,T26,T3
StableSt->IdleSt	206	Covered	T1,T3,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T26,T3
0	1	Covered	T1,T26,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T26,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T58,T72,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T26,T3
DetectSt	-	-	-	-	1	-	-	Covered	T58,T72,T83
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	166	0	0
CntIncr_A	8299801	158365	0	0
CntNoWrap_A	8299801	7623498	0	0
DetectStDropOut_A	8299801	8	0	0
DetectedOut_A	8299801	719541	0	0
DetectedPulseOut_A	8299801	65	0	0
DisabledIdleSt_A	8299801	5905558	0	0
DisabledNoDetection_A	8299801	5908028	0	0
EnterDebounceSt_A	8299801	93	0	0
EnterDetectSt_A	8299801	73	0	0
EnterStableSt_A	8299801	65	0	0
PulseIsPulse_A	8299801	65	0	0
StayInStableSt	8299801	719476	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_sticky_sva.StableStDropOut_A	8299801	837120	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	166	0	0
T1	132641	2	0	0
T2	28822	0	0	0
T3	0	2	0	0
T12	0	4	0	0
T13	0	2	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	2	0	0
T58	0	11	0	0
T71	0	2	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	158365	0	0
T1	132641	12	0	0
T2	28822	0	0	0
T3	0	18400	0	0
T12	0	94	0	0
T13	0	22	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	53	0	0
T58	0	504	0	0
T71	0	30	0	0
T72	0	74	0	0
T73	0	43	0	0
T74	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623498	0	0
T1	132641	128131	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	8	0	0
T35	22972	0	0	0
T42	563	0	0	0
T51	642	0	0	0
T52	5468	0	0	0
T58	1262	3	0	0
T62	493	0	0	0
T72	0	1	0	0
T83	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	417	0	0	0
T143	504	0	0	0
T144	925	0	0	0
T145	534	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	719541	0	0
T1	132641	41	0	0
T2	28822	0	0	0
T3	0	55205	0	0
T12	0	217	0	0
T13	0	132	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	86	0	0
T73	0	111	0	0
T74	0	116	0	0
T84	0	47	0	0
T85	0	30	0	0
T124	0	594	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	65	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	2	0	0
T13	0	1	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T124	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	5905558	0	0
T1	132641	127753	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	5908028	0	0
T1	132641	127765	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	93	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	2	0	0
T13	0	1	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	2	0	0
T58	0	6	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	73	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	2	0	0
T13	0	1	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	5	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	2	0	0
T124	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	65	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	2	0	0
T13	0	1	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T124	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	65	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	2	0	0
T13	0	1	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T124	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	719476	0	0
T1	132641	40	0	0
T2	28822	0	0	0
T3	0	55204	0	0
T12	0	215	0	0
T13	0	131	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	84	0	0
T73	0	110	0	0
T74	0	115	0	0
T84	0	45	0	0
T85	0	29	0	0
T124	0	593	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	837120	0	0
T1	132641	310	0	0
T2	28822	0	0	0
T3	0	84	0	0
T12	0	215703	0	0
T13	0	408	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	82	0	0
T73	0	115	0	0
T74	0	358	0	0
T84	0	171	0	0
T85	0	94	0	0
T124	0	93	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T26,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T26,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T26,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T26,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T12
0	1	Covered	T3,T12,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T12
0	1	Unreachable
1	0	Covered	T1,T3,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T26,T3
DetectSt	168	Covered	T1,T3,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T12
DebounceSt->IdleSt	163	Covered	T26,T12,T72
DetectSt->IdleSt	186	Covered	T3,T12,T81
DetectSt->StableSt	191	Covered	T1,T3,T12
IdleSt->DebounceSt	148	Covered	T1,T26,T3
StableSt->IdleSt	206	Covered	T1,T3,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T26,T3
0	1	Covered	T1,T26,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T26,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T72,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T26,T3
DetectSt	-	-	-	-	1	-	-	Covered	T3,T12,T81
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	182	0	0
CntIncr_A	8299801	284827	0	0
CntNoWrap_A	8299801	7623482	0	0
DetectStDropOut_A	8299801	14	0	0
DetectedOut_A	8299801	510969	0	0
DetectedPulseOut_A	8299801	53	0	0
DisabledIdleSt_A	8299801	5905558	0	0
DisabledNoDetection_A	8299801	5908028	0	0
EnterDebounceSt_A	8299801	115	0	0
EnterDetectSt_A	8299801	67	0	0
EnterStableSt_A	8299801	53	0	0
PulseIsPulse_A	8299801	53	0	0
StayInStableSt	8299801	510916	0	0
gen_high_event_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_sticky_sva.StableStDropOut_A	8299801	411429	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	182	0	0
T1	132641	2	0	0
T2	28822	0	0	0
T3	0	8	0	0
T12	0	7	0	0
T13	0	2	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	2	0	0
T58	0	4	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	3	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	284827	0	0
T1	132641	67	0	0
T2	28822	0	0	0
T3	0	92	0	0
T12	0	215968	0	0
T13	0	35	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	56	0	0
T58	0	54	0	0
T71	0	34	0	0
T72	0	122	0	0
T73	0	165	0	0
T74	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623482	0	0
T1	132641	128131	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	14	0	0
T3	166236	3	0	0
T7	623	0	0	0
T12	0	2	0	0
T28	492	0	0	0
T29	523	0	0	0
T30	5466	0	0	0
T46	710	0	0	0
T47	4770	0	0	0
T56	507	0	0	0
T77	0	1	0	0
T81	0	2	0	0
T103	0	1	0	0
T122	501	0	0	0
T123	505	0	0	0
T134	0	3	0	0
T146	0	1	0	0
T147	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	510969	0	0
T1	132641	258	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	1	0	0
T13	0	154	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	197	0	0
T74	0	167	0	0
T84	0	129	0	0
T85	0	84	0	0
T124	0	236	0	0
T125	0	114	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	53	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T74	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	5905558	0	0
T1	132641	127753	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	5908028	0	0
T1	132641	127765	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	115	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	4	0	0
T12	0	4	0	0
T13	0	1	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	0	2	0	0
T58	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	3	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	67	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	4	0	0
T12	0	3	0	0
T13	0	1	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T74	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	53	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T74	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	53	0	0
T1	132641	1	0	0
T2	28822	0	0	0
T3	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	2	0	0
T74	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	510916	0	0
T1	132641	257	0	0
T2	28822	0	0	0
T13	0	153	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	195	0	0
T74	0	166	0	0
T84	0	127	0	0
T85	0	83	0	0
T124	0	235	0	0
T125	0	113	0	0
T126	0	428	0	0
T127	0	186	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	411429	0	0
T1	132641	49	0	0
T2	28822	0	0	0
T3	0	18417	0	0
T12	0	25	0	0
T13	0	393	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T58	0	539	0	0
T74	0	315	0	0
T84	0	70	0	0
T85	0	32	0	0
T124	0	501	0	0
T125	0	209	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T43,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T43,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T43,T42,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T7,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T43,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T42,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T42,T45
0	1	Covered	T41,T148,T149
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T42,T45
1	-	Covered	T41,T148,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T43,T42
DetectSt	168	Covered	T43,T42,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T43,T42,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T42,T45
DebounceSt->IdleSt	163	Covered	T26,T71,T150
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T43,T42,T45
IdleSt->DebounceSt	148	Covered	T26,T43,T42
StableSt->IdleSt	206	Covered	T41,T148,T149

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T43,T42
0	1	Covered	T26,T43,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T42,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T43,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T42,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T150,T151,T152
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T43,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T43,T42,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T148,T149
StableSt	-	-	-	-	-	-	0	Covered	T43,T42,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	85	0	0
CntIncr_A	8299801	67709	0	0
CntNoWrap_A	8299801	7623579	0	0
DetectStDropOut_A	8299801	0	0	0
DetectedOut_A	8299801	83565	0	0
DetectedPulseOut_A	8299801	40	0	0
DisabledIdleSt_A	8299801	7165957	0	0
DisabledNoDetection_A	8299801	7168361	0	0
EnterDebounceSt_A	8299801	45	0	0
EnterDetectSt_A	8299801	40	0	0
EnterStableSt_A	8299801	40	0	0
PulseIsPulse_A	8299801	40	0	0
StayInStableSt	8299801	83505	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	85	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T81	0	2	0	0
T148	0	2	0	0
T149	0	2	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	67709	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	19	0	0
T27	492	0	0	0
T30	5466	0	0	0
T41	0	11	0	0
T42	0	47	0	0
T43	0	16	0	0
T45	0	90	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	26	0	0
T81	0	96	0	0
T148	0	8822	0	0
T149	0	98	0	0
T153	0	55	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623579	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	83565	0	0
T34	12894	0	0	0
T35	22972	0	0	0
T41	0	6	0	0
T42	563	41	0	0
T43	483	40	0	0
T45	0	43	0	0
T50	466	0	0	0
T58	1262	0	0	0
T81	0	42	0	0
T142	417	0	0	0
T143	504	0	0	0
T144	925	0	0	0
T148	0	17892	0	0
T149	0	192	0	0
T153	0	148	0	0
T154	0	44	0	0
T155	0	188	0	0
T156	526	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	40	0	0
T34	12894	0	0	0
T35	22972	0	0	0
T41	0	1	0	0
T42	563	1	0	0
T43	483	1	0	0
T45	0	1	0	0
T50	466	0	0	0
T58	1262	0	0	0
T81	0	1	0	0
T142	417	0	0	0
T143	504	0	0	0
T144	925	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	526	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7165957	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7168361	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	45	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T81	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	40	0	0
T34	12894	0	0	0
T35	22972	0	0	0
T41	0	1	0	0
T42	563	1	0	0
T43	483	1	0	0
T45	0	1	0	0
T50	466	0	0	0
T58	1262	0	0	0
T81	0	1	0	0
T142	417	0	0	0
T143	504	0	0	0
T144	925	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	526	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	40	0	0
T34	12894	0	0	0
T35	22972	0	0	0
T41	0	1	0	0
T42	563	1	0	0
T43	483	1	0	0
T45	0	1	0	0
T50	466	0	0	0
T58	1262	0	0	0
T81	0	1	0	0
T142	417	0	0	0
T143	504	0	0	0
T144	925	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	526	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	40	0	0
T34	12894	0	0	0
T35	22972	0	0	0
T41	0	1	0	0
T42	563	1	0	0
T43	483	1	0	0
T45	0	1	0	0
T50	466	0	0	0
T58	1262	0	0	0
T81	0	1	0	0
T142	417	0	0	0
T143	504	0	0	0
T144	925	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	526	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	83505	0	0
T34	12894	0	0	0
T35	22972	0	0	0
T41	0	5	0	0
T42	563	39	0	0
T43	483	38	0	0
T45	0	41	0	0
T50	466	0	0	0
T58	1262	0	0	0
T81	0	40	0	0
T142	417	0	0	0
T143	504	0	0	0
T144	925	0	0	0
T148	0	17891	0	0
T149	0	191	0	0
T153	0	146	0	0
T154	0	43	0	0
T155	0	186	0	0
T156	526	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	20	0	0
T41	544	1	0	0
T73	990	0	0	0
T77	0	1	0	0
T88	719	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	503	0	0	0
T161	422	0	0	0
T162	444	0	0	0
T163	1318	0	0	0
T164	402	0	0	0
T165	559	0	0	0
T166	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T7,T8
1	0	Covered	T4,T6,T22
1	1	Covered	T26,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T43
0	1	Covered	T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T42
0	1	Covered	T8,T43,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T42
1	-	Covered	T8,T43,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T7,T8
DetectSt	168	Covered	T7,T8,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T8,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T43
DebounceSt->IdleSt	163	Covered	T26,T71,T167
DetectSt->IdleSt	186	Covered	T78
DetectSt->StableSt	191	Covered	T7,T8,T43
IdleSt->DebounceSt	148	Covered	T26,T7,T8
StableSt->IdleSt	206	Covered	T8,T43,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T7,T8
0	1	Covered	T26,T7,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T167,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T78
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T43,T42
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	121	0	0
CntIncr_A	8299801	81222	0	0
CntNoWrap_A	8299801	7623543	0	0
DetectStDropOut_A	8299801	1	0	0
DetectedOut_A	8299801	83171	0	0
DetectedPulseOut_A	8299801	57	0	0
DisabledIdleSt_A	8299801	7189208	0	0
DisabledNoDetection_A	8299801	7191631	0	0
EnterDebounceSt_A	8299801	64	0	0
EnterDetectSt_A	8299801	58	0	0
EnterStableSt_A	8299801	57	0	0
PulseIsPulse_A	8299801	57	0	0
StayInStableSt	8299801	83091	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8299801	2775	0	0
gen_low_level_sva.LowLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	121	0	0
T3	166236	0	0	0
T7	623	2	0	0
T8	0	6	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T81	0	2	0	0
T148	0	4	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	81222	0	0
T3	166236	0	0	0
T7	623	85	0	0
T8	0	198	0	0
T26	6326	17	0	0
T27	492	0	0	0
T30	5466	0	0	0
T42	0	47	0	0
T43	0	16	0	0
T45	0	90	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	26	0	0
T81	0	96	0	0
T148	0	17644	0	0
T168	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623543	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1	0	0
T78	16369	1	0	0
T80	18255	0	0	0
T131	9392	0	0	0
T169	8549	0	0	0
T170	534	0	0	0
T171	503	0	0	0
T172	12515	0	0	0
T173	421	0	0	0
T174	2254	0	0	0
T175	736	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	83171	0	0
T7	623	128	0	0
T8	1017	87	0	0
T9	1034	0	0	0
T28	492	0	0	0
T29	523	0	0	0
T42	0	18	0	0
T43	0	1	0	0
T45	0	17	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	18	0	0
T122	501	0	0	0
T123	505	0	0	0
T148	0	22454	0	0
T154	0	126	0	0
T168	0	40	0	0
T176	0	77	0	0
T177	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	57	0	0
T7	623	1	0	0
T8	1017	3	0	0
T9	1034	0	0	0
T28	492	0	0	0
T29	523	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T122	501	0	0	0
T123	505	0	0	0
T148	0	2	0	0
T154	0	2	0	0
T168	0	1	0	0
T176	0	1	0	0
T177	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7189208	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7191631	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	64	0	0
T3	166236	0	0	0
T7	623	1	0	0
T8	0	3	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T81	0	1	0	0
T148	0	2	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	58	0	0
T7	623	1	0	0
T8	1017	3	0	0
T9	1034	0	0	0
T28	492	0	0	0
T29	523	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T122	501	0	0	0
T123	505	0	0	0
T148	0	2	0	0
T154	0	2	0	0
T168	0	1	0	0
T176	0	1	0	0
T177	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	57	0	0
T7	623	1	0	0
T8	1017	3	0	0
T9	1034	0	0	0
T28	492	0	0	0
T29	523	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T122	501	0	0	0
T123	505	0	0	0
T148	0	2	0	0
T154	0	2	0	0
T168	0	1	0	0
T176	0	1	0	0
T177	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	57	0	0
T7	623	1	0	0
T8	1017	3	0	0
T9	1034	0	0	0
T28	492	0	0	0
T29	523	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T122	501	0	0	0
T123	505	0	0	0
T148	0	2	0	0
T154	0	2	0	0
T168	0	1	0	0
T176	0	1	0	0
T177	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	83091	0	0
T7	623	126	0	0
T8	1017	83	0	0
T9	1034	0	0	0
T28	492	0	0	0
T29	523	0	0	0
T42	0	17	0	0
T45	0	16	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	17	0	0
T122	501	0	0	0
T123	505	0	0	0
T148	0	22451	0	0
T154	0	123	0	0
T155	0	39	0	0
T168	0	38	0	0
T176	0	75	0	0
T177	402	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2775	0	0
T1	132641	13	0	0
T2	28822	0	0	0
T4	522	6	0	0
T5	8262	0	0	0
T6	444	5	0	0
T14	632	0	0	0
T15	426	3	0	0
T16	526	5	0	0
T17	504	7	0	0
T19	0	11	0	0
T21	0	7	0	0
T22	527	6	0	0
T67	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	34	0	0
T8	1017	2	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T104	402	0	0	0
T129	0	1	0	0
T148	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0