Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1989

1

T5

15

T2

10

T20

15

auto[1]

657

1

T5

5

T2

5

T20

14

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2047

1

T5

20

T20

23

T32

3

auto[1]

599

1

T2

15

T20

6

T11

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2034

1

T5

15

T2

15

T20

27

auto[1]

612

1

T5

5

T20

2

T11

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2020

1

T5

20

T2

14

T20

18

auto[1]

626

1

T2

1

T20

11

T11

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2493

1

T5

20

T2

15

T20

29

auto[1]

153

1

T69

4

T92

6

T244

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2314

1

T5

20

T2

15

T20

29

auto[1]

332

1

T36

1

T69

1

T70

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2455

1

T5

15

T2

15

T20

29

auto[1]

191

1

T5

5

T36

4

T242

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2468

1

T5

20

T2

15

T20

29

auto[1]

178

1

T34

2

T70

4

T90

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2381

1

T5

10

T2

15

T20

29

auto[1]

265

1

T5

10

T36

1

T69

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2028

1

T5

20

T2

14

T20

23

auto[1]

618

1

T2

1

T20

6

T11

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	905	1			T2	15		T20	18		T11	7
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	38	1			T69	1		T348	1		T349	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	59	1			T70	8		T350	4		T351	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	15	1			T332	3		T352	1		T353	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	49	1			T34	2		T70	4		T243	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	14	1			T92	6		T328	1		T354	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	13	1			T342	1		T355	1		T223	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T172	2		T356	1		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	27	1			T36	4		T244	1		T329	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	24	1			T327	5		T333	2		T357	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T242	2		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	6	1			T244	1		T93	2		T358	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	14	1			T359	2		T195	2		T341	5
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T93	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	5	1			T359	1		T341	4		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	100	1			T70	6		T244	1		T241	9
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	10	1			T333	1		T360	1		T361	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	60	1			T36	1		T69	1		T245	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	3	1			T332	3		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	30	1			T241	7		T350	2		T333	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	6	1			T362	1		T350	2		T363	3
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	12	1			T90	3		T241	5		T364	4
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	61	1			T328	6		T327	4		T332	9
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T365	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T245	2		T366	1		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T246	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	4	1			T341	4		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

115

1

T20

12

T36

4

T244

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

109

1

T86

12

T93

1

T125

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

89

1

T248

5

T243

5

T328

15

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

106

1

T124

9

T244

2

T83

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

67

1

T245

2

T329

4

T367

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T328

6

T330

7

T210

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

48

1

T124

2

T328

15

T327

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

117

1

T36

1

T90

3

T245

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

73

1

T32

2

T120

3

T69

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T34

2

T119

5

T241

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T38

3

T333

1

T254

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T86

1

T70

6

T37

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T37

3

T368

3

T337

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T94

2

T326

4

T207

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

22

1

T241

9

T95

1

T369

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

138

1

T2

9

T70

4

T38

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

42

1

T2

5

T242

2

T95

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T20

4

T35

5

T248

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T11

3

T32

2

T66

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T35

7

T69

1

T37

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T244

1

T288

1

T370

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T2

1

T35

5

T124

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T11

1

T249

1

T129

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

46

1

T91

7

T367

2

T328

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T35

6

T70

4

T37

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T11

3

T70

4

T94

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T20

2

T329

2

T367

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

33

1

T120

2

T352

1

T98

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T119

1

T38

1

T350

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T253

1

T371

1

T337

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T372

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded