Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T22

8

T1

11

T16

10

auto[1]

1120

1

T22

12

T1

9

T16

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T22

5

T1

6

T16

3

from_0to1

525

1

T22

5

T1

6

T16

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T22

7

T1

9

T16

10

auto[1]

1122

1

T22

13

T1

11

T16

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1103

1

T22

14

T1

13

T16

9

auto[1]

1146

1

T22

6

T1

7

T16

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T22

1

T1

1

T16

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T21

1

T56

2

T122

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T1

1

T21

3

T122

2

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T22

1

T1

1

T16

1

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T1

2

T55

1

T122

2

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T21

2

T55

2

T56

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T22

1

T1

1

T16

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T22

1

T1

1

T21

1

auto[1]

from_1to0

auto[0]

auto[0]

88

1

T22

1

T1

1

T21

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T1

1

T19

1

T55

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T22

2

T16

1

T19

2

auto[1]

from_1to0

auto[1]

auto[1]

51

1

T1

1

T21

1

T56

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T22

1

T1

1

T16

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T17

2

T55

1

T122

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T22

1

T17

1

T56

2

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T22

1

T1

1

T16

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T22

10

T1

13

T16

10

auto[1]

1115

1

T22

10

T1

7

T16

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T22

6

T1

6

T16

7

from_0to1

530

1

T22

6

T1

6

T16

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1076

1

T22

8

T1

9

T16

14

auto[1]

1173

1

T22

12

T1

11

T16

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1152

1

T22

11

T1

9

T16

10

auto[1]

1097

1

T22

9

T1

11

T16

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T1

2

T16

1

T123

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T22

1

T16

3

T21

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T17

2

T19

2

T21

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T1

2

T17

1

T122

1

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T22

1

T16

1

T17

1

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T22

1

T1

1

T19

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T22

2

T1

1

T16

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T1

1

T16

1

T17

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T22

1

T1

1

T16

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T16

1

T179

3

T33

1

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T22

2

T16

1

T21

2

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T22

2

T1

1

T17

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T1

2

T16

1

T17

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T16

2

T55

2

T122

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T22

1

T1

1

T17

1

auto[1]

from_0to1

auto[1]

auto[1]

84

1

T22

1

T16

1

T21

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T22

11

T1

14

T16

10

auto[1]

1116

1

T22

9

T1

6

T16

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

525

1

T22

5

T1

4

T16

3

from_0to1

531

1

T22

5

T1

5

T16

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1158

1

T22

11

T1

12

T16

11

auto[1]

1091

1

T22

9

T1

8

T16

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T22

10

T1

13

T16

10

auto[1]

1136

1

T22

10

T1

7

T16

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T1

3

T19

2

T55

2

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T16

1

T17

1

T19

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T1

1

T55

1

T179

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T22

1

T21

1

T55

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T22

1

T1

1

T56

3

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T22

1

T21

1

T56

1

auto[0]

from_0to1

auto[1]

auto[0]

47

1

T22

1

T1

1

T19

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T22

1

T21

1

T143

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T22

1

T17

1

T19

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T16

1

T21

1

T55

1

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T22

2

T16

1

T21

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T22

1

T17

1

T55

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T17

1

T19

1

T105

1

auto[1]

from_0to1

auto[0]

auto[1]

86

1

T22

1

T1

1

T16

1

auto[1]

from_0to1

auto[1]

auto[0]

80

1

T1

1

T16

2

T17

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T1

1

T17

1

T55

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1157

1

T22

11

T1

12

T16

12

auto[1]

1092

1

T22

9

T1

8

T16

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

553

1

T22

6

T1

6

T16

3

from_0to1

560

1

T22

7

T1

6

T16

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T22

13

T1

15

T16

13

auto[1]

1109

1

T22

7

T1

5

T16

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T22

10

T1

7

T16

11

auto[1]

1152

1

T22

10

T1

13

T16

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T22

1

T19

2

T21

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T1

5

T16

1

T122

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T16

1

T17

1

T19

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T21

1

T55

1

T56

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T22

2

T1

1

T56

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T22

1

T1

1

T16

1

auto[0]

from_0to1

auto[1]

auto[0]

80

1

T22

2

T17

2

T21

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T19

1

T56

2

T123

3

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T22

2

T16

1

T17

2

auto[1]

from_1to0

auto[0]

auto[1]

87

1

T22

2

T1

1

T19

2

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T22

1

T19

1

T21

1

auto[1]

from_1to0

auto[1]

auto[1]

86

1

T19

1

T21

2

T55

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T16

3

T17

2

T19

1

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T22

1

T1

2

T122

2

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T1

1

T19

1

T21

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T22

1

T1

1

T19

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1137

1

T22

7

T1

9

T16

7

auto[1]

1112

1

T22

13

T1

11

T16

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

554

1

T22

5

T1

4

T16

5

from_0to1

558

1

T22

4

T1

5

T16

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T22

13

T1

11

T16

8

auto[1]

1116

1

T22

7

T1

9

T16

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1154

1

T22

7

T1

11

T16

9

auto[1]

1095

1

T22

13

T1

9

T16

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T19

1

T21

1

T55

3

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T1

1

T56

1

T179

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T16

1

T19

1

T21

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T22

1

T16

1

T123

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T1

1

T19

1

T55

1

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T1

1

T19

1

T21

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T1

1

T17

2

T179

2

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T22

1

T1

1

T16

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T22

1

T1

1

T17

1

auto[1]

from_1to0

auto[0]

auto[1]

82

1

T22

2

T1

2

T16

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T22

1

T16

1

T17

1

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T16

1

T17

1

T19

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T16

1

T17

2

T21

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T22

2

T16

1

T19

1

auto[1]

from_0to1

auto[1]

auto[0]

83

1

T22

1

T1

1

T16

2

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T17

1

T21

1

T123

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T22

11

T1

11

T16

8

auto[1]

1139

1

T22

9

T1

9

T16

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

522

1

T22

3

T1

5

T16

2

from_0to1

514

1

T22

2

T1

6

T16

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1149

1

T22

9

T1

11

T16

11

auto[1]

1100

1

T22

11

T1

9

T16

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T22

11

T1

12

T16

13

auto[1]

1155

1

T22

9

T1

8

T16

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T22

1

T1

2

T16

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T16

1

T17

1

T19

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T55

1

T123

1

T179

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T22

1

T122

1

T179

2

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T16

1

T19

1

T21

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T19

1

T21

1

T122

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T1

3

T19

1

T122

2

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T1

1

T19

1

T21

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T22

1

T1

1

T19

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T1

1

T21

1

T55

3

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T1

1

T19

2

T122

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T17

2

T19

1

T21

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T1

1

T16

1

T55

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T19

1

T55

1

T123

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T22

1

T16

1

T17

2

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T22

1

T1

1

T17

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1137

1

T22

8

T1

10

T16

8

auto[1]

1112

1

T22

12

T1

10

T16

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

518

1

T22

4

T1

4

T16

3

from_0to1

524

1

T22

5

T1

5

T16

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1149

1

T22

12

T1

8

T16

9

auto[1]

1100

1

T22

8

T1

12

T16

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T22

12

T1

10

T16

7

auto[1]

1143

1

T22

8

T1

10

T16

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T55

2

T179

1

T105

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T22

1

T17

2

T56

4

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T22

1

T1

1

T17

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T16

1

T17

1

T21

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T1

1

T56

1

T123

3

auto[0]

from_0to1

auto[0]

auto[1]

85

1

T22

1

T1

1

T16

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T22

1

T17

3

T56

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T19

1

T21

1

T55

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T22

1

T1

1

T19

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T22

1

T16

1

T21

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T1

1

T16

1

T56

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T1

1

T19

3

T21

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T22

1

T1

1

T16

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T22

2

T19

1

T122

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T19

1

T56

1

T143

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T1

2

T16

1

T21

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T22

10

T1

9

T16

8

auto[1]

1131

1

T22

10

T1

11

T16

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

514

1

T22

5

T1

3

T16

7

from_0to1

505

1

T22

6

T1

3

T16

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T22

9

T1

4

T16

10

auto[1]

1137

1

T22

11

T1

16

T16

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1103

1

T22

12

T1

10

T16

6

auto[1]

1146

1

T22

8

T1

10

T16

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T1

1

T16

1

T17

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T56

1

T123

1

T33

2

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T22

2

T17

1

T21

3

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T22

1

T16

1

T55

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T17

1

T21

1

T56

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T22

1

T16

1

T17

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T22

1

T1

1

T17

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T22

1

T16

3

T17

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T22

1

T17

1

T19

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T22

1

T16

1

T105

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T1

1

T16

2

T17

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T1

1

T16

2

T17

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T22

2

T21

1

T56

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T16

1

T17

1

T21

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T22

1

T1

1

T19

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T1

1

T16

1

T17

1