Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155127	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122071

1

T4

20

T5

243

T6

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142493	1			T4	2		T5	209		T6	44
values[0x0]	66901	1			T4	31		T5	290		T22	28
values[0x1]	67804	1			T4	29		T5	290		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125831	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151367

1

T4

22

T5

305

T6

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1077	1			T5	5		T22	1		T17	1
valid_sources[0x01]	1081	1			T5	4		T2	2		T20	5
valid_sources[0x02]	795	1			T5	2		T2	4		T55	1
valid_sources[0x03]	892	1			T5	4		T17	1		T20	3
valid_sources[0x04]	963	1			T5	5		T2	1		T20	10
valid_sources[0x05]	943	1			T5	2		T22	1		T2	6
valid_sources[0x06]	1795	1			T5	4		T20	4		T21	1
valid_sources[0x07]	729	1			T5	1		T2	1		T17	1
valid_sources[0x08]	1349	1			T5	2		T22	1		T20	3
valid_sources[0x09]	925	1			T5	2		T2	8		T20	1
valid_sources[0x0a]	804	1			T5	13		T2	1		T20	2
valid_sources[0x0b]	994	1			T5	11		T2	3		T19	1
valid_sources[0x0c]	763	1			T5	2		T22	1		T19	1
valid_sources[0x0d]	857	1			T5	4		T19	1		T20	4
valid_sources[0x0e]	1062	1			T5	3		T2	5		T19	2
valid_sources[0x0f]	901	1			T5	1		T22	1		T1	3
valid_sources[0x10]	953	1			T5	3		T2	8		T17	1
valid_sources[0x11]	816	1			T5	10		T22	1		T2	4
valid_sources[0x12]	1172	1			T5	4		T22	1		T2	4
valid_sources[0x13]	939	1			T5	10		T22	1		T2	5
valid_sources[0x14]	1068	1			T5	2		T17	2		T19	1
valid_sources[0x15]	1058	1			T5	6		T20	1		T27	1
valid_sources[0x16]	1427	1			T5	4		T22	1		T2	1
valid_sources[0x17]	850	1			T5	1		T2	2		T20	1
valid_sources[0x18]	764	1			T5	4		T2	1		T11	2
valid_sources[0x19]	961	1			T5	6		T22	2		T19	1
valid_sources[0x1a]	822	1			T5	1		T17	1		T19	2
valid_sources[0x1b]	1043	1			T2	4		T20	2		T55	1
valid_sources[0x1c]	917	1			T5	4		T2	5		T17	1
valid_sources[0x1d]	654	1			T5	3		T17	5		T19	1
valid_sources[0x1e]	1053	1			T5	4		T2	1		T19	3
valid_sources[0x1f]	1438	1			T5	4		T2	1		T19	1
valid_sources[0x20]	1005	1			T5	2		T17	1		T19	2
valid_sources[0x21]	950	1			T22	1		T2	9		T17	3
valid_sources[0x22]	1930	1			T5	6		T2	7		T21	1
valid_sources[0x23]	896	1			T22	1		T2	1		T20	2
valid_sources[0x24]	2308	1			T5	3		T2	4		T19	3
valid_sources[0x25]	882	1			T5	1		T22	1		T2	3
valid_sources[0x26]	969	1			T5	1		T2	1		T20	1
valid_sources[0x27]	702	1			T5	8		T2	5		T20	2
valid_sources[0x28]	908	1			T2	5		T17	1		T19	3
valid_sources[0x29]	796	1			T5	3		T2	1		T21	1
valid_sources[0x2a]	1167	1			T5	2		T22	1		T2	8
valid_sources[0x2b]	1166	1			T5	1		T2	4		T17	1
valid_sources[0x2c]	1208	1			T5	5		T2	1		T20	4
valid_sources[0x2d]	834	1			T17	2		T20	6		T21	1
valid_sources[0x2e]	839	1			T5	1		T2	6		T20	2
valid_sources[0x2f]	856	1			T5	8		T22	1		T19	1
valid_sources[0x30]	2057	1			T17	1		T19	2		T21	1
valid_sources[0x31]	1064	1			T5	4		T2	1		T19	1
valid_sources[0x32]	752	1			T5	5		T15	1		T2	2
valid_sources[0x33]	812	1			T5	2		T2	3		T17	1
valid_sources[0x34]	1054	1			T5	4		T22	3		T21	1
valid_sources[0x35]	1735	1			T5	4		T1	3		T2	2
valid_sources[0x36]	1965	1			T5	1		T22	1		T14	2
valid_sources[0x37]	821	1			T5	2		T22	3		T2	3
valid_sources[0x38]	1050	1			T5	5		T18	1		T19	1
valid_sources[0x39]	684	1			T5	3		T20	3		T55	1
valid_sources[0x3a]	1339	1			T5	4		T22	1		T2	2
valid_sources[0x3b]	919	1			T5	6		T2	6		T20	1
valid_sources[0x3c]	1922	1			T5	2		T2	1		T17	1
valid_sources[0x3d]	752	1			T5	2		T2	2		T20	3
valid_sources[0x3e]	952	1			T5	9		T22	1		T55	1
valid_sources[0x3f]	1022	1			T5	4		T22	1		T17	2
valid_sources[0x40]	1129	1			T5	3		T1	185		T21	3
valid_sources[0x41]	960	1			T5	5		T2	1		T17	2
valid_sources[0x42]	907	1			T5	5		T21	1		T56	3
valid_sources[0x43]	704	1			T5	7		T17	1		T20	1
valid_sources[0x44]	912	1			T5	3		T6	12		T22	2
valid_sources[0x45]	923	1			T5	3		T2	2		T17	1
valid_sources[0x46]	1161	1			T5	4		T22	1		T2	5
valid_sources[0x47]	1032	1			T5	4		T2	3		T20	1
valid_sources[0x48]	895	1			T22	1		T1	2		T2	1
valid_sources[0x49]	978	1			T5	6		T2	2		T17	1
valid_sources[0x4a]	969	1			T5	1		T2	2		T19	2
valid_sources[0x4b]	1776	1			T5	6		T21	3		T105	2
valid_sources[0x4c]	781	1			T5	2		T22	2		T2	3
valid_sources[0x4d]	1931	1			T5	6		T2	1		T19	1
valid_sources[0x4e]	741	1			T2	1		T19	1		T20	3
valid_sources[0x4f]	1036	1			T5	1		T22	1		T2	9
valid_sources[0x50]	1257	1			T22	1		T14	2		T2	2
valid_sources[0x51]	1114	1			T5	1		T20	2		T27	1
valid_sources[0x52]	952	1			T5	7		T22	1		T2	1
valid_sources[0x53]	1051	1			T5	7		T2	4		T17	1
valid_sources[0x54]	934	1			T5	4		T17	1		T19	2
valid_sources[0x55]	947	1			T5	3		T22	1		T2	2
valid_sources[0x56]	2504	1			T5	5		T2	9		T17	1
valid_sources[0x57]	845	1			T5	3		T2	1		T55	1
valid_sources[0x58]	2022	1			T5	6		T20	1		T27	2
valid_sources[0x59]	1105	1			T22	1		T19	1		T20	3
valid_sources[0x5a]	959	1			T5	4		T22	1		T20	2
valid_sources[0x5b]	965	1			T5	6		T22	1		T2	6
valid_sources[0x5c]	1764	1			T5	2		T22	1		T2	3
valid_sources[0x5d]	1896	1			T22	1		T17	1		T19	1
valid_sources[0x5e]	788	1			T17	1		T21	1		T56	6
valid_sources[0x5f]	827	1			T5	3		T19	1		T20	4
valid_sources[0x60]	1015	1			T5	1		T22	1		T17	1
valid_sources[0x61]	1613	1			T5	2		T2	1		T122	1
valid_sources[0x62]	1467	1			T5	6		T2	2		T19	2
valid_sources[0x63]	873	1			T5	5		T2	1		T19	1
valid_sources[0x64]	913	1			T19	1		T20	1		T29	1
valid_sources[0x65]	1114	1			T22	1		T2	5		T11	2
valid_sources[0x66]	1085	1			T5	1		T17	1		T20	1
valid_sources[0x67]	1092	1			T5	5		T14	1		T2	4
valid_sources[0x68]	1742	1			T5	4		T2	4		T18	1
valid_sources[0x69]	1298	1			T5	2		T22	1		T2	3
valid_sources[0x6a]	1531	1			T22	3		T2	1		T17	1
valid_sources[0x6b]	1162	1			T5	3		T2	7		T19	1
valid_sources[0x6c]	833	1			T2	4		T19	2		T20	1
valid_sources[0x6d]	707	1			T5	2		T22	2		T2	4
valid_sources[0x6e]	986	1			T5	2		T1	9		T2	2
valid_sources[0x6f]	888	1			T22	3		T20	2		T60	1
valid_sources[0x70]	932	1			T5	3		T2	5		T20	4
valid_sources[0x71]	1440	1			T14	1		T2	5		T17	3
valid_sources[0x72]	1641	1			T5	2		T22	1		T14	1
valid_sources[0x73]	725	1			T5	4		T17	1		T19	1
valid_sources[0x74]	1095	1			T2	2		T19	1		T20	2
valid_sources[0x75]	888	1			T5	6		T19	1		T20	1
valid_sources[0x76]	959	1			T5	1		T20	1		T21	1
valid_sources[0x77]	902	1			T5	6		T22	1		T19	1
valid_sources[0x78]	1039	1			T5	1		T22	1		T20	1
valid_sources[0x79]	1137	1			T1	47		T15	1		T2	2
valid_sources[0x7a]	961	1			T22	2		T2	6		T17	1
valid_sources[0x7b]	1032	1			T5	4		T17	1		T20	4
valid_sources[0x7c]	1259	1			T5	2		T22	1		T17	2
valid_sources[0x7d]	1996	1			T5	3		T19	1		T20	1
valid_sources[0x7e]	1033	1			T5	2		T22	1		T17	1
valid_sources[0x7f]	890	1			T5	7		T22	1		T17	2
valid_sources[0x80]	1012	1			T5	2		T2	5		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65394

1

T5

110

T6

18

T22

29

values[0x0]

all_enables

biggest_size

32898

1

T4

12

T5

87

T22

9

values[0x1]

all_enables

biggest_size

23779

1

T4

8

T5

46

T22

8