Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T9,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T9,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T39,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T9,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T9,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T39,T44
0	1	Covered	T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T39,T44
0	1	Covered	T9,T44,T41
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T39,T44
1	-	Covered	T9,T44,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T9,T39
DetectSt	168	Covered	T9,T39,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T39,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T39,T44
DebounceSt->IdleSt	163	Covered	T26,T71,T181
DetectSt->IdleSt	186	Covered	T180
DetectSt->StableSt	191	Covered	T9,T39,T44
IdleSt->DebounceSt	148	Covered	T26,T9,T39
StableSt->IdleSt	206	Covered	T9,T44,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T9,T39
0	1	Covered	T26,T9,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T39,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T9,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T39,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T181,T182,T152
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T9,T39
DetectSt	-	-	-	-	1	-	-	Covered	T180
DetectSt	-	-	-	-	0	1	-	Covered	T9,T39,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T44,T41
StableSt	-	-	-	-	-	-	0	Covered	T9,T39,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	75	0	0
CntIncr_A	8299801	14788	0	0
CntNoWrap_A	8299801	7623589	0	0
DetectStDropOut_A	8299801	1	0	0
DetectedOut_A	8299801	2269	0	0
DetectedPulseOut_A	8299801	34	0	0
DisabledIdleSt_A	8299801	7495537	0	0
DisabledNoDetection_A	8299801	7497958	0	0
EnterDebounceSt_A	8299801	40	0	0
EnterDetectSt_A	8299801	35	0	0
EnterStableSt_A	8299801	34	0	0
PulseIsPulse_A	8299801	34	0	0
StayInStableSt	8299801	2216	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	75	0	0
T3	166236	0	0	0
T7	623	0	0	0
T9	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	2	0	0
T41	0	2	0	0
T44	0	4	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T82	0	4	0	0
T153	0	2	0	0
T168	0	2	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	14788	0	0
T3	166236	0	0	0
T7	623	0	0	0
T9	0	82	0	0
T26	6326	18	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	12711	0	0
T41	0	11	0	0
T44	0	170	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	25	0	0
T82	0	58	0	0
T153	0	55	0	0
T168	0	28	0	0
T183	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623589	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1	0	0
T180	819	1	0	0
T181	16125	0	0	0
T184	408	0	0	0
T185	430	0	0	0
T186	493	0	0	0
T187	402	0	0	0
T188	758	0	0	0
T189	576	0	0	0
T190	422	0	0	0
T191	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2269	0	0
T9	1034	42	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	45	0	0
T41	0	6	0	0
T44	0	77	0	0
T48	688	0	0	0
T60	952	0	0	0
T82	0	83	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	49	0	0
T157	0	49	0	0
T167	0	161	0	0
T168	0	41	0	0
T179	504	0	0	0
T183	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	34	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T48	688	0	0	0
T60	952	0	0	0
T82	0	2	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	1	0	0
T157	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7495537	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7497958	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	40	0	0
T3	166236	0	0	0
T7	623	0	0	0
T9	0	1	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T82	0	2	0	0
T153	0	1	0	0
T168	0	1	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	35	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T48	688	0	0	0
T60	952	0	0	0
T82	0	2	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	1	0	0
T157	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	34	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T48	688	0	0	0
T60	952	0	0	0
T82	0	2	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	1	0	0
T157	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	34	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T48	688	0	0	0
T60	952	0	0	0
T82	0	2	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	1	0	0
T157	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2216	0	0
T9	1034	41	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	43	0	0
T41	0	5	0	0
T44	0	74	0	0
T48	688	0	0	0
T60	952	0	0	0
T82	0	80	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	48	0	0
T157	0	48	0	0
T167	0	159	0	0
T168	0	39	0	0
T179	504	0	0	0
T183	0	97	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	15	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T82	0	1	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T116	0	1	0	0
T153	0	1	0	0
T157	0	1	0	0
T179	504	0	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T10,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T7,T9
1	0	Covered	T4,T6,T22
1	1	Covered	T26,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T43
0	1	Covered	T76,T193
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T43
0	1	Covered	T9,T40,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T43
1	-	Covered	T9,T40,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T7,T9
DetectSt	168	Covered	T9,T10,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T10,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T43
DebounceSt->IdleSt	163	Covered	T26,T7,T40
DetectSt->IdleSt	186	Covered	T76,T193
DetectSt->StableSt	191	Covered	T9,T10,T43
IdleSt->DebounceSt	148	Covered	T26,T7,T9
StableSt->IdleSt	206	Covered	T9,T40,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T7,T9
0	1	Covered	T26,T7,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T40,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T76,T193
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T40,T39
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	157	0	0
CntIncr_A	8299801	156506	0	0
CntNoWrap_A	8299801	7623507	0	0
DetectStDropOut_A	8299801	2	0	0
DetectedOut_A	8299801	63741	0	0
DetectedPulseOut_A	8299801	73	0	0
DisabledIdleSt_A	8299801	7096001	0	0
DisabledNoDetection_A	8299801	7098417	0	0
EnterDebounceSt_A	8299801	83	0	0
EnterDetectSt_A	8299801	75	0	0
EnterStableSt_A	8299801	73	0	0
PulseIsPulse_A	8299801	73	0	0
StayInStableSt	8299801	63629	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8299801	3188	0	0
gen_low_level_sva.LowLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	157	0	0
T3	166236	0	0	0
T7	623	1	0	0
T9	0	4	0	0
T10	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T41	0	4	0	0
T43	0	2	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	156506	0	0
T3	166236	0	0	0
T7	623	85	0	0
T9	0	164	0	0
T10	0	64	0	0
T26	6326	17	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	12711	0	0
T40	0	156	0	0
T41	0	22	0	0
T43	0	16	0	0
T44	0	170	0	0
T45	0	90	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623507	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2	0	0
T76	649	1	0	0
T77	86606	0	0	0
T147	1193	0	0	0
T193	0	1	0	0
T194	415	0	0	0
T195	15727	0	0	0
T196	524	0	0	0
T197	524	0	0	0
T198	402	0	0	0
T199	594	0	0	0
T200	774	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	63741	0	0
T9	1034	252	0	0
T10	602	40	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	50487	0	0
T40	0	92	0	0
T41	0	78	0	0
T43	0	40	0	0
T44	0	72	0	0
T45	0	43	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	86	0	0
T168	0	9	0	0
T179	504	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	73	0	0
T9	1034	2	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	2	0	0
T168	0	1	0	0
T179	504	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7096001	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7098417	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	83	0	0
T3	166236	0	0	0
T7	623	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	75	0	0
T9	1034	2	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	2	0	0
T168	0	1	0	0
T179	504	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	73	0	0
T9	1034	2	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	2	0	0
T168	0	1	0	0
T179	504	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	73	0	0
T9	1034	2	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	2	0	0
T168	0	1	0	0
T179	504	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	63629	0	0
T9	1034	249	0	0
T10	602	38	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	50486	0	0
T40	0	89	0	0
T41	0	75	0	0
T43	0	38	0	0
T44	0	71	0	0
T45	0	41	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T153	0	83	0	0
T168	0	8	0	0
T179	504	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	3188	0	0
T1	132641	21	0	0
T2	28822	0	0	0
T4	522	5	0	0
T5	8262	0	0	0
T6	444	5	0	0
T14	632	0	0	0
T15	426	3	0	0
T16	526	5	0	0
T17	504	7	0	0
T18	0	3	0	0
T19	0	13	0	0
T21	0	3	0	0
T22	527	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	34	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T148	0	2	0	0
T153	0	1	0	0
T168	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T10,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T8,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T13
0	1	Covered	T170
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T13
0	1	Covered	T8,T40,T202
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T13
1	-	Covered	T8,T40,T202

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T8,T10
DetectSt	168	Covered	T8,T10,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T10,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T13
DebounceSt->IdleSt	163	Covered	T26,T44,T71
DetectSt->IdleSt	186	Covered	T170
DetectSt->StableSt	191	Covered	T8,T10,T13
IdleSt->DebounceSt	148	Covered	T26,T8,T10
StableSt->IdleSt	206	Covered	T8,T13,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T8,T10
0	1	Covered	T26,T8,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T176,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T170
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T40,T202
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	100	0	0
CntIncr_A	8299801	66039	0	0
CntNoWrap_A	8299801	7623564	0	0
DetectStDropOut_A	8299801	1	0	0
DetectedOut_A	8299801	78409	0	0
DetectedPulseOut_A	8299801	46	0	0
DisabledIdleSt_A	8299801	7238144	0	0
DisabledNoDetection_A	8299801	7240566	0	0
EnterDebounceSt_A	8299801	53	0	0
EnterDetectSt_A	8299801	47	0	0
EnterStableSt_A	8299801	46	0	0
PulseIsPulse_A	8299801	46	0	0
StayInStableSt	8299801	78342	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	100	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	4	0	0
T10	0	2	0	0
T13	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T40	0	6	0	0
T44	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T149	0	2	0	0
T176	0	1	0	0
T202	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	66039	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	132	0	0
T10	0	64	0	0
T13	0	73	0	0
T26	6326	18	0	0
T27	492	0	0	0
T30	5466	0	0	0
T40	0	142	0	0
T44	0	85	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	26	0	0
T149	0	98	0	0
T176	0	14	0	0
T202	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623564	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1	0	0
T170	534	1	0	0
T171	503	0	0	0
T172	12515	0	0	0
T173	421	0	0	0
T174	2254	0	0	0
T175	736	0	0	0
T203	410	0	0	0
T204	662	0	0	0
T205	756	0	0	0
T206	17333	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	78409	0	0
T8	1017	370	0	0
T9	1034	0	0	0
T10	602	40	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	122	0	0
T40	0	253	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T149	0	192	0	0
T154	0	98	0	0
T155	0	323	0	0
T178	0	123	0	0
T179	504	0	0	0
T201	0	1	0	0
T202	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	46	0	0
T8	1017	2	0	0
T9	1034	0	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T40	0	3	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T149	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T202	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7238144	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7240566	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	53	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	2	0	0
T10	0	1	0	0
T13	0	1	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T40	0	3	0	0
T44	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T149	0	1	0	0
T176	0	1	0	0
T202	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	47	0	0
T8	1017	2	0	0
T9	1034	0	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T40	0	3	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T149	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T202	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	46	0	0
T8	1017	2	0	0
T9	1034	0	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T40	0	3	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T149	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T202	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	46	0	0
T8	1017	2	0	0
T9	1034	0	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T40	0	3	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T149	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T202	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	78342	0	0
T8	1017	367	0	0
T9	1034	0	0	0
T10	602	38	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	120	0	0
T40	0	248	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T149	0	191	0	0
T154	0	97	0	0
T155	0	321	0	0
T167	0	162	0	0
T178	0	122	0	0
T179	504	0	0	0
T202	0	77	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	25	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T40	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T149	0	1	0	0
T154	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T202	0	2	0	0
T207	0	1	0	0
T208	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T8,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T8,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T42,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T8,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T8,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T42,T41
0	1	Covered	T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T42,T41
0	1	Covered	T8,T148,T183
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T42,T41
1	-	Covered	T8,T148,T183

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T8,T42
DetectSt	168	Covered	T8,T42,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T42,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T42,T41
DebounceSt->IdleSt	163	Covered	T26,T71
DetectSt->IdleSt	186	Covered	T77
DetectSt->StableSt	191	Covered	T8,T42,T41
IdleSt->DebounceSt	148	Covered	T26,T8,T42
StableSt->IdleSt	206	Covered	T8,T148,T81

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T8,T42
0	1	Covered	T26,T8,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T42,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T8,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T42,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T8,T42
DetectSt	-	-	-	-	1	-	-	Covered	T77
DetectSt	-	-	-	-	0	1	-	Covered	T8,T42,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T148,T183
StableSt	-	-	-	-	-	-	0	Covered	T8,T42,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	84	0	0
CntIncr_A	8299801	19752	0	0
CntNoWrap_A	8299801	7623580	0	0
DetectStDropOut_A	8299801	1	0	0
DetectedOut_A	8299801	9723	0	0
DetectedPulseOut_A	8299801	40	0	0
DisabledIdleSt_A	8299801	7187532	0	0
DisabledNoDetection_A	8299801	7189952	0	0
EnterDebounceSt_A	8299801	43	0	0
EnterDetectSt_A	8299801	41	0	0
EnterStableSt_A	8299801	40	0	0
PulseIsPulse_A	8299801	40	0	0
StayInStableSt	8299801	9656	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8299801	6634	0	0
gen_low_level_sva.LowLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	84	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T81	0	2	0	0
T148	0	4	0	0
T149	0	2	0	0
T153	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	19752	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	66	0	0
T26	6326	18	0	0
T27	492	0	0	0
T30	5466	0	0	0
T41	0	11	0	0
T42	0	47	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	25	0	0
T81	0	90	0	0
T148	0	17644	0	0
T149	0	98	0	0
T153	0	55	0	0
T201	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623580	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1	0	0
T77	86606	1	0	0
T147	1193	0	0	0
T194	415	0	0	0
T195	15727	0	0	0
T196	524	0	0	0
T197	524	0	0	0
T198	402	0	0	0
T199	594	0	0	0
T200	774	0	0	0
T209	39155	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	9723	0	0
T8	1017	37	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T41	0	57	0	0
T42	0	41	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	42	0	0
T104	402	0	0	0
T148	0	6439	0	0
T149	0	192	0	0
T153	0	147	0	0
T178	0	100	0	0
T179	504	0	0	0
T183	0	101	0	0
T201	0	340	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	40	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T104	402	0	0	0
T148	0	2	0	0
T149	0	1	0	0
T153	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7187532	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7189952	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	43	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	1	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T81	0	1	0	0
T148	0	2	0	0
T149	0	1	0	0
T153	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	41	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T104	402	0	0	0
T148	0	2	0	0
T149	0	1	0	0
T153	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	40	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T104	402	0	0	0
T148	0	2	0	0
T149	0	1	0	0
T153	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	40	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T104	402	0	0	0
T148	0	2	0	0
T149	0	1	0	0
T153	0	1	0	0
T178	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	9656	0	0
T8	1017	36	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T41	0	55	0	0
T42	0	39	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	40	0	0
T104	402	0	0	0
T148	0	6437	0	0
T149	0	190	0	0
T153	0	145	0	0
T178	0	98	0	0
T179	504	0	0	0
T183	0	100	0	0
T201	0	338	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	6634	0	0
T1	132641	16	0	0
T2	28822	12	0	0
T4	522	6	0	0
T5	8262	29	0	0
T6	444	8	0	0
T14	632	0	0	0
T15	426	2	0	0
T16	526	6	0	0
T17	504	6	0	0
T19	0	13	0	0
T22	527	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	13	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T77	0	1	0	0
T104	402	0	0	0
T116	0	1	0	0
T148	0	2	0	0
T179	504	0	0	0
T183	0	1	0	0
T192	0	1	0	0
T207	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T7,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T213,T77,T214
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T8,T9,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T9
1	-	Covered	T8,T9,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T7,T8
DetectSt	168	Covered	T7,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T9
DebounceSt->IdleSt	163	Covered	T26,T71,T167
DetectSt->IdleSt	186	Covered	T213,T77,T214
DetectSt->StableSt	191	Covered	T7,T8,T9
IdleSt->DebounceSt	148	Covered	T26,T7,T8
StableSt->IdleSt	206	Covered	T8,T9,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T7,T8
0	1	Covered	T26,T7,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T167,T129,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T213,T77,T214
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T40
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	168	0	0
CntIncr_A	8299801	37165	0	0
CntNoWrap_A	8299801	7623496	0	0
DetectStDropOut_A	8299801	4	0	0
DetectedOut_A	8299801	47989	0	0
DetectedPulseOut_A	8299801	74	0	0
DisabledIdleSt_A	8299801	7486149	0	0
DisabledNoDetection_A	8299801	7488556	0	0
EnterDebounceSt_A	8299801	90	0	0
EnterDetectSt_A	8299801	78	0	0
EnterStableSt_A	8299801	74	0	0
PulseIsPulse_A	8299801	74	0	0
StayInStableSt	8299801	47885	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	44	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	168	0	0
T3	166236	0	0	0
T7	623	2	0	0
T8	0	6	0	0
T9	0	4	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	4	0	0
T40	0	8	0	0
T44	0	6	0	0
T45	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T149	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	37165	0	0
T3	166236	0	0	0
T7	623	85	0	0
T8	0	198	0	0
T9	0	164	0	0
T26	6326	18	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	25422	0	0
T40	0	194	0	0
T44	0	133	0	0
T45	0	90	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	25	0	0
T149	0	196	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623496	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	4	0	0
T77	0	1	0	0
T157	40175	0	0	0
T213	542	1	0	0
T214	0	1	0	0
T215	0	1	0	0
T216	489	0	0	0
T217	491	0	0	0
T218	7153	0	0	0
T219	522	0	0	0
T220	12990	0	0	0
T221	523	0	0	0
T222	711	0	0	0
T223	8206	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	47989	0	0
T7	623	43	0	0
T8	1017	88	0	0
T9	1034	251	0	0
T28	492	0	0	0
T29	523	0	0	0
T39	0	37780	0	0
T40	0	187	0	0
T44	0	471	0	0
T45	0	151	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	157	0	0
T122	501	0	0	0
T123	505	0	0	0
T149	0	230	0	0
T177	402	0	0	0
T224	0	184	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	74	0	0
T7	623	1	0	0
T8	1017	3	0	0
T9	1034	2	0	0
T28	492	0	0	0
T29	523	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T44	0	3	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T122	501	0	0	0
T123	505	0	0	0
T149	0	2	0	0
T177	402	0	0	0
T224	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7486149	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7488556	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	90	0	0
T3	166236	0	0	0
T7	623	1	0	0
T8	0	3	0	0
T9	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T149	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	78	0	0
T7	623	1	0	0
T8	1017	3	0	0
T9	1034	2	0	0
T28	492	0	0	0
T29	523	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T44	0	3	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T122	501	0	0	0
T123	505	0	0	0
T149	0	2	0	0
T177	402	0	0	0
T224	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	74	0	0
T7	623	1	0	0
T8	1017	3	0	0
T9	1034	2	0	0
T28	492	0	0	0
T29	523	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T44	0	3	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T122	501	0	0	0
T123	505	0	0	0
T149	0	2	0	0
T177	402	0	0	0
T224	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	74	0	0
T7	623	1	0	0
T8	1017	3	0	0
T9	1034	2	0	0
T28	492	0	0	0
T29	523	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T44	0	3	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T122	501	0	0	0
T123	505	0	0	0
T149	0	2	0	0
T177	402	0	0	0
T224	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	47885	0	0
T7	623	41	0	0
T8	1017	84	0	0
T9	1034	248	0	0
T28	492	0	0	0
T29	523	0	0	0
T39	0	37777	0	0
T40	0	181	0	0
T44	0	466	0	0
T45	0	149	0	0
T59	1289	0	0	0
T60	952	0	0	0
T81	0	155	0	0
T122	501	0	0	0
T123	505	0	0	0
T149	0	227	0	0
T177	402	0	0	0
T224	0	181	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	44	0	0
T8	1017	2	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T129	0	2	0	0
T149	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T179	504	0	0	0
T224	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T8,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T8,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T8,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T8,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T40
0	1	Covered	T8,T13,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T13,T40
1	-	Covered	T8,T13,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T8,T13
DetectSt	168	Covered	T8,T13,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T13,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T13,T40
DebounceSt->IdleSt	163	Covered	T26,T71,T129
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T13,T40
IdleSt->DebounceSt	148	Covered	T26,T8,T13
StableSt->IdleSt	206	Covered	T8,T13,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T8,T13
0	1	Covered	T26,T8,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T8,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T13,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T129
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T8,T13
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T13,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T13,T40
StableSt	-	-	-	-	-	-	0	Covered	T8,T13,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	89	0	0
CntIncr_A	8299801	71485	0	0
CntNoWrap_A	8299801	7623575	0	0
DetectStDropOut_A	8299801	0	0	0
DetectedOut_A	8299801	2789	0	0
DetectedPulseOut_A	8299801	43	0	0
DisabledIdleSt_A	8299801	7163503	0	0
DisabledNoDetection_A	8299801	7165916	0	0
EnterDebounceSt_A	8299801	46	0	0
EnterDetectSt_A	8299801	43	0	0
EnterStableSt_A	8299801	43	0	0
PulseIsPulse_A	8299801	43	0	0
StayInStableSt	8299801	2723	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8299801	6278	0	0
gen_low_level_sva.LowLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	89	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	4	0	0
T13	0	4	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	2	0	0
T44	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T153	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	71485	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	132	0	0
T13	0	146	0	0
T26	6326	18	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	12711	0	0
T40	0	104	0	0
T41	0	11	0	0
T44	0	24	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	25	0	0
T153	0	55	0	0
T168	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623575	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2789	0	0
T8	1017	185	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	80	0	0
T39	0	40	0	0
T40	0	28	0	0
T41	0	38	0	0
T44	0	82	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T153	0	147	0	0
T155	0	323	0	0
T167	0	44	0	0
T168	0	40	0	0
T179	504	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	43	0	0
T8	1017	2	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T153	0	1	0	0
T155	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T179	504	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7163503	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7165916	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	46	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	2	0	0
T13	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T153	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	43	0	0
T8	1017	2	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T153	0	1	0	0
T155	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T179	504	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	43	0	0
T8	1017	2	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T153	0	1	0	0
T155	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T179	504	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	43	0	0
T8	1017	2	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T153	0	1	0	0
T155	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T179	504	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2723	0	0
T8	1017	183	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	77	0	0
T39	0	39	0	0
T40	0	26	0	0
T41	0	36	0	0
T44	0	81	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T153	0	145	0	0
T155	0	321	0	0
T167	0	43	0	0
T168	0	38	0	0
T179	504	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	6278	0	0
T1	132641	10	0	0
T2	28822	11	0	0
T4	522	5	0	0
T5	8262	34	0	0
T6	444	3	0	0
T14	632	0	0	0
T15	426	2	0	0
T16	526	6	0	0
T17	504	5	0	0
T19	0	12	0	0
T22	527	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	20	0	0
T8	1017	2	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T77	0	2	0	0
T104	402	0	0	0
T129	0	1	0	0
T131	0	1	0	0
T150	0	1	0	0
T167	0	1	0	0
T179	504	0	0	0