Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T7,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T9,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T8,T9,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T9
1	-	Covered	T8,T9,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T7,T8
DetectSt	168	Covered	T7,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T9
DebounceSt->IdleSt	163	Covered	T26,T71,T225
DetectSt->IdleSt	186	Covered	T9,T82
DetectSt->StableSt	191	Covered	T7,T8,T9
IdleSt->DebounceSt	148	Covered	T26,T7,T8
StableSt->IdleSt	206	Covered	T8,T9,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T7,T8
0	1	Covered	T26,T7,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T225,T226,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T9,T82
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T40
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	135	0	0
CntIncr_A	8299801	32011	0	0
CntNoWrap_A	8299801	7623529	0	0
DetectStDropOut_A	8299801	2	0	0
DetectedOut_A	8299801	10579	0	0
DetectedPulseOut_A	8299801	63	0	0
DisabledIdleSt_A	8299801	7515956	0	0
DisabledNoDetection_A	8299801	7518368	0	0
EnterDebounceSt_A	8299801	71	0	0
EnterDetectSt_A	8299801	65	0	0
EnterStableSt_A	8299801	63	0	0
PulseIsPulse_A	8299801	63	0	0
StayInStableSt	8299801	10481	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	135	0	0
T3	166236	0	0	0
T7	623	2	0	0
T8	0	4	0	0
T9	0	4	0	0
T10	0	2	0	0
T13	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T40	0	6	0	0
T43	0	2	0	0
T44	0	4	0	0
T45	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	32011	0	0
T3	166236	0	0	0
T7	623	85	0	0
T8	0	132	0	0
T9	0	164	0	0
T10	0	64	0	0
T13	0	73	0	0
T26	6326	17	0	0
T27	492	0	0	0
T30	5466	0	0	0
T40	0	142	0	0
T43	0	16	0	0
T44	0	48	0	0
T45	0	90	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623529	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T48	688	0	0	0
T60	952	0	0	0
T82	0	1	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T179	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	10579	0	0
T7	623	129	0	0
T8	1017	295	0	0
T9	1034	212	0	0
T10	0	39	0	0
T13	0	122	0	0
T28	492	0	0	0
T29	523	0	0	0
T40	0	256	0	0
T43	0	57	0	0
T44	0	46	0	0
T45	0	44	0	0
T59	1289	0	0	0
T60	952	0	0	0
T122	501	0	0	0
T123	505	0	0	0
T177	402	0	0	0
T202	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	63	0	0
T7	623	1	0	0
T8	1017	2	0	0
T9	1034	1	0	0
T10	0	1	0	0
T13	0	1	0	0
T28	492	0	0	0
T29	523	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T122	501	0	0	0
T123	505	0	0	0
T177	402	0	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7515956	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7518368	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	71	0	0
T3	166236	0	0	0
T7	623	1	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	1	0	0
T13	0	1	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	65	0	0
T7	623	1	0	0
T8	1017	2	0	0
T9	1034	2	0	0
T10	0	1	0	0
T13	0	1	0	0
T28	492	0	0	0
T29	523	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T122	501	0	0	0
T123	505	0	0	0
T177	402	0	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	63	0	0
T7	623	1	0	0
T8	1017	2	0	0
T9	1034	1	0	0
T10	0	1	0	0
T13	0	1	0	0
T28	492	0	0	0
T29	523	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T122	501	0	0	0
T123	505	0	0	0
T177	402	0	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	63	0	0
T7	623	1	0	0
T8	1017	2	0	0
T9	1034	1	0	0
T10	0	1	0	0
T13	0	1	0	0
T28	492	0	0	0
T29	523	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T59	1289	0	0	0
T60	952	0	0	0
T122	501	0	0	0
T123	505	0	0	0
T177	402	0	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	10481	0	0
T7	623	127	0	0
T8	1017	292	0	0
T9	1034	211	0	0
T10	0	37	0	0
T13	0	120	0	0
T28	492	0	0	0
T29	523	0	0	0
T40	0	251	0	0
T43	0	55	0	0
T44	0	43	0	0
T45	0	42	0	0
T59	1289	0	0	0
T60	952	0	0	0
T122	501	0	0	0
T123	505	0	0	0
T148	0	80	0	0
T177	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	28	0	0
T8	1017	1	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T148	0	1	0	0
T155	0	1	0	0
T167	0	1	0	0
T179	504	0	0	0
T202	0	1	0	0
T224	0	1	0	0
T227	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T7,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T39
0	1	Covered	T8,T9,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T39
1	-	Covered	T8,T9,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T8,T9
DetectSt	168	Covered	T8,T9,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T9,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T39
DebounceSt->IdleSt	163	Covered	T26,T71,T228
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T9,T39
IdleSt->DebounceSt	148	Covered	T26,T8,T9
StableSt->IdleSt	206	Covered	T8,T9,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T8,T9
0	1	Covered	T26,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T228
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T8,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T39
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	61	0	0
CntIncr_A	8299801	92262	0	0
CntNoWrap_A	8299801	7623603	0	0
DetectStDropOut_A	8299801	0	0	0
DetectedOut_A	8299801	90051	0	0
DetectedPulseOut_A	8299801	29	0	0
DisabledIdleSt_A	8299801	7093626	0	0
DisabledNoDetection_A	8299801	7096047	0	0
EnterDebounceSt_A	8299801	32	0	0
EnterDetectSt_A	8299801	29	0	0
EnterStableSt_A	8299801	29	0	0
PulseIsPulse_A	8299801	29	0	0
StayInStableSt	8299801	90006	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8299801	6237	0	0
gen_low_level_sva.LowLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	61	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	2	0	0
T9	0	4	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	4	0	0
T41	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T82	0	2	0	0
T148	0	2	0	0
T149	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	92262	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	66	0	0
T9	0	164	0	0
T26	6326	18	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	25422	0	0
T41	0	11	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	24	0	0
T82	0	29	0	0
T148	0	8822	0	0
T149	0	98	0	0
T202	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623603	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	90051	0	0
T8	1017	38	0	0
T9	1034	81	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	87	0	0
T41	0	41	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T82	0	42	0	0
T104	402	0	0	0
T148	0	24247	0	0
T149	0	333	0	0
T167	0	39	0	0
T179	504	0	0	0
T201	0	50	0	0
T202	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	29	0	0
T8	1017	1	0	0
T9	1034	2	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T82	0	1	0	0
T104	402	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T167	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7093626	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7096047	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	32	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T82	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	29	0	0
T8	1017	1	0	0
T9	1034	2	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T82	0	1	0	0
T104	402	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T167	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	29	0	0
T8	1017	1	0	0
T9	1034	2	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T82	0	1	0	0
T104	402	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T167	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	29	0	0
T8	1017	1	0	0
T9	1034	2	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T82	0	1	0	0
T104	402	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T167	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	90006	0	0
T8	1017	37	0	0
T9	1034	78	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	84	0	0
T41	0	40	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T82	0	40	0	0
T104	402	0	0	0
T148	0	24246	0	0
T149	0	331	0	0
T167	0	37	0	0
T179	504	0	0	0
T201	0	49	0	0
T202	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	6237	0	0
T1	132641	12	0	0
T2	28822	11	0	0
T4	522	3	0	0
T5	8262	24	0	0
T6	444	6	0	0
T14	632	0	0	0
T15	426	2	0	0
T16	526	5	0	0
T17	504	4	0	0
T19	0	9	0	0
T22	527	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	13	0	0
T8	1017	1	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T77	0	1	0	0
T104	402	0	0	0
T148	0	1	0	0
T151	0	2	0	0
T179	504	0	0	0
T201	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T9,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T9,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T13,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T9,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T9,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T43
0	1	Covered	T39,T231
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T43
0	1	Covered	T9,T13,T153
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T43
1	-	Covered	T9,T13,T153

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T9,T13
DetectSt	168	Covered	T9,T13,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T13,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T13,T43
DebounceSt->IdleSt	163	Covered	T26,T71,T210
DetectSt->IdleSt	186	Covered	T39,T231
DetectSt->StableSt	191	Covered	T9,T13,T43
IdleSt->DebounceSt	148	Covered	T26,T9,T13
StableSt->IdleSt	206	Covered	T9,T13,T153

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T9,T13
0	1	Covered	T26,T9,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T13,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T9,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T13,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T210,T150,T228
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T9,T13
DetectSt	-	-	-	-	1	-	-	Covered	T39,T231
DetectSt	-	-	-	-	0	1	-	Covered	T9,T13,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T13,T153
StableSt	-	-	-	-	-	-	0	Covered	T9,T13,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	131	0	0
CntIncr_A	8299801	16956	0	0
CntNoWrap_A	8299801	7623533	0	0
DetectStDropOut_A	8299801	2	0	0
DetectedOut_A	8299801	4562	0	0
DetectedPulseOut_A	8299801	58	0	0
DisabledIdleSt_A	8299801	7505986	0	0
DisabledNoDetection_A	8299801	7508398	0	0
EnterDebounceSt_A	8299801	72	0	0
EnterDetectSt_A	8299801	60	0	0
EnterStableSt_A	8299801	58	0	0
PulseIsPulse_A	8299801	58	0	0
StayInStableSt	8299801	4480	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	131	0	0
T3	166236	0	0	0
T7	623	0	0	0
T9	0	4	0	0
T13	0	4	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	2	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T149	0	4	0	0
T153	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	16956	0	0
T3	166236	0	0	0
T7	623	0	0	0
T9	0	164	0	0
T13	0	146	0	0
T26	6326	18	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	12711	0	0
T43	0	16	0	0
T45	0	90	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	25	0	0
T149	0	196	0	0
T153	0	55	0	0
T168	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623533	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2	0	0
T36	17604	0	0	0
T39	94785	1	0	0
T45	651	0	0	0
T64	493	0	0	0
T87	1603	0	0	0
T118	484	0	0	0
T119	15785	0	0	0
T120	13812	0	0	0
T231	0	1	0	0
T232	429	0	0	0
T233	105172	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	4562	0	0
T9	1034	42	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	212	0	0
T43	0	57	0	0
T45	0	151	0	0
T48	688	0	0	0
T60	952	0	0	0
T81	0	157	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	458	0	0
T153	0	116	0	0
T155	0	78	0	0
T168	0	9	0	0
T179	504	0	0	0
T224	0	25	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	58	0	0
T9	1034	2	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	2	0	0
T153	0	1	0	0
T155	0	2	0	0
T168	0	1	0	0
T179	504	0	0	0
T224	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7505986	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7508398	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	72	0	0
T3	166236	0	0	0
T7	623	0	0	0
T9	0	2	0	0
T13	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T149	0	2	0	0
T153	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	60	0	0
T9	1034	2	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	2	0	0
T39	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	2	0	0
T153	0	1	0	0
T168	0	1	0	0
T179	504	0	0	0
T224	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	58	0	0
T9	1034	2	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	2	0	0
T153	0	1	0	0
T155	0	2	0	0
T168	0	1	0	0
T179	504	0	0	0
T224	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	58	0	0
T9	1034	2	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T81	0	1	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	2	0	0
T153	0	1	0	0
T155	0	2	0	0
T168	0	1	0	0
T179	504	0	0	0
T224	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	4480	0	0
T9	1034	39	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	209	0	0
T43	0	55	0	0
T45	0	149	0	0
T48	688	0	0	0
T60	952	0	0	0
T81	0	155	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	455	0	0
T153	0	115	0	0
T155	0	75	0	0
T168	0	8	0	0
T179	504	0	0	0
T224	0	24	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	34	0	0
T9	1034	1	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T129	0	2	0	0
T149	0	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T167	0	2	0	0
T168	0	1	0	0
T179	504	0	0	0
T224	0	1	0	0
T234	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T40,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T40,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T40,T39,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T7,T42
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T40,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T39,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T39,T41
0	1	Covered	T40,T41,T149
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T39,T41
1	-	Covered	T40,T41,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T40,T39
DetectSt	168	Covered	T40,T39,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T40,T39,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T39,T41
DebounceSt->IdleSt	163	Covered	T26,T71,T76
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T39,T41
IdleSt->DebounceSt	148	Covered	T26,T40,T39
StableSt->IdleSt	206	Covered	T40,T41,T149

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T40,T39
0	1	Covered	T26,T40,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T39,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T40,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T39,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T76
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T40,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T39,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T41,T149
StableSt	-	-	-	-	-	-	0	Covered	T40,T39,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	89	0	0
CntIncr_A	8299801	136556	0	0
CntNoWrap_A	8299801	7623575	0	0
DetectStDropOut_A	8299801	0	0	0
DetectedOut_A	8299801	45628	0	0
DetectedPulseOut_A	8299801	43	0	0
DisabledIdleSt_A	8299801	7097513	0	0
DisabledNoDetection_A	8299801	7099927	0	0
EnterDebounceSt_A	8299801	46	0	0
EnterDetectSt_A	8299801	43	0	0
EnterStableSt_A	8299801	43	0	0
PulseIsPulse_A	8299801	43	0	0
StayInStableSt	8299801	45557	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8299801	6137	0	0
gen_low_level_sva.LowLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	89	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T82	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T153	0	2	0	0
T224	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	136556	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	18	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	12711	0	0
T40	0	52	0	0
T41	0	11	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	24	0	0
T82	0	58	0	0
T148	0	8822	0	0
T149	0	98	0	0
T153	0	55	0	0
T224	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623575	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	45628	0	0
T33	7622	0	0	0
T39	0	44	0	0
T40	18022	100	0	0
T41	0	57	0	0
T53	649	0	0	0
T63	494	0	0	0
T72	626	0	0	0
T82	0	82	0	0
T86	33077	0	0	0
T135	819	0	0	0
T136	526	0	0	0
T137	94455	0	0	0
T138	449	0	0	0
T148	0	41977	0	0
T149	0	43	0	0
T153	0	147	0	0
T154	0	43	0	0
T155	0	190	0	0
T224	0	257	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	43	0	0
T33	7622	0	0	0
T39	0	1	0	0
T40	18022	1	0	0
T41	0	1	0	0
T53	649	0	0	0
T63	494	0	0	0
T72	626	0	0	0
T82	0	2	0	0
T86	33077	0	0	0
T135	819	0	0	0
T136	526	0	0	0
T137	94455	0	0	0
T138	449	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T224	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7097513	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7099927	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	46	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T82	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0
T224	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	43	0	0
T33	7622	0	0	0
T39	0	1	0	0
T40	18022	1	0	0
T41	0	1	0	0
T53	649	0	0	0
T63	494	0	0	0
T72	626	0	0	0
T82	0	2	0	0
T86	33077	0	0	0
T135	819	0	0	0
T136	526	0	0	0
T137	94455	0	0	0
T138	449	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T224	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	43	0	0
T33	7622	0	0	0
T39	0	1	0	0
T40	18022	1	0	0
T41	0	1	0	0
T53	649	0	0	0
T63	494	0	0	0
T72	626	0	0	0
T82	0	2	0	0
T86	33077	0	0	0
T135	819	0	0	0
T136	526	0	0	0
T137	94455	0	0	0
T138	449	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T224	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	43	0	0
T33	7622	0	0	0
T39	0	1	0	0
T40	18022	1	0	0
T41	0	1	0	0
T53	649	0	0	0
T63	494	0	0	0
T72	626	0	0	0
T82	0	2	0	0
T86	33077	0	0	0
T135	819	0	0	0
T136	526	0	0	0
T137	94455	0	0	0
T138	449	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T224	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	45557	0	0
T33	7622	0	0	0
T39	0	42	0	0
T40	18022	99	0	0
T41	0	56	0	0
T53	649	0	0	0
T63	494	0	0	0
T72	626	0	0	0
T82	0	79	0	0
T86	33077	0	0	0
T135	819	0	0	0
T136	526	0	0	0
T137	94455	0	0	0
T138	449	0	0	0
T148	0	41975	0	0
T149	0	42	0	0
T153	0	145	0	0
T154	0	41	0	0
T155	0	189	0	0
T224	0	255	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	6137	0	0
T1	132641	12	0	0
T2	28822	13	0	0
T4	522	4	0	0
T5	8262	36	0	0
T6	444	5	0	0
T14	632	0	0	0
T15	426	3	0	0
T16	526	5	0	0
T17	504	5	0	0
T19	0	11	0	0
T22	527	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	15	0	0
T33	7622	0	0	0
T40	18022	1	0	0
T41	0	1	0	0
T53	649	0	0	0
T63	494	0	0	0
T72	626	0	0	0
T82	0	1	0	0
T86	33077	0	0	0
T113	0	1	0	0
T129	0	1	0	0
T135	819	0	0	0
T136	526	0	0	0
T137	94455	0	0	0
T138	449	0	0	0
T149	0	1	0	0
T155	0	1	0	0
T211	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T10,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T7,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T13
0	1	Covered	T213,T158,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T13
0	1	Covered	T13,T39,T149
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T13
1	-	Covered	T13,T39,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T9,T10
DetectSt	168	Covered	T9,T10,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T10,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T13
DebounceSt->IdleSt	163	Covered	T26,T44,T71
DetectSt->IdleSt	186	Covered	T213,T158,T78
DetectSt->StableSt	191	Covered	T9,T10,T13
IdleSt->DebounceSt	148	Covered	T26,T9,T10
StableSt->IdleSt	206	Covered	T13,T40,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T9,T10
0	1	Covered	T26,T9,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T149,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T213,T158,T78
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T39,T149
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	120	0	0
CntIncr_A	8299801	32922	0	0
CntNoWrap_A	8299801	7623544	0	0
DetectStDropOut_A	8299801	3	0	0
DetectedOut_A	8299801	60658	0	0
DetectedPulseOut_A	8299801	52	0	0
DisabledIdleSt_A	8299801	7507662	0	0
DisabledNoDetection_A	8299801	7510077	0	0
EnterDebounceSt_A	8299801	67	0	0
EnterDetectSt_A	8299801	55	0	0
EnterStableSt_A	8299801	52	0	0
PulseIsPulse_A	8299801	52	0	0
StayInStableSt	8299801	60580	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	120	0	0
T3	166236	0	0	0
T7	623	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T13	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T44	0	3	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T81	0	1	0	0
T149	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	32922	0	0
T3	166236	0	0	0
T7	623	0	0	0
T9	0	82	0	0
T10	0	64	0	0
T13	0	73	0	0
T26	6326	19	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	25422	0	0
T40	0	38	0	0
T44	0	170	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	25	0	0
T81	0	90	0	0
T149	0	196	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623544	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	3	0	0
T78	0	1	0	0
T157	40175	0	0	0
T158	0	1	0	0
T213	542	1	0	0
T216	489	0	0	0
T217	491	0	0	0
T218	7153	0	0	0
T219	522	0	0	0
T220	12990	0	0	0
T221	523	0	0	0
T222	711	0	0	0
T223	8206	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	60658	0	0
T9	1034	38	0	0
T10	602	128	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	127	0	0
T39	0	56239	0	0
T40	0	53	0	0
T44	0	195	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	342	0	0
T167	0	3	0	0
T179	504	0	0	0
T201	0	189	0	0
T224	0	257	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	52	0	0
T9	1034	1	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	1	0	0
T167	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T224	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7507662	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7510077	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	67	0	0
T3	166236	0	0	0
T7	623	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T13	0	1	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T44	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T81	0	1	0	0
T149	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	55	0	0
T9	1034	1	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	1	0	0
T167	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T224	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	52	0	0
T9	1034	1	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	1	0	0
T167	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T224	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	52	0	0
T9	1034	1	0	0
T10	602	1	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	1	0	0
T167	0	1	0	0
T179	504	0	0	0
T201	0	1	0	0
T224	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	60580	0	0
T9	1034	36	0	0
T10	602	126	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	126	0	0
T39	0	56236	0	0
T40	0	51	0	0
T44	0	193	0	0
T48	688	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T149	0	341	0	0
T167	0	2	0	0
T179	504	0	0	0
T201	0	188	0	0
T224	0	255	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	26	0	0
T13	3866	1	0	0
T32	15301	0	0	0
T34	12894	0	0	0
T39	0	1	0	0
T43	483	0	0	0
T61	1330	0	0	0
T108	406	0	0	0
T149	0	1	0	0
T156	526	0	0	0
T157	0	1	0	0
T167	0	1	0	0
T201	0	1	0	0
T207	0	1	0	0
T210	0	1	0	0
T227	0	1	0	0
T235	0	1	0	0
T236	402	0	0	0
T237	702	0	0	0
T238	711	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T8,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T8,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T7,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T8,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T44
0	1	Covered	T8,T39,T44
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T13,T44
1	-	Covered	T8,T39,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T8,T13
DetectSt	168	Covered	T8,T13,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T13,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T13,T39
DebounceSt->IdleSt	163	Covered	T26,T71
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T13,T39
IdleSt->DebounceSt	148	Covered	T26,T8,T13
StableSt->IdleSt	206	Covered	T8,T13,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T8,T13
0	1	Covered	T26,T8,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T8,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T13,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T8,T13
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T13,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T39,T44
StableSt	-	-	-	-	-	-	0	Covered	T8,T13,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	86	0	0
CntIncr_A	8299801	127954	0	0
CntNoWrap_A	8299801	7623578	0	0
DetectStDropOut_A	8299801	0	0	0
DetectedOut_A	8299801	3871	0	0
DetectedPulseOut_A	8299801	42	0	0
DisabledIdleSt_A	8299801	7161213	0	0
DisabledNoDetection_A	8299801	7163623	0	0
EnterDebounceSt_A	8299801	44	0	0
EnterDetectSt_A	8299801	42	0	0
EnterStableSt_A	8299801	42	0	0
PulseIsPulse_A	8299801	42	0	0
StayInStableSt	8299801	3805	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8299801	6937	0	0
gen_low_level_sva.LowLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	86	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	2	0	0
T13	0	2	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	2	0	0
T44	0	4	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T149	0	4	0	0
T154	0	2	0	0
T155	0	2	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	127954	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	66	0	0
T13	0	73	0	0
T26	6326	18	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	12711	0	0
T44	0	109	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	24	0	0
T149	0	196	0	0
T154	0	34	0	0
T155	0	94	0	0
T183	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7623578	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	3871	0	0
T8	1017	254	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	38	0	0
T39	0	1	0	0
T44	0	118	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T129	0	187	0	0
T149	0	82	0	0
T154	0	98	0	0
T155	0	38	0	0
T179	504	0	0	0
T183	0	100	0	0
T207	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	42	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T39	0	1	0	0
T44	0	2	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T129	0	2	0	0
T149	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0
T207	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7161213	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7163623	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	44	0	0
T3	166236	0	0	0
T7	623	0	0	0
T8	0	1	0	0
T13	0	1	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T39	0	1	0	0
T44	0	2	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T149	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	42	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T39	0	1	0	0
T44	0	2	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T129	0	2	0	0
T149	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0
T207	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	42	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T39	0	1	0	0
T44	0	2	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T129	0	2	0	0
T149	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0
T207	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	42	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	1	0	0
T39	0	1	0	0
T44	0	2	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T129	0	2	0	0
T149	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T179	504	0	0	0
T183	0	1	0	0
T207	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	3805	0	0
T8	1017	253	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T13	0	36	0	0
T44	0	116	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T104	402	0	0	0
T129	0	184	0	0
T149	0	79	0	0
T154	0	96	0	0
T155	0	36	0	0
T157	0	281	0	0
T179	504	0	0	0
T183	0	98	0	0
T207	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	6937	0	0
T1	132641	22	0	0
T2	28822	10	0	0
T4	522	7	0	0
T5	8262	28	0	0
T6	444	5	0	0
T14	632	3	0	0
T15	426	4	0	0
T16	526	5	0	0
T17	504	7	0	0
T22	527	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	18	0	0
T8	1017	1	0	0
T9	1034	0	0	0
T10	602	0	0	0
T11	12804	0	0	0
T12	216509	0	0	0
T39	0	1	0	0
T44	0	2	0	0
T48	688	0	0	0
T59	1289	0	0	0
T60	952	0	0	0
T76	0	1	0	0
T104	402	0	0	0
T129	0	1	0	0
T149	0	1	0	0
T158	0	1	0	0
T179	504	0	0	0
T211	0	1	0	0
T229	0	2	0	0
T239	0	1	0	0