Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T26,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T30
1	0	Covered	T5,T26,T34
1	1	Covered	T5,T26,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T30
0	1	Covered	T26,T30,T47
1	0	Covered	T26,T36,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T34
0	1	Covered	T5,T26,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T26,T34
1	-	Covered	T5,T26,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T26,T30
DetectSt	168	Covered	T5,T26,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T5,T26,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T26,T30
DebounceSt->IdleSt	163	Covered	T26,T71,T240
DetectSt->IdleSt	186	Covered	T26,T30,T47
DetectSt->StableSt	191	Covered	T5,T26,T34
IdleSt->DebounceSt	148	Covered	T5,T26,T30
StableSt->IdleSt	206	Covered	T5,T26,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T26,T30
0	1	Covered	T5,T26,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T26,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T26,T30
IdleSt	0	-	-	-	-	-	-	Covered	T5,T26,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T26,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T71,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T26,T30
DetectSt	-	-	-	-	1	-	-	Covered	T26,T30,T47
DetectSt	-	-	-	-	0	1	-	Covered	T5,T26,T34
DetectSt	-	-	-	-	0	0	-	Covered	T5,T26,T30
StableSt	-	-	-	-	-	-	1	Covered	T5,T26,T34
StableSt	-	-	-	-	-	-	0	Covered	T5,T26,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	2685	0	0
CntIncr_A	8299801	99305	0	0
CntNoWrap_A	8299801	7620979	0	0
DetectStDropOut_A	8299801	312	0	0
DetectedOut_A	8299801	73677	0	0
DetectedPulseOut_A	8299801	862	0	0
DisabledIdleSt_A	8299801	7146962	0	0
DisabledNoDetection_A	8299801	7149225	0	0
EnterDebounceSt_A	8299801	1361	0	0
EnterDetectSt_A	8299801	1325	0	0
EnterStableSt_A	8299801	862	0	0
PulseIsPulse_A	8299801	862	0	0
StayInStableSt	8299801	72695	0	0
gen_high_event_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	741	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2685	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	48	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	16	0	0
T30	0	50	0	0
T34	0	12	0	0
T36	0	22	0	0
T47	0	66	0	0
T50	0	2	0	0
T52	0	8	0	0
T68	0	2	0	0
T69	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	99305	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	1656	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	363	0	0
T30	0	1430	0	0
T34	0	300	0	0
T36	0	593	0	0
T47	0	1421	0	0
T50	0	21	0	0
T52	0	225	0	0
T68	0	21	0	0
T69	0	1185	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7620979	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7813	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	312	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	25	0	0
T36	0	5	0	0
T46	710	0	0	0
T47	4770	33	0	0
T52	0	4	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T90	0	12	0	0
T92	0	4	0	0
T93	0	1	0	0
T241	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	73677	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	455	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	265	0	0
T34	0	240	0	0
T50	0	40	0	0
T68	0	79	0	0
T69	0	484	0	0
T70	0	1982	0	0
T71	0	352	0	0
T242	0	1997	0	0
T243	0	2209	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	862	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	24	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	6	0	0
T50	0	1	0	0
T68	0	1	0	0
T69	0	15	0	0
T70	0	31	0	0
T71	0	5	0	0
T242	0	16	0	0
T243	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7146962	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	3308	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7149225	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	3308	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1361	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	24	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	9	0	0
T30	0	25	0	0
T34	0	6	0	0
T36	0	11	0	0
T47	0	33	0	0
T50	0	1	0	0
T52	0	4	0	0
T68	0	1	0	0
T69	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1325	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	24	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	7	0	0
T30	0	25	0	0
T34	0	6	0	0
T36	0	11	0	0
T47	0	33	0	0
T50	0	1	0	0
T52	0	4	0	0
T68	0	1	0	0
T69	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	862	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	24	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	6	0	0
T50	0	1	0	0
T68	0	1	0	0
T69	0	15	0	0
T70	0	31	0	0
T71	0	5	0	0
T242	0	16	0	0
T243	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	862	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	24	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	6	0	0
T50	0	1	0	0
T68	0	1	0	0
T69	0	15	0	0
T70	0	31	0	0
T71	0	5	0	0
T242	0	16	0	0
T243	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	72695	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	431	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	260	0	0
T34	0	234	0	0
T50	0	38	0	0
T68	0	77	0	0
T69	0	468	0	0
T70	0	1948	0	0
T71	0	347	0	0
T242	0	1979	0	0
T243	0	2180	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	741	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	24	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	6	0	0
T69	0	14	0	0
T70	0	28	0	0
T71	0	5	0	0
T242	0	14	0	0
T243	0	19	0	0
T244	0	25	0	0
T245	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T2,T20
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T20,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T20,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T20,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T20
1	0	Covered	T5,T1,T2
1	1	Covered	T2,T20,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T26
0	1	Covered	T11,T91,T94
1	0	Covered	T26,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T26
0	1	Covered	T2,T20,T32
1	0	Covered	T26,T71,T246

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T20,T26
1	-	Covered	T2,T20,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T20,T26
DetectSt	168	Covered	T2,T20,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T20,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T20,T26
DebounceSt->IdleSt	163	Covered	T2,T20,T26
DetectSt->IdleSt	186	Covered	T26,T11,T71
DetectSt->StableSt	191	Covered	T2,T20,T26
IdleSt->DebounceSt	148	Covered	T2,T20,T26
StableSt->IdleSt	206	Covered	T2,T20,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T20,T26
0	1	Covered	T2,T20,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T20,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T20,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T20,T11
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T20,T26
DetectSt	-	-	-	-	1	-	-	Covered	T26,T11,T71
DetectSt	-	-	-	-	0	1	-	Covered	T2,T20,T26
DetectSt	-	-	-	-	0	0	-	Covered	T2,T20,T26
StableSt	-	-	-	-	-	-	1	Covered	T2,T20,T26
StableSt	-	-	-	-	-	-	0	Covered	T2,T20,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	963	0	0
CntIncr_A	8299801	48571	0	0
CntNoWrap_A	8299801	7622701	0	0
DetectStDropOut_A	8299801	66	0	0
DetectedOut_A	8299801	17892	0	0
DetectedPulseOut_A	8299801	370	0	0
DisabledIdleSt_A	8299801	7228486	0	0
DisabledNoDetection_A	8299801	7230167	0	0
EnterDebounceSt_A	8299801	523	0	0
EnterDetectSt_A	8299801	440	0	0
EnterStableSt_A	8299801	370	0	0
PulseIsPulse_A	8299801	370	0	0
StayInStableSt	8299801	17490	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	334	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	963	0	0
T2	28822	22	0	0
T11	0	5	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	5	0	0
T21	502	0	0	0
T26	6326	8	0	0
T27	492	0	0	0
T32	0	4	0	0
T33	0	3	0	0
T35	0	10	0	0
T49	0	1	0	0
T50	0	1	0	0
T67	437	0	0	0
T86	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	48571	0	0
T2	28822	3755	0	0
T11	0	377	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	488	0	0
T21	502	0	0	0
T26	6326	124	0	0
T27	492	0	0	0
T32	0	236	0	0
T33	0	45	0	0
T35	0	450	0	0
T49	0	20	0	0
T50	0	20	0	0
T67	437	0	0	0
T86	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7622701	0	0
T1	132641	128133	0	0
T2	28822	28381	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	66	0	0
T11	12804	2	0	0
T12	216509	0	0	0
T13	3866	0	0	0
T48	688	0	0	0
T49	8660	0	0	0
T91	0	2	0	0
T94	0	5	0	0
T95	0	4	0	0
T96	0	1	0	0
T97	0	2	0	0
T98	0	3	0	0
T99	0	5	0	0
T100	0	11	0	0
T101	0	4	0	0
T104	402	0	0	0
T105	506	0	0	0
T106	891	0	0	0
T107	427	0	0	0
T108	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	17892	0	0
T2	28822	473	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	18	0	0
T21	502	0	0	0
T26	6326	74	0	0
T27	492	0	0	0
T32	0	129	0	0
T33	0	3	0	0
T35	0	382	0	0
T67	437	0	0	0
T68	0	3	0	0
T118	0	3	0	0
T119	0	229	0	0
T120	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	370	0	0
T2	28822	9	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	2	0	0
T21	502	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	5	0	0
T67	437	0	0	0
T68	0	1	0	0
T118	0	1	0	0
T119	0	5	0	0
T120	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7228486	0	0
T1	132641	128133	0	0
T2	28822	20147	0	0
T4	522	121	0	0
T5	8262	7406	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7230167	0	0
T1	132641	128145	0	0
T2	28822	20147	0	0
T4	522	122	0	0
T5	8262	7407	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	523	0	0
T2	28822	13	0	0
T11	0	3	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	3	0	0
T21	502	0	0	0
T26	6326	5	0	0
T27	492	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	5	0	0
T49	0	1	0	0
T50	0	1	0	0
T67	437	0	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	440	0	0
T2	28822	9	0	0
T11	0	2	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	2	0	0
T21	502	0	0	0
T26	6326	3	0	0
T27	492	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	5	0	0
T67	437	0	0	0
T118	0	1	0	0
T119	0	5	0	0
T120	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	370	0	0
T2	28822	9	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	2	0	0
T21	502	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	5	0	0
T67	437	0	0	0
T68	0	1	0	0
T118	0	1	0	0
T119	0	5	0	0
T120	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	370	0	0
T2	28822	9	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	2	0	0
T21	502	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	5	0	0
T67	437	0	0	0
T68	0	1	0	0
T118	0	1	0	0
T119	0	5	0	0
T120	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	17490	0	0
T2	28822	464	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	16	0	0
T21	502	0	0	0
T26	6326	73	0	0
T27	492	0	0	0
T32	0	127	0	0
T33	0	2	0	0
T35	0	377	0	0
T67	437	0	0	0
T68	0	2	0	0
T118	0	2	0	0
T119	0	224	0	0
T120	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	334	0	0
T2	28822	9	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	2	0	0
T21	502	0	0	0
T26	6326	0	0	0
T27	492	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	5	0	0
T67	437	0	0	0
T68	0	1	0	0
T70	0	4	0	0
T118	0	1	0	0
T119	0	5	0	0
T120	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T26,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T30
1	0	Covered	T5,T26,T34
1	1	Covered	T5,T26,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T30
0	1	Covered	T26,T30,T47
1	0	Covered	T26,T71,T242

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T34
0	1	Covered	T5,T26,T34
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T26,T34
1	-	Covered	T5,T26,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T26,T30
DetectSt	168	Covered	T5,T26,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T5,T26,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T26,T30
DebounceSt->IdleSt	163	Covered	T26,T71,T240
DetectSt->IdleSt	186	Covered	T26,T30,T47
DetectSt->StableSt	191	Covered	T5,T26,T34
IdleSt->DebounceSt	148	Covered	T5,T26,T30
StableSt->IdleSt	206	Covered	T5,T26,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T26,T30
0	1	Covered	T5,T26,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T26,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T26,T30
IdleSt	0	-	-	-	-	-	-	Covered	T5,T26,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T26,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T71,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T26,T30
DetectSt	-	-	-	-	1	-	-	Covered	T26,T30,T47
DetectSt	-	-	-	-	0	1	-	Covered	T5,T26,T34
DetectSt	-	-	-	-	0	0	-	Covered	T5,T26,T30
StableSt	-	-	-	-	-	-	1	Covered	T5,T26,T34
StableSt	-	-	-	-	-	-	0	Covered	T5,T26,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	2701	0	0
CntIncr_A	8299801	100866	0	0
CntNoWrap_A	8299801	7620963	0	0
DetectStDropOut_A	8299801	342	0	0
DetectedOut_A	8299801	73328	0	0
DetectedPulseOut_A	8299801	858	0	0
DisabledIdleSt_A	8299801	7147663	0	0
DisabledNoDetection_A	8299801	7149945	0	0
EnterDebounceSt_A	8299801	1372	0	0
EnterDetectSt_A	8299801	1330	0	0
EnterStableSt_A	8299801	858	0	0
PulseIsPulse_A	8299801	858	0	0
StayInStableSt	8299801	72369	0	0
gen_high_event_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	756	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2701	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	26	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	16	0	0
T30	0	14	0	0
T34	0	42	0	0
T36	0	30	0	0
T47	0	24	0	0
T52	0	10	0	0
T69	0	48	0	0
T70	0	50	0	0
T71	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	100866	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	871	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	344	0	0
T30	0	394	0	0
T34	0	1260	0	0
T36	0	750	0	0
T47	0	509	0	0
T52	0	282	0	0
T69	0	1656	0	0
T70	0	1125	0	0
T71	0	554	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7620963	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7835	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	342	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	7	0	0
T46	710	0	0	0
T47	4770	12	0	0
T52	0	5	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T92	0	7	0	0
T242	0	3	0	0
T243	0	6	0	0
T245	0	20	0	0
T247	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	73328	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	1520	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	277	0	0
T34	0	2383	0	0
T36	0	231	0	0
T69	0	2275	0	0
T70	0	1564	0	0
T71	0	374	0	0
T90	0	913	0	0
T93	0	812	0	0
T244	0	232	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	858	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	13	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	21	0	0
T36	0	15	0	0
T69	0	24	0	0
T70	0	25	0	0
T71	0	5	0	0
T90	0	4	0	0
T93	0	9	0	0
T244	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7147663	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	2100	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7149945	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	2100	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1372	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	13	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	9	0	0
T30	0	7	0	0
T34	0	21	0	0
T36	0	15	0	0
T47	0	12	0	0
T52	0	5	0	0
T69	0	24	0	0
T70	0	25	0	0
T71	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1330	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	13	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	7	0	0
T30	0	7	0	0
T34	0	21	0	0
T36	0	15	0	0
T47	0	12	0	0
T52	0	5	0	0
T69	0	24	0	0
T70	0	25	0	0
T71	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	858	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	13	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	21	0	0
T36	0	15	0	0
T69	0	24	0	0
T70	0	25	0	0
T71	0	5	0	0
T90	0	4	0	0
T93	0	9	0	0
T244	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	858	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	13	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	21	0	0
T36	0	15	0	0
T69	0	24	0	0
T70	0	25	0	0
T71	0	5	0	0
T90	0	4	0	0
T93	0	9	0	0
T244	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	72369	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	1507	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	272	0	0
T34	0	2360	0	0
T36	0	215	0	0
T69	0	2250	0	0
T70	0	1535	0	0
T71	0	369	0	0
T90	0	906	0	0
T93	0	802	0	0
T244	0	228	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	756	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	13	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	19	0	0
T36	0	14	0	0
T69	0	23	0	0
T70	0	21	0	0
T71	0	5	0	0
T90	0	1	0	0
T93	0	8	0	0
T244	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T2,T20
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T2,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T5,T2,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T2,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T20
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T2,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T20
0	1	Covered	T26,T120,T248
1	0	Covered	T26,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T20
0	1	Covered	T5,T2,T20
1	0	Covered	T71,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T2,T20
1	-	Covered	T5,T2,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T2,T20
DetectSt	168	Covered	T5,T2,T20
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T5,T2,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T2,T20
DebounceSt->IdleSt	163	Covered	T2,T20,T26
DetectSt->IdleSt	186	Covered	T26,T120,T71
DetectSt->StableSt	191	Covered	T5,T2,T20
IdleSt->DebounceSt	148	Covered	T5,T2,T20
StableSt->IdleSt	206	Covered	T5,T2,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T2,T20
0	1	Covered	T5,T2,T20
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T2,T20
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T2,T20
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T2,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T20,T11
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T2,T20
DetectSt	-	-	-	-	1	-	-	Covered	T26,T120,T71
DetectSt	-	-	-	-	0	1	-	Covered	T5,T2,T20
DetectSt	-	-	-	-	0	0	-	Covered	T5,T2,T20
StableSt	-	-	-	-	-	-	1	Covered	T5,T2,T20
StableSt	-	-	-	-	-	-	0	Covered	T5,T2,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	831	0	0
CntIncr_A	8299801	48575	0	0
CntNoWrap_A	8299801	7622833	0	0
DetectStDropOut_A	8299801	62	0	0
DetectedOut_A	8299801	15072	0	0
DetectedPulseOut_A	8299801	326	0	0
DisabledIdleSt_A	8299801	7234619	0	0
DisabledNoDetection_A	8299801	7236381	0	0
EnterDebounceSt_A	8299801	440	0	0
EnterDetectSt_A	8299801	391	0	0
EnterStableSt_A	8299801	326	0	0
PulseIsPulse_A	8299801	326	0	0
StayInStableSt	8299801	14726	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	303	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	831	0	0
T1	132641	0	0	0
T2	28822	11	0	0
T5	8262	10	0	0
T6	444	0	0	0
T11	0	7	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T20	0	9	0	0
T22	527	0	0	0
T26	0	8	0	0
T32	0	2	0	0
T34	0	4	0	0
T35	0	14	0	0
T86	0	3	0	0
T119	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	48575	0	0
T1	132641	0	0	0
T2	28822	1826	0	0
T5	8262	345	0	0
T6	444	0	0	0
T11	0	469	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T20	0	574	0	0
T22	527	0	0	0
T26	0	133	0	0
T32	0	137	0	0
T34	0	126	0	0
T35	0	651	0	0
T86	0	195	0	0
T119	0	119	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7622833	0	0
T1	132641	128133	0	0
T2	28822	28392	0	0
T4	522	121	0	0
T5	8262	7851	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	62	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	0	0	0
T46	710	0	0	0
T47	4770	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T91	0	5	0	0
T97	0	1	0	0
T120	0	3	0	0
T158	0	2	0	0
T207	0	7	0	0
T248	0	4	0	0
T249	0	9	0	0
T250	0	1	0	0
T251	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	15072	0	0
T1	132641	0	0	0
T2	28822	192	0	0
T5	8262	265	0	0
T6	444	0	0	0
T11	0	52	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T20	0	347	0	0
T22	527	0	0	0
T26	0	73	0	0
T32	0	45	0	0
T34	0	153	0	0
T35	0	515	0	0
T86	0	53	0	0
T119	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	326	0	0
T1	132641	0	0	0
T2	28822	5	0	0
T5	8262	5	0	0
T6	444	0	0	0
T11	0	3	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T20	0	4	0	0
T22	527	0	0	0
T26	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	7	0	0
T86	0	1	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7234619	0	0
T1	132641	128133	0	0
T2	28822	20147	0	0
T4	522	121	0	0
T5	8262	6341	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7236381	0	0
T1	132641	128145	0	0
T2	28822	20147	0	0
T4	522	122	0	0
T5	8262	6342	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	440	0	0
T1	132641	0	0	0
T2	28822	6	0	0
T5	8262	5	0	0
T6	444	0	0	0
T11	0	4	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T20	0	5	0	0
T22	527	0	0	0
T26	0	5	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	7	0	0
T86	0	2	0	0
T119	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	391	0	0
T1	132641	0	0	0
T2	28822	5	0	0
T5	8262	5	0	0
T6	444	0	0	0
T11	0	3	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T20	0	4	0	0
T22	527	0	0	0
T26	0	3	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	7	0	0
T86	0	1	0	0
T119	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	326	0	0
T1	132641	0	0	0
T2	28822	5	0	0
T5	8262	5	0	0
T6	444	0	0	0
T11	0	3	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T20	0	4	0	0
T22	527	0	0	0
T26	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	7	0	0
T86	0	1	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	326	0	0
T1	132641	0	0	0
T2	28822	5	0	0
T5	8262	5	0	0
T6	444	0	0	0
T11	0	3	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T20	0	4	0	0
T22	527	0	0	0
T26	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	7	0	0
T86	0	1	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	14726	0	0
T1	132641	0	0	0
T2	28822	187	0	0
T5	8262	260	0	0
T6	444	0	0	0
T11	0	49	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T20	0	343	0	0
T22	527	0	0	0
T26	0	72	0	0
T32	0	44	0	0
T34	0	151	0	0
T35	0	508	0	0
T86	0	52	0	0
T119	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	303	0	0
T1	132641	0	0	0
T2	28822	5	0	0
T5	8262	5	0	0
T6	444	0	0	0
T11	0	3	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T20	0	4	0	0
T22	527	0	0	0
T26	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	7	0	0
T86	0	1	0	0
T119	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T26,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T30
1	0	Covered	T5,T26,T34
1	1	Covered	T5,T26,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T30
0	1	Covered	T26,T30,T47
1	0	Covered	T26,T71,T242

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T34
0	1	Covered	T5,T26,T34
1	0	Covered	T26,T80,T252

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T26,T34
1	-	Covered	T5,T26,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T26,T30
DetectSt	168	Covered	T5,T26,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T5,T26,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T26,T30
DebounceSt->IdleSt	163	Covered	T26,T71,T240
DetectSt->IdleSt	186	Covered	T26,T30,T47
DetectSt->StableSt	191	Covered	T5,T26,T34
IdleSt->DebounceSt	148	Covered	T5,T26,T30
StableSt->IdleSt	206	Covered	T5,T26,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T26,T30
0	1	Covered	T5,T26,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T26,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T26,T30
IdleSt	0	-	-	-	-	-	-	Covered	T5,T26,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T26,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T71,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T26,T30
DetectSt	-	-	-	-	1	-	-	Covered	T26,T30,T47
DetectSt	-	-	-	-	0	1	-	Covered	T5,T26,T34
DetectSt	-	-	-	-	0	0	-	Covered	T5,T26,T30
StableSt	-	-	-	-	-	-	1	Covered	T5,T26,T34
StableSt	-	-	-	-	-	-	0	Covered	T5,T26,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	2885	0	0
CntIncr_A	8299801	111398	0	0
CntNoWrap_A	8299801	7620779	0	0
DetectStDropOut_A	8299801	317	0	0
DetectedOut_A	8299801	93519	0	0
DetectedPulseOut_A	8299801	964	0	0
DisabledIdleSt_A	8299801	7129702	0	0
DisabledNoDetection_A	8299801	7131963	0	0
EnterDebounceSt_A	8299801	1462	0	0
EnterDetectSt_A	8299801	1424	0	0
EnterStableSt_A	8299801	964	0	0
PulseIsPulse_A	8299801	964	0	0
StayInStableSt	8299801	92433	0	0
gen_high_event_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	837	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2885	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	56	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	16	0	0
T30	0	50	0	0
T34	0	24	0	0
T36	0	40	0	0
T47	0	24	0	0
T52	0	18	0	0
T69	0	28	0	0
T70	0	62	0	0
T71	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	111398	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	2128	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	447	0	0
T30	0	1425	0	0
T34	0	960	0	0
T36	0	820	0	0
T47	0	509	0	0
T52	0	506	0	0
T69	0	952	0	0
T70	0	1829	0	0
T71	0	540	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7620779	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7805	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	317	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	25	0	0
T46	710	0	0	0
T47	4770	12	0	0
T52	0	9	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T75	0	14	0	0
T90	0	2	0	0
T93	0	3	0	0
T243	0	15	0	0
T245	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	93519	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	1590	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	353	0	0
T34	0	124	0	0
T36	0	2285	0	0
T69	0	483	0	0
T70	0	1703	0	0
T71	0	275	0	0
T92	0	1259	0	0
T241	0	832	0	0
T244	0	790	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	964	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	28	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	12	0	0
T36	0	20	0	0
T69	0	14	0	0
T70	0	31	0	0
T71	0	5	0	0
T92	0	8	0	0
T241	0	9	0	0
T244	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7129702	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	2047	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7131963	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	2047	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1462	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	28	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	9	0	0
T30	0	25	0	0
T34	0	12	0	0
T36	0	20	0	0
T47	0	12	0	0
T52	0	9	0	0
T69	0	14	0	0
T70	0	31	0	0
T71	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1424	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	28	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	7	0	0
T30	0	25	0	0
T34	0	12	0	0
T36	0	20	0	0
T47	0	12	0	0
T52	0	9	0	0
T69	0	14	0	0
T70	0	31	0	0
T71	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	964	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	28	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	12	0	0
T36	0	20	0	0
T69	0	14	0	0
T70	0	31	0	0
T71	0	5	0	0
T92	0	8	0	0
T241	0	9	0	0
T244	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	964	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	28	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	12	0	0
T36	0	20	0	0
T69	0	14	0	0
T70	0	31	0	0
T71	0	5	0	0
T92	0	8	0	0
T241	0	9	0	0
T244	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	92433	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	1562	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	348	0	0
T34	0	112	0	0
T36	0	2261	0	0
T69	0	469	0	0
T70	0	1669	0	0
T71	0	270	0	0
T92	0	1245	0	0
T241	0	821	0	0
T244	0	763	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	837	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	28	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	4	0	0
T34	0	12	0	0
T36	0	16	0	0
T69	0	14	0	0
T70	0	28	0	0
T71	0	5	0	0
T92	0	2	0	0
T241	0	7	0	0
T244	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T2,T20
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T20,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T20,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T20,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T20
1	0	Covered	T5,T1,T2
1	1	Covered	T2,T20,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T26
0	1	Covered	T2,T119,T253
1	0	Covered	T26,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T26,T11
0	1	Covered	T20,T26,T11
1	0	Covered	T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T26,T11
1	-	Covered	T20,T26,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T20,T26
DetectSt	168	Covered	T2,T20,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T20,T26,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T20,T26
DebounceSt->IdleSt	163	Covered	T26,T35,T86
DetectSt->IdleSt	186	Covered	T2,T26,T119
DetectSt->StableSt	191	Covered	T20,T26,T11
IdleSt->DebounceSt	148	Covered	T2,T20,T26
StableSt->IdleSt	206	Covered	T20,T26,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T20,T26
0	1	Covered	T2,T20,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T20,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T20,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T86,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T20,T26
DetectSt	-	-	-	-	1	-	-	Covered	T2,T26,T119
DetectSt	-	-	-	-	0	1	-	Covered	T20,T26,T11
DetectSt	-	-	-	-	0	0	-	Covered	T2,T20,T26
StableSt	-	-	-	-	-	-	1	Covered	T20,T26,T11
StableSt	-	-	-	-	-	-	0	Covered	T20,T26,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	945	0	0
CntIncr_A	8299801	55433	0	0
CntNoWrap_A	8299801	7622719	0	0
DetectStDropOut_A	8299801	40	0	0
DetectedOut_A	8299801	17503	0	0
DetectedPulseOut_A	8299801	398	0	0
DisabledIdleSt_A	8299801	7226933	0	0
DisabledNoDetection_A	8299801	7228695	0	0
EnterDebounceSt_A	8299801	503	0	0
EnterDetectSt_A	8299801	442	0	0
EnterStableSt_A	8299801	398	0	0
PulseIsPulse_A	8299801	398	0	0
StayInStableSt	8299801	17083	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	374	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	945	0	0
T2	28822	2	0	0
T11	0	2	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	22	0	0
T21	502	0	0	0
T26	6326	8	0	0
T27	492	0	0	0
T32	0	4	0	0
T35	0	11	0	0
T36	0	8	0	0
T67	437	0	0	0
T86	0	26	0	0
T119	0	10	0	0
T120	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	55433	0	0
T2	28822	350	0	0
T11	0	133	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	2079	0	0
T21	502	0	0	0
T26	6326	209	0	0
T27	492	0	0	0
T32	0	352	0	0
T35	0	803	0	0
T36	0	216	0	0
T67	437	0	0	0
T86	0	1850	0	0
T119	0	554	0	0
T120	0	323	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7622719	0	0
T1	132641	128133	0	0
T2	28822	28401	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	40	0	0
T2	28822	1	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	0	0	0
T21	502	0	0	0
T26	6326	0	0	0
T27	492	0	0	0
T67	437	0	0	0
T77	0	1	0	0
T99	0	4	0	0
T101	0	4	0	0
T119	0	4	0	0
T251	0	5	0	0
T253	0	2	0	0
T254	0	1	0	0
T255	0	10	0	0
T256	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	17503	0	0
T3	166236	0	0	0
T11	0	10	0	0
T20	35564	212	0	0
T21	502	0	0	0
T26	6326	74	0	0
T27	492	0	0	0
T32	0	12	0	0
T35	0	83	0	0
T36	0	327	0	0
T37	0	155	0	0
T46	710	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T67	437	0	0	0
T70	0	140	0	0
T86	0	351	0	0
T120	0	107	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	398	0	0
T3	166236	0	0	0
T11	0	1	0	0
T20	35564	11	0	0
T21	502	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T32	0	2	0	0
T35	0	5	0	0
T36	0	4	0	0
T37	0	3	0	0
T46	710	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T67	437	0	0	0
T70	0	3	0	0
T86	0	12	0	0
T120	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7226933	0	0
T1	132641	128133	0	0
T2	28822	20147	0	0
T4	522	121	0	0
T5	8262	6271	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7228695	0	0
T1	132641	128145	0	0
T2	28822	20147	0	0
T4	522	122	0	0
T5	8262	6272	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	503	0	0
T2	28822	1	0	0
T11	0	1	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	11	0	0
T21	502	0	0	0
T26	6326	5	0	0
T27	492	0	0	0
T32	0	2	0	0
T35	0	6	0	0
T36	0	4	0	0
T67	437	0	0	0
T86	0	14	0	0
T119	0	6	0	0
T120	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	442	0	0
T2	28822	1	0	0
T11	0	1	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	11	0	0
T21	502	0	0	0
T26	6326	3	0	0
T27	492	0	0	0
T32	0	2	0	0
T35	0	5	0	0
T36	0	4	0	0
T67	437	0	0	0
T86	0	12	0	0
T119	0	4	0	0
T120	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	398	0	0
T3	166236	0	0	0
T11	0	1	0	0
T20	35564	11	0	0
T21	502	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T32	0	2	0	0
T35	0	5	0	0
T36	0	4	0	0
T37	0	3	0	0
T46	710	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T67	437	0	0	0
T70	0	3	0	0
T86	0	12	0	0
T120	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	398	0	0
T3	166236	0	0	0
T11	0	1	0	0
T20	35564	11	0	0
T21	502	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T32	0	2	0	0
T35	0	5	0	0
T36	0	4	0	0
T37	0	3	0	0
T46	710	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T67	437	0	0	0
T70	0	3	0	0
T86	0	12	0	0
T120	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	17083	0	0
T3	166236	0	0	0
T11	0	9	0	0
T20	35564	201	0	0
T21	502	0	0	0
T26	6326	73	0	0
T27	492	0	0	0
T32	0	10	0	0
T35	0	78	0	0
T36	0	323	0	0
T37	0	152	0	0
T46	710	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T67	437	0	0	0
T70	0	137	0	0
T86	0	339	0	0
T120	0	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	374	0	0
T3	166236	0	0	0
T11	0	1	0	0
T20	35564	11	0	0
T21	502	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T32	0	2	0	0
T35	0	5	0	0
T36	0	4	0	0
T37	0	3	0	0
T46	710	0	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T67	437	0	0	0
T70	0	3	0	0
T86	0	12	0	0
T120	0	3	0	0