Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T26,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T30
1	0	Covered	T5,T26,T34
1	1	Covered	T5,T26,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T30
0	1	Covered	T26,T30,T47
1	0	Covered	T26,T36,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T34
0	1	Covered	T5,T26,T34
1	0	Covered	T257

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T26,T34
1	-	Covered	T5,T26,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T26,T30
DetectSt	168	Covered	T5,T26,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T5,T26,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T26,T30
DebounceSt->IdleSt	163	Covered	T26,T71,T240
DetectSt->IdleSt	186	Covered	T26,T30,T47
DetectSt->StableSt	191	Covered	T5,T26,T34
IdleSt->DebounceSt	148	Covered	T5,T26,T30
StableSt->IdleSt	206	Covered	T5,T26,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T26,T30
0	1	Covered	T5,T26,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T26,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T26,T30
IdleSt	0	-	-	-	-	-	-	Covered	T5,T26,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T26,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T71,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T26,T30
DetectSt	-	-	-	-	1	-	-	Covered	T26,T30,T47
DetectSt	-	-	-	-	0	1	-	Covered	T5,T26,T34
DetectSt	-	-	-	-	0	0	-	Covered	T5,T26,T30
StableSt	-	-	-	-	-	-	1	Covered	T5,T26,T34
StableSt	-	-	-	-	-	-	0	Covered	T5,T26,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	2845	0	0
CntIncr_A	8299801	103350	0	0
CntNoWrap_A	8299801	7620819	0	0
DetectStDropOut_A	8299801	439	0	0
DetectedOut_A	8299801	73156	0	0
DetectedPulseOut_A	8299801	759	0	0
DisabledIdleSt_A	8299801	7148306	0	0
DisabledNoDetection_A	8299801	7150605	0	0
EnterDebounceSt_A	8299801	1433	0	0
EnterDetectSt_A	8299801	1412	0	0
EnterStableSt_A	8299801	759	0	0
PulseIsPulse_A	8299801	759	0	0
StayInStableSt	8299801	72312	0	0
gen_high_event_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	664	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	2845	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	10	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	16	0	0
T30	0	30	0	0
T34	0	10	0	0
T36	0	26	0	0
T47	0	46	0	0
T52	0	46	0	0
T69	0	8	0	0
T70	0	54	0	0
T71	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	103350	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	370	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	406	0	0
T30	0	853	0	0
T34	0	415	0	0
T36	0	707	0	0
T47	0	990	0	0
T52	0	1307	0	0
T69	0	280	0	0
T70	0	1890	0	0
T71	0	295	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7620819	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	7851	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	439	0	0
T3	166236	0	0	0
T7	623	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T30	5466	15	0	0
T36	0	2	0	0
T46	710	0	0	0
T47	4770	23	0	0
T52	0	23	0	0
T54	2737	0	0	0
T55	505	0	0	0
T56	507	0	0	0
T71	0	1	0	0
T75	0	6	0	0
T90	0	20	0	0
T92	0	23	0	0
T242	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	73156	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	65	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	272	0	0
T34	0	36	0	0
T69	0	128	0	0
T70	0	952	0	0
T71	0	363	0	0
T93	0	545	0	0
T241	0	3285	0	0
T244	0	1053	0	0
T245	0	1624	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	759	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	5	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	5	0	0
T69	0	4	0	0
T70	0	27	0	0
T71	0	5	0	0
T93	0	8	0	0
T241	0	23	0	0
T244	0	26	0	0
T245	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7148306	0	0
T1	132641	128133	0	0
T2	28822	28403	0	0
T4	522	121	0	0
T5	8262	3387	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7150605	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	3387	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1433	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	5	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	9	0	0
T30	0	15	0	0
T34	0	5	0	0
T36	0	13	0	0
T47	0	23	0	0
T52	0	23	0	0
T69	0	4	0	0
T70	0	27	0	0
T71	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	1412	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	5	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	7	0	0
T30	0	15	0	0
T34	0	5	0	0
T36	0	13	0	0
T47	0	23	0	0
T52	0	23	0	0
T69	0	4	0	0
T70	0	27	0	0
T71	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	759	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	5	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	5	0	0
T69	0	4	0	0
T70	0	27	0	0
T71	0	5	0	0
T93	0	8	0	0
T241	0	23	0	0
T244	0	26	0	0
T245	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	759	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	5	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	5	0	0
T69	0	4	0	0
T70	0	27	0	0
T71	0	5	0	0
T93	0	8	0	0
T241	0	23	0	0
T244	0	26	0	0
T245	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	72312	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	60	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	267	0	0
T34	0	31	0	0
T69	0	124	0	0
T70	0	922	0	0
T71	0	358	0	0
T93	0	535	0	0
T241	0	3257	0	0
T244	0	1026	0	0
T245	0	1615	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	664	0	0
T1	132641	0	0	0
T2	28822	0	0	0
T5	8262	5	0	0
T6	444	0	0	0
T14	632	0	0	0
T15	426	0	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T22	527	0	0	0
T26	0	5	0	0
T34	0	5	0	0
T69	0	4	0	0
T70	0	24	0	0
T71	0	5	0	0
T93	0	6	0	0
T241	0	18	0	0
T244	0	25	0	0
T245	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T2,T20
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T20,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T20,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T20,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T20
1	0	Covered	T5,T1,T2
1	1	Covered	T2,T20,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T26
0	1	Covered	T32,T119,T248
1	0	Covered	T26,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T26
0	1	Covered	T2,T20,T11
1	0	Covered	T26,T258

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T20,T26
1	-	Covered	T2,T20,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T20,T26
DetectSt	168	Covered	T2,T20,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T20,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T20,T26
DebounceSt->IdleSt	163	Covered	T2,T26,T11
DetectSt->IdleSt	186	Covered	T26,T32,T119
DetectSt->StableSt	191	Covered	T2,T20,T26
IdleSt->DebounceSt	148	Covered	T2,T20,T26
StableSt->IdleSt	206	Covered	T2,T20,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T20,T26
0	1	Covered	T2,T20,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T20,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T20,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T11,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T20,T26
DetectSt	-	-	-	-	1	-	-	Covered	T26,T32,T119
DetectSt	-	-	-	-	0	1	-	Covered	T2,T20,T26
DetectSt	-	-	-	-	0	0	-	Covered	T2,T20,T26
StableSt	-	-	-	-	-	-	1	Covered	T2,T20,T26
StableSt	-	-	-	-	-	-	0	Covered	T2,T20,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8299801	840	0	0
CntIncr_A	8299801	45394	0	0
CntNoWrap_A	8299801	7622824	0	0
DetectStDropOut_A	8299801	61	0	0
DetectedOut_A	8299801	15829	0	0
DetectedPulseOut_A	8299801	330	0	0
DisabledIdleSt_A	8299801	7243783	0	0
DisabledNoDetection_A	8299801	7245590	0	0
EnterDebounceSt_A	8299801	445	0	0
EnterDetectSt_A	8299801	395	0	0
EnterStableSt_A	8299801	330	0	0
PulseIsPulse_A	8299801	330	0	0
StayInStableSt	8299801	15475	0	0
gen_high_level_sva.HighLevelEvent_A	8299801	7626136	0	0
gen_not_sticky_sva.StableStDropOut_A	8299801	303	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	840	0	0
T2	28822	4	0	0
T11	0	7	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	24	0	0
T21	502	0	0	0
T26	6326	8	0	0
T27	492	0	0	0
T32	0	14	0	0
T35	0	12	0	0
T37	0	6	0	0
T67	437	0	0	0
T70	0	6	0	0
T119	0	5	0	0
T120	0	19	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	45394	0	0
T2	28822	863	0	0
T11	0	445	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	1404	0	0
T21	502	0	0	0
T26	6326	131	0	0
T27	492	0	0	0
T32	0	1278	0	0
T35	0	594	0	0
T37	0	285	0	0
T67	437	0	0	0
T70	0	96	0	0
T119	0	277	0	0
T120	0	1106	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7622824	0	0
T1	132641	128133	0	0
T2	28822	28399	0	0
T4	522	121	0	0
T5	8262	7861	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	61	0	0
T32	15301	7	0	0
T34	12894	0	0	0
T35	22972	0	0	0
T42	563	0	0	0
T43	483	0	0	0
T50	466	0	0	0
T58	1262	0	0	0
T91	0	2	0	0
T96	0	6	0	0
T119	0	2	0	0
T125	0	5	0	0
T142	417	0	0	0
T143	504	0	0	0
T156	526	0	0	0
T239	0	1	0	0
T248	0	2	0	0
T251	0	6	0	0
T254	0	5	0	0
T259	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	15829	0	0
T2	28822	20	0	0
T11	0	75	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	1097	0	0
T21	502	0	0	0
T26	6326	74	0	0
T27	492	0	0	0
T35	0	403	0	0
T37	0	36	0	0
T38	0	104	0	0
T67	437	0	0	0
T70	0	216	0	0
T71	0	76	0	0
T120	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	330	0	0
T2	28822	1	0	0
T11	0	3	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	12	0	0
T21	502	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T35	0	6	0	0
T37	0	3	0	0
T38	0	3	0	0
T67	437	0	0	0
T70	0	3	0	0
T71	0	1	0	0
T120	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7243783	0	0
T1	132641	128133	0	0
T2	28822	20147	0	0
T4	522	121	0	0
T5	8262	7796	0	0
T6	444	43	0	0
T14	632	231	0	0
T15	426	25	0	0
T16	526	125	0	0
T17	504	103	0	0
T22	527	126	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7245590	0	0
T1	132641	128145	0	0
T2	28822	20147	0	0
T4	522	122	0	0
T5	8262	7797	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	445	0	0
T2	28822	3	0	0
T11	0	4	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	12	0	0
T21	502	0	0	0
T26	6326	5	0	0
T27	492	0	0	0
T32	0	7	0	0
T35	0	6	0	0
T37	0	3	0	0
T67	437	0	0	0
T70	0	3	0	0
T119	0	3	0	0
T120	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	395	0	0
T2	28822	1	0	0
T11	0	3	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	12	0	0
T21	502	0	0	0
T26	6326	3	0	0
T27	492	0	0	0
T32	0	7	0	0
T35	0	6	0	0
T37	0	3	0	0
T67	437	0	0	0
T70	0	3	0	0
T119	0	2	0	0
T120	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	330	0	0
T2	28822	1	0	0
T11	0	3	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	12	0	0
T21	502	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T35	0	6	0	0
T37	0	3	0	0
T38	0	3	0	0
T67	437	0	0	0
T70	0	3	0	0
T71	0	1	0	0
T120	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	330	0	0
T2	28822	1	0	0
T11	0	3	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	12	0	0
T21	502	0	0	0
T26	6326	1	0	0
T27	492	0	0	0
T35	0	6	0	0
T37	0	3	0	0
T38	0	3	0	0
T67	437	0	0	0
T70	0	3	0	0
T71	0	1	0	0
T120	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	15475	0	0
T2	28822	19	0	0
T11	0	72	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	1085	0	0
T21	502	0	0	0
T26	6326	73	0	0
T27	492	0	0	0
T35	0	397	0	0
T37	0	33	0	0
T38	0	101	0	0
T67	437	0	0	0
T70	0	210	0	0
T71	0	75	0	0
T120	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	7626136	0	0
T1	132641	128145	0	0
T2	28822	28413	0	0
T4	522	122	0	0
T5	8262	7862	0	0
T6	444	44	0	0
T14	632	232	0	0
T15	426	26	0	0
T16	526	126	0	0
T17	504	104	0	0
T22	527	127	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8299801	303	0	0
T2	28822	1	0	0
T11	0	3	0	0
T16	526	0	0	0
T17	504	0	0	0
T18	550	0	0	0
T19	2817	0	0	0
T20	35564	12	0	0
T21	502	0	0	0
T26	6326	0	0	0
T27	492	0	0	0
T35	0	6	0	0
T37	0	3	0	0
T38	0	3	0	0
T67	437	0	0	0
T93	0	2	0	0
T120	0	9	0	0
T124	0	2	0	0
T244	0	1	0	0