Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1535642565	13982	0	0
auto_block_debounce_ctl_rd_A	1535642565	2365	0	0
auto_block_out_ctl_rd_A	1535642565	2800	0	0
com_det_ctl_0_rd_A	1535642565	4184	0	0
com_det_ctl_1_rd_A	1535642565	4610	0	0
com_det_ctl_2_rd_A	1535642565	4563	0	0
com_det_ctl_3_rd_A	1535642565	4402	0	0
com_out_ctl_0_rd_A	1535642565	4769	0	0
com_out_ctl_1_rd_A	1535642565	4990	0	0
com_out_ctl_2_rd_A	1535642565	5092	0	0
com_out_ctl_3_rd_A	1535642565	4897	0	0
com_pre_det_ctl_0_rd_A	1535642565	1803	0	0
com_pre_det_ctl_1_rd_A	1535642565	1816	0	0
com_pre_det_ctl_2_rd_A	1535642565	1707	0	0
com_pre_det_ctl_3_rd_A	1535642565	1909	0	0
com_pre_sel_ctl_0_rd_A	1535642565	5272	0	0
com_pre_sel_ctl_1_rd_A	1535642565	5265	0	0
com_pre_sel_ctl_2_rd_A	1535642565	5412	0	0
com_pre_sel_ctl_3_rd_A	1535642565	5306	0	0
com_sel_ctl_0_rd_A	1535642565	5110	0	0
com_sel_ctl_1_rd_A	1535642565	5280	0	0
com_sel_ctl_2_rd_A	1535642565	4955	0	0
com_sel_ctl_3_rd_A	1535642565	5393	0	0
ec_rst_ctl_rd_A	1535642565	2949	0	0
intr_enable_rd_A	1535642565	2349	0	0
key_intr_ctl_rd_A	1535642565	4145	0	0
key_intr_debounce_ctl_rd_A	1535642565	1748	0	0
key_invert_ctl_rd_A	1535642565	5110	0	0
pin_allowed_ctl_rd_A	1535642565	6280	0	0
pin_out_ctl_rd_A	1535642565	4886	0	0
pin_out_value_rd_A	1535642565	5302	0	0
regwen_rd_A	1535642565	2024	0	0
ulp_ac_debounce_ctl_rd_A	1535642565	2061	0	0
ulp_ctl_rd_A	1535642565	2015	0	0
ulp_lid_debounce_ctl_rd_A	1535642565	1988	0	0
ulp_pwrb_debounce_ctl_rd_A	1535642565	1964	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	13982	0	0
T1	125121	3	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T33	0	9	0	0
T44	0	12	0	0
T49	0	12	0	0
T66	0	22	0	0
T81	0	17	0	0
T83	0	3	0	0
T125	0	4	0	0
T266	0	16	0	0
T287	0	11	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	2365	0	0
T1	125121	15	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T40	0	11	0	0
T46	0	8	0	0
T48	0	9	0	0
T51	0	9	0	0
T81	0	72	0	0
T83	0	5	0	0
T87	0	8	0	0
T125	0	14	0	0
T288	0	21	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	2800	0	0
T1	125121	21	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T40	0	26	0	0
T46	0	6	0	0
T48	0	11	0	0
T51	0	8	0	0
T81	0	61	0	0
T83	0	2	0	0
T87	0	16	0	0
T125	0	22	0	0
T289	0	4	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	4184	0	0
T1	125121	12	0	0
T2	138344	0	0	0
T5	950254	40	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	49	0	0
T35	0	63	0	0
T37	0	68	0	0
T91	0	44	0	0
T119	0	68	0	0
T120	0	35	0	0
T242	0	47	0	0
T248	0	54	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	4610	0	0
T1	125121	7	0	0
T2	138344	0	0	0
T5	950254	53	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	75	0	0
T35	0	50	0	0
T37	0	43	0	0
T91	0	88	0	0
T119	0	59	0	0
T120	0	72	0	0
T242	0	42	0	0
T248	0	67	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	4563	0	0
T1	125121	13	0	0
T2	138344	0	0	0
T5	950254	54	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	78	0	0
T35	0	36	0	0
T37	0	57	0	0
T91	0	67	0	0
T119	0	74	0	0
T120	0	47	0	0
T242	0	34	0	0
T248	0	82	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	4402	0	0
T1	125121	9	0	0
T2	138344	0	0	0
T5	950254	41	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	59	0	0
T35	0	37	0	0
T37	0	62	0	0
T91	0	55	0	0
T119	0	72	0	0
T120	0	16	0	0
T242	0	44	0	0
T248	0	80	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	4769	0	0
T1	125121	12	0	0
T2	138344	0	0	0
T5	950254	28	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	68	0	0
T35	0	35	0	0
T37	0	97	0	0
T91	0	79	0	0
T119	0	72	0	0
T120	0	47	0	0
T242	0	61	0	0
T248	0	49	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	4990	0	0
T1	125121	1	0	0
T2	138344	0	0	0
T5	950254	24	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	79	0	0
T35	0	46	0	0
T37	0	77	0	0
T91	0	79	0	0
T119	0	78	0	0
T120	0	48	0	0
T242	0	52	0	0
T248	0	59	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	5092	0	0
T1	125121	17	0	0
T2	138344	0	0	0
T5	950254	40	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	69	0	0
T35	0	32	0	0
T37	0	75	0	0
T91	0	69	0	0
T119	0	73	0	0
T120	0	24	0	0
T242	0	40	0	0
T248	0	51	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	4897	0	0
T1	125121	15	0	0
T2	138344	0	0	0
T5	950254	33	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	66	0	0
T35	0	37	0	0
T37	0	75	0	0
T91	0	76	0	0
T119	0	50	0	0
T120	0	24	0	0
T242	0	46	0	0
T248	0	51	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	1803	0	0
T1	125121	17	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T81	0	42	0	0
T83	0	8	0	0
T125	0	3	0	0
T181	0	39	0	0
T210	0	5	0	0
T234	0	5	0	0
T239	0	13	0	0
T288	0	10	0	0
T290	0	16	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	1816	0	0
T1	125121	16	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T81	0	37	0	0
T83	0	10	0	0
T125	0	6	0	0
T181	0	29	0	0
T210	0	11	0	0
T234	0	11	0	0
T239	0	19	0	0
T288	0	13	0	0
T290	0	17	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	1707	0	0
T1	125121	14	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T81	0	32	0	0
T83	0	17	0	0
T125	0	3	0	0
T181	0	29	0	0
T210	0	3	0	0
T234	0	19	0	0
T239	0	18	0	0
T288	0	15	0	0
T290	0	15	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	1909	0	0
T1	125121	18	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T81	0	27	0	0
T83	0	7	0	0
T125	0	11	0	0
T181	0	33	0	0
T210	0	11	0	0
T234	0	11	0	0
T239	0	18	0	0
T288	0	28	0	0
T290	0	12	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	5272	0	0
T1	125121	8	0	0
T2	138344	0	0	0
T5	950254	37	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	62	0	0
T35	0	34	0	0
T37	0	68	0	0
T91	0	65	0	0
T119	0	57	0	0
T120	0	42	0	0
T242	0	41	0	0
T248	0	62	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	5265	0	0
T1	125121	18	0	0
T2	138344	0	0	0
T5	950254	30	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	70	0	0
T35	0	59	0	0
T37	0	74	0	0
T91	0	48	0	0
T119	0	68	0	0
T120	0	30	0	0
T242	0	34	0	0
T248	0	87	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	5412	0	0
T1	125121	9	0	0
T2	138344	0	0	0
T5	950254	46	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	68	0	0
T35	0	21	0	0
T37	0	72	0	0
T91	0	57	0	0
T119	0	66	0	0
T120	0	38	0	0
T242	0	43	0	0
T248	0	51	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	5306	0	0
T1	125121	9	0	0
T2	138344	0	0	0
T5	950254	41	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	63	0	0
T35	0	38	0	0
T37	0	80	0	0
T91	0	67	0	0
T119	0	56	0	0
T120	0	45	0	0
T242	0	42	0	0
T248	0	61	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	5110	0	0
T1	125121	10	0	0
T2	138344	0	0	0
T5	950254	38	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	51	0	0
T35	0	38	0	0
T37	0	73	0	0
T91	0	79	0	0
T119	0	64	0	0
T120	0	43	0	0
T242	0	50	0	0
T248	0	78	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	5280	0	0
T1	125121	27	0	0
T2	138344	0	0	0
T5	950254	40	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	60	0	0
T35	0	39	0	0
T37	0	57	0	0
T91	0	84	0	0
T119	0	40	0	0
T120	0	36	0	0
T242	0	38	0	0
T248	0	69	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	4955	0	0
T1	125121	12	0	0
T2	138344	0	0	0
T5	950254	45	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	73	0	0
T35	0	38	0	0
T37	0	61	0	0
T91	0	86	0	0
T119	0	66	0	0
T120	0	35	0	0
T242	0	33	0	0
T248	0	40	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	5393	0	0
T1	125121	12	0	0
T2	138344	0	0	0
T5	950254	44	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	56	0	0
T35	0	60	0	0
T37	0	71	0	0
T91	0	75	0	0
T119	0	74	0	0
T120	0	17	0	0
T242	0	50	0	0
T248	0	92	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	2949	0	0
T1	125121	12	0	0
T2	138344	0	0	0
T5	950254	2	0	0
T6	222150	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T22	15817	0	0	0
T32	0	18	0	0
T35	0	31	0	0
T37	0	49	0	0
T40	0	6	0	0
T52	0	2	0	0
T119	0	7	0	0
T137	0	2	0	0
T242	0	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	2349	0	0
T1	125121	25	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T81	0	47	0	0
T83	0	8	0	0
T125	0	15	0	0
T181	0	36	0	0
T207	0	5	0	0
T234	0	14	0	0
T250	0	14	0	0
T288	0	10	0	0
T291	0	21	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	4145	0	0
T1	125121	6	0	0
T2	138344	0	0	0
T9	0	3	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T40	0	2	0	0
T81	0	43	0	0
T82	0	9	0	0
T83	0	9	0	0
T125	0	6	0	0
T167	0	4	0	0
T288	0	23	0	0
T291	0	4	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	1748	0	0
T1	125121	13	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T81	0	48	0	0
T83	0	8	0	0
T125	0	13	0	0
T181	0	13	0	0
T210	0	6	0	0
T234	0	2	0	0
T239	0	15	0	0
T288	0	13	0	0
T290	0	14	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	5110	0	0
T1	125121	5	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T63	0	27	0	0
T65	0	94	0	0
T81	0	33	0	0
T83	0	101	0	0
T125	0	79	0	0
T288	0	17	0	0
T292	0	77	0	0
T293	0	53	0	0
T294	0	63	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	6280	0	0
T1	125121	60	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T81	0	177	0	0
T83	0	104	0	0
T87	0	52	0	0
T122	0	65	0	0
T125	0	164	0	0
T295	0	74	0	0
T296	0	41	0	0
T297	0	58	0	0
T298	0	36	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	4886	0	0
T1	125121	76	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T81	0	174	0	0
T83	0	72	0	0
T87	0	54	0	0
T122	0	76	0	0
T125	0	152	0	0
T295	0	56	0	0
T296	0	42	0	0
T297	0	58	0	0
T298	0	50	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	5302	0	0
T1	125121	82	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T81	0	192	0	0
T83	0	96	0	0
T87	0	68	0	0
T122	0	69	0	0
T125	0	172	0	0
T295	0	63	0	0
T296	0	36	0	0
T297	0	73	0	0
T298	0	53	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	2024	0	0
T1	125121	12	0	0
T2	138344	0	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T81	0	26	0	0
T83	0	12	0	0
T125	0	8	0	0
T181	0	32	0	0
T210	0	12	0	0
T234	0	21	0	0
T239	0	14	0	0
T288	0	9	0	0
T290	0	18	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	2061	0	0
T1	125121	11	0	0
T2	138344	0	0	0
T3	0	11	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T72	0	9	0	0
T74	0	7	0	0
T81	0	42	0	0
T83	0	16	0	0
T125	0	12	0	0
T288	0	23	0	0
T299	0	3	0	0
T300	0	4	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	2015	0	0
T1	125121	21	0	0
T2	138344	0	0	0
T3	0	9	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T72	0	3	0	0
T74	0	14	0	0
T81	0	50	0	0
T83	0	12	0	0
T125	0	6	0	0
T146	0	9	0	0
T233	0	2	0	0
T288	0	15	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	1988	0	0
T1	125121	15	0	0
T2	138344	0	0	0
T3	0	16	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T72	0	3	0	0
T74	0	14	0	0
T81	0	50	0	0
T83	0	14	0	0
T125	0	20	0	0
T146	0	3	0	0
T233	0	1	0	0
T288	0	13	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535642565	1964	0	0
T1	125121	20	0	0
T2	138344	0	0	0
T3	0	14	0	0
T14	157930	0	0	0
T15	53325	0	0	0
T16	13161	0	0	0
T17	121004	0	0	0
T18	22028	0	0	0
T19	128787	0	0	0
T20	889091	0	0	0
T21	240977	0	0	0
T72	0	6	0	0
T74	0	12	0	0
T81	0	35	0	0
T83	0	21	0	0
T125	0	18	0	0
T233	0	5	0	0
T288	0	11	0	0
T299	0	9	0	0