Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1990

1

T1

36

T7

22

T45

19

auto[1]

746

1

T1

20

T7

8

T8

6

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2104

1

T1

44

T7

18

T45

19

auto[1]

632

1

T1

12

T7

12

T8

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2015

1

T1

56

T7

28

T45

10

auto[1]

721

1

T7

2

T45

9

T8

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2041

1

T1

51

T7

20

T45

8

auto[1]

695

1

T1

5

T7

10

T45

11

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2454

1

T1

56

T7

30

T45

19

auto[1]

282

1

T8

9

T9

5

T48

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2457

1

T1

48

T7

30

T45

19

auto[1]

279

1

T1

8

T8

6

T9

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2477

1

T1

44

T7

30

T45

19

auto[1]

259

1

T1

12

T8

25

T9

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2426

1

T1

41

T7

30

T45

19

auto[1]

310

1

T1

15

T9

11

T60

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2505

1

T1

51

T7

30

T45

19

auto[1]

231

1

T1

5

T8

6

T9

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2062

1

T1

56

T7

24

T45

18

auto[1]

674

1

T7

6

T45

1

T8

13

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

792

1

T7

30

T45

8

T47

21

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

64

1

T48

2

T302

36

T389

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

97

1

T288

5

T177

16

T379

24

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T177

11

T390

1

T391

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

111

1

T9

5

T288

5

T300

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T9

3

T290

2

T392

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

13

1

T393

1

T394

12

-

-

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T288

3

T302

4

T395

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

89

1

T8

13

T48

2

T60

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T8

9

T48

2

T290

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

24

1

T1

5

T384

6

T396

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T9

2

T397

3

T398

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T1

7

T211

1

T267

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T388

4

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T134

2

T395

4

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

78

1

T11

2

T60

3

T303

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

63

1

T289

7

T399

14

T396

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

13

1

T8

3

T300

2

T292

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T289

5

T301

1

T397

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T1

8

T9

3

T60

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T393

7

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

8

1

T384

5

T267

3

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

17

1

T389

1

T375

4

T392

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T372

6

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T8

3

T400

2

T401

2

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

130

1

T1

8

T9

3

T129

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

102

1

T8

13

T132

11

T301

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

74

1

T7

6

T9

5

T298

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

90

1

T7

10

T9

2

T206

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

114

1

T8

3

T37

2

T60

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T132

3

T370

8

T392

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T11

2

T60

1

T132

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

113

1

T45

8

T60

2

T288

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

87

1

T7

2

T128

8

T380

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

67

1

T293

4

T131

2

T402

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T13

4

T206

1

T131

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T289

5

T135

6

T137

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

61

1

T8

3

T47

2

T37

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

26

1

T380

2

T255

3

T389

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T403

1

T174

4

T312

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

98

1

T7

12

T47

14

T48

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

48

1

T1

7

T305

5

T255

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

73

1

T48

2

T206

2

T295

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T275

6

T295

5

T367

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

65

1

T8

9

T12

5

T116

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T1

5

T13

4

T144

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T47

2

T12

2

T48

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T367

1

T305

2

T307

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T367

5

T380

4

T300

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T128

3

T403

1

T249

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T9

3

T294

2

T368

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T37

2

T144

1

T249

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T47

3

T37

2

T288

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T12

1

T293

1

T306

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T12

2

T275

3

T374

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T275

3

T369

1

T374

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded