Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

650

1

T6

10

T15

10

T20

6

auto[1]

630

1

T6

10

T15

10

T20

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

290

1

T6

5

T15

6

T20

5

from_0to1

280

1

T6

5

T15

5

T20

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

632

1

T6

11

T15

10

T20

9

auto[1]

648

1

T6

9

T15

10

T20

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

655

1

T6

10

T15

8

T20

11

auto[1]

625

1

T6

10

T15

12

T20

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

45

1

T6

1

T15

1

T33

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T80

2

T33

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T6

2

T15

1

T83

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T15

3

T20

1

T79

1

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T15

1

T83

3

T80

2

auto[0]

from_0to1

auto[0]

auto[1]

33

1

T6

2

T79

1

T80

1

auto[0]

from_0to1

auto[1]

auto[0]

35

1

T6

1

T15

1

T58

1

auto[0]

from_0to1

auto[1]

auto[1]

28

1

T80

1

T196

1

T31

1

auto[1]

from_1to0

auto[0]

auto[0]

30

1

T6

1

T83

1

T79

1

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T6

1

T15

1

T83

2

auto[1]

from_1to0

auto[1]

auto[0]

29

1

T20

3

T83

1

T58

1

auto[1]

from_1to0

auto[1]

auto[1]

27

1

T20

1

T33

1

T58

2

auto[1]

from_0to1

auto[0]

auto[0]

29

1

T15

1

T20

2

T79

2

auto[1]

from_0to1

auto[0]

auto[1]

35

1

T6

1

T15

1

T20

2

auto[1]

from_0to1

auto[1]

auto[0]

39

1

T6

1

T58

1

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T15

1

T20

1

T83

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

640

1

T6

10

T15

11

T20

9

auto[1]

640

1

T6

10

T15

9

T20

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

304

1

T6

4

T15

6

T20

4

from_0to1

306

1

T6

3

T15

5

T20

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

646

1

T6

10

T15

9

T20

11

auto[1]

634

1

T6

10

T15

11

T20

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

633

1

T6

12

T15

11

T20

8

auto[1]

647

1

T6

8

T15

9

T20

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

35

1

T6

1

T15

1

T83

1

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T79

1

T33

1

T196

2

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T79

1

T33

2

T58

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T6

1

T15

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T15

1

T80

1

T33

2

auto[0]

from_0to1

auto[0]

auto[1]

28

1

T6

1

T33

1

T418

1

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T6

1

T20

1

T80

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T15

1

T83

1

T79

1

auto[1]

from_1to0

auto[0]

auto[0]

31

1

T6

1

T15

1

T20

1

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T6

1

T20

3

T83

1

auto[1]

from_1to0

auto[1]

auto[0]

34

1

T15

2

T58

1

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

35

1

T15

1

T83

2

T80

2

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T15

1

T79

2

T58

1

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T20

1

T83

1

T79

1

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T6

1

T20

1

T83

2

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T15

2

T20

1

T83

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

635

1

T6

9

T15

10

T20

10

auto[1]

645

1

T6

11

T15

10

T20

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

311

1

T6

6

T15

4

T20

5

from_0to1

309

1

T6

5

T15

5

T20

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

652

1

T6

10

T15

10

T20

10

auto[1]

628

1

T6

10

T15

10

T20

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T6

10

T15

8

T20

14

auto[1]

632

1

T6

10

T15

12

T20

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

34

1

T79

1

T80

1

T33

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T6

1

T15

1

T83

1

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T20

1

T83

1

T80

1

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T58

1

T31

2

T277

1

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T20

1

T83

4

T80

1

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T6

1

T58

1

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

40

1

T6

1

T15

1

T20

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T6

1

T15

1

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T6

2

T20

1

T79

1

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T6

1

T15

1

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T6

2

T15

2

T20

2

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T79

1

T80

1

T196

2

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T6

1

T15

1

T79

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T15

1

T20

2

T79

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T6

1

T20

1

T80

1

auto[1]

from_0to1

auto[1]

auto[1]

32

1

T15

1

T83

1

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616

1

T6

12

T15

8

T20

10

auto[1]

664

1

T6

8

T15

12

T20

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

322

1

T6

4

T15

5

T20

4

from_0to1

321

1

T6

3

T15

4

T20

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659

1

T6

8

T15

7

T20

8

auto[1]

621

1

T6

12

T15

13

T20

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657

1

T6

11

T15

13

T20

11

auto[1]

623

1

T6

9

T15

7

T20

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T58

2

T70

1

T277

1

auto[0]

from_1to0

auto[0]

auto[1]

26

1

T6

1

T80

1

T33

1

auto[0]

from_1to0

auto[1]

auto[0]

39

1

T6

1

T15

2

T20

3

auto[0]

from_1to0

auto[1]

auto[1]

41

1

T83

1

T80

2

T31

1

auto[0]

from_0to1

auto[0]

auto[0]

43

1

T6

1

T15

1

T20

2

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T15

1

T83

1

T58

1

auto[0]

from_0to1

auto[1]

auto[0]

26

1

T6

1

T80

2

T31

2

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T83

1

T79

1

T80

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T20

1

T80

1

T33

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T83

2

T79

1

T80

2

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T6

1

T15

3

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

41

1

T6

1

T79

1

T196

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T20

1

T79

2

T80

1

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T80

1

T33

1

T58

1

auto[1]

from_0to1

auto[1]

auto[0]

45

1

T15

1

T20

1

T83

3

auto[1]

from_0to1

auto[1]

auto[1]

36

1

T6

1

T15

1

T80

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

621

1

T6

10

T15

9

T20

8

auto[1]

659

1

T6

10

T15

11

T20

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

311

1

T6

6

T15

4

T20

4

from_0to1

309

1

T6

6

T15

3

T20

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

658

1

T6

7

T15

8

T20

9

auto[1]

622

1

T6

13

T15

12

T20

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

625

1

T6

8

T15

7

T20

11

auto[1]

655

1

T6

12

T15

13

T20

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T20

1

T83

1

T70

2

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T6

1

T33

3

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T6

1

T15

1

T79

1

auto[0]

from_1to0

auto[1]

auto[1]

33

1

T20

1

T80

1

T33

1

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T83

2

T79

1

T33

3

auto[0]

from_0to1

auto[0]

auto[1]

33

1

T6

1

T20

1

T58

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T6

1

T15

1

T20

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T6

1

T15

1

T79

1

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T79

1

T33

1

T58

1

auto[1]

from_1to0

auto[0]

auto[1]

45

1

T6

1

T15

1

T79

1

auto[1]

from_1to0

auto[1]

auto[0]

30

1

T6

2

T20

1

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T6

1

T15

2

T20

1

auto[1]

from_0to1

auto[0]

auto[0]

37

1

T6

1

T15

1

T20

1

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T20

1

T79

1

T33

1

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T6

1

T79

1

T58

1

auto[1]

from_0to1

auto[1]

auto[1]

44

1

T6

1

T20

1

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

636

1

T6

10

T15

8

T20

10

auto[1]

644

1

T6

10

T15

12

T20

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

300

1

T6

6

T15

6

T20

5

from_0to1

298

1

T6

6

T15

6

T20

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T6

11

T15

8

T20

11

auto[1]

633

1

T6

9

T15

12

T20

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

653

1

T6

8

T15

11

T20

12

auto[1]

627

1

T6

12

T15

9

T20

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

47

1

T6

2

T15

1

T80

2

auto[0]

from_1to0

auto[0]

auto[1]

32

1

T79

1

T196

1

T294

1

auto[0]

from_1to0

auto[1]

auto[0]

38

1

T6

1

T15

1

T20

2

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T6

1

T20

1

T80

2

auto[0]

from_0to1

auto[0]

auto[0]

35

1

T6

1

T20

2

T83

1

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T6

2

T15

1

T83

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T20

1

T79

1

T74

2

auto[0]

from_0to1

auto[1]

auto[1]

37

1

T15

1

T80

1

T196

2

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T6

1

T79

1

T80

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T6

1

T15

1

T20

2

auto[1]

from_1to0

auto[1]

auto[0]

43

1

T15

2

T83

1

T79

1

auto[1]

from_1to0

auto[1]

auto[1]

23

1

T15

1

T79

1

T70

1

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T6

1

T15

1

T20

2

auto[1]

from_0to1

auto[0]

auto[1]

33

1

T6

1

T15

1

T33

1

auto[1]

from_0to1

auto[1]

auto[0]

32

1

T15

1

T79

1

T80

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T6

1

T15

1

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

639

1

T6

11

T15

8

T20

10

auto[1]

641

1

T6

9

T15

12

T20

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

305

1

T6

4

T15

6

T20

4

from_0to1

293

1

T6

4

T15

5

T20

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T6

10

T15

9

T20

13

auto[1]

632

1

T6

10

T15

11

T20

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T6

8

T15

9

T20

5

auto[1]

638

1

T6

12

T15

11

T20

15

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T15

1

T83

2

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T20

1

T79

1

T80

1

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T6

1

T15

2

T79

1

auto[0]

from_1to0

auto[1]

auto[1]

36

1

T6

1

T15

1

T20

1

auto[0]

from_0to1

auto[0]

auto[0]

32

1

T15

2

T58

1

T196

1

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T6

1

T20

1

T83

1

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T83

1

T80

1

T33

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T6

2

T20

1

T79

2

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T20

1

T79

1

T33

2

auto[1]

from_1to0

auto[0]

auto[1]

33

1

T6

1

T80

1

T196

2

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T15

1

T70

1

T196

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T6

1

T15

1

T20

1

auto[1]

from_0to1

auto[0]

auto[0]

32

1

T15

1

T80

1

T70

1

auto[1]

from_0to1

auto[0]

auto[1]

29

1

T15

1

T20

2

T58

1

auto[1]

from_0to1

auto[1]

auto[0]

32

1

T83

1

T79

1

T80

1

auto[1]

from_0to1

auto[1]

auto[1]

30

1

T6

1

T15

1

T83

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T6

7

T15

13

T20

10

auto[1]

632

1

T6

13

T15

7

T20

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

307

1

T6

5

T15

4

T20

5

from_0to1

309

1

T6

5

T15

4

T20

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668

1

T6

13

T15

12

T20

10

auto[1]

612

1

T6

7

T15

8

T20

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

632

1

T6

12

T15

12

T20

11

auto[1]

648

1

T6

8

T15

8

T20

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T15

3

T20

1

T83

1

auto[0]

from_1to0

auto[0]

auto[1]

35

1

T20

1

T83

1

T79

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T20

1

T83

1

T79

1

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T83

1

T79

1

T74

1

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T83

1

T79

1

T80

1

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T6

2

T15

2

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

31

1

T6

1

T15

1

T20

1

auto[0]

from_0to1

auto[1]

auto[1]

30

1

T83

1

T80

1

T196

2

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T6

3

T15

1

T80

1

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T20

1

T83

1

T79

2

auto[1]

from_1to0

auto[1]

auto[0]

26

1

T6

1

T20

1

T80

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T6

1

T79

1

T80

1

auto[1]

from_0to1

auto[0]

auto[0]

49

1

T20

1

T83

1

T79

2

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T6

1

T83

2

T79

1

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T6

1

T20

1

T79

1

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T15

1

T83

1

T58

2