Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148226	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

116648

1

T4

4

T5

251

T6

46

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141983	1			T4	3		T5	417		T6	62
values[0x0]	60920	1			T4	1		T5	16		T6	31
values[0x1]	61971	1			T4	1		T5	25		T6	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	119449	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145425

1

T4

4

T5

293

T6

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1771	1			T20	1		T83	2		T79	2
valid_sources[0x01]	812	1			T18	1		T20	1		T83	2
valid_sources[0x02]	802	1			T6	1		T18	1		T83	3
valid_sources[0x03]	784	1			T21	3		T18	7		T83	4
valid_sources[0x04]	1014	1			T20	3		T7	2		T45	1
valid_sources[0x05]	1097	1			T18	2		T20	1		T79	1
valid_sources[0x06]	761	1			T45	1		T8	9		T47	1
valid_sources[0x07]	1792	1			T5	4		T6	2		T83	1
valid_sources[0x08]	786	1			T18	1		T83	2		T79	1
valid_sources[0x09]	975	1			T5	20		T86	2		T83	2
valid_sources[0x0a]	878	1			T18	1		T83	2		T79	1
valid_sources[0x0b]	1043	1			T83	1		T45	1		T8	4
valid_sources[0x0c]	1069	1			T16	1		T20	1		T175	3
valid_sources[0x0d]	782	1			T15	1		T18	1		T20	1
valid_sources[0x0e]	1074	1			T6	1		T18	1		T20	2
valid_sources[0x0f]	771	1			T2	1		T18	1		T86	11
valid_sources[0x10]	1927	1			T6	1		T18	1		T20	1
valid_sources[0x11]	685	1			T5	1		T15	3		T18	4
valid_sources[0x12]	978	1			T18	1		T83	2		T45	3
valid_sources[0x13]	962	1			T6	2		T18	2		T83	2
valid_sources[0x14]	845	1			T18	3		T83	2		T7	4
valid_sources[0x15]	1060	1			T83	2		T79	1		T45	1
valid_sources[0x16]	1725	1			T3	1		T18	5		T20	3
valid_sources[0x17]	863	1			T5	2		T2	1		T18	2
valid_sources[0x18]	1953	1			T18	3		T20	1		T83	5
valid_sources[0x19]	964	1			T18	2		T20	1		T86	5
valid_sources[0x1a]	730	1			T15	6		T18	9		T7	3
valid_sources[0x1b]	1043	1			T6	2		T18	1		T83	1
valid_sources[0x1c]	1106	1			T18	4		T83	4		T45	2
valid_sources[0x1d]	871	1			T20	1		T83	1		T79	1
valid_sources[0x1e]	1009	1			T18	2		T83	3		T79	1
valid_sources[0x1f]	1580	1			T18	4		T83	2		T7	4
valid_sources[0x20]	1392	1			T83	4		T79	1		T8	4
valid_sources[0x21]	909	1			T18	1		T83	2		T7	2
valid_sources[0x22]	726	1			T6	1		T83	4		T7	3
valid_sources[0x23]	1113	1			T6	1		T18	2		T83	2
valid_sources[0x24]	881	1			T6	2		T18	2		T20	1
valid_sources[0x25]	864	1			T83	1		T7	2		T45	2
valid_sources[0x26]	876	1			T6	1		T18	1		T20	1
valid_sources[0x27]	1081	1			T18	2		T86	3		T79	1
valid_sources[0x28]	1057	1			T4	1		T15	1		T18	1
valid_sources[0x29]	847	1			T21	7		T20	3		T86	2
valid_sources[0x2a]	1163	1			T6	2		T20	1		T83	2
valid_sources[0x2b]	793	1			T6	2		T15	5		T18	2
valid_sources[0x2c]	1629	1			T19	1		T83	3		T7	4
valid_sources[0x2d]	1050	1			T5	20		T6	1		T18	1
valid_sources[0x2e]	864	1			T6	2		T3	1		T83	2
valid_sources[0x2f]	1031	1			T20	1		T83	4		T45	1
valid_sources[0x30]	658	1			T18	2		T86	9		T83	2
valid_sources[0x31]	869	1			T5	48		T18	1		T83	7
valid_sources[0x32]	777	1			T6	2		T15	1		T19	1
valid_sources[0x33]	976	1			T6	4		T83	2		T45	5
valid_sources[0x34]	2368	1			T6	2		T3	1		T18	4
valid_sources[0x35]	1132	1			T175	3		T83	1		T7	7
valid_sources[0x36]	1073	1			T20	2		T45	4		T8	5
valid_sources[0x37]	1821	1			T18	1		T20	3		T83	1
valid_sources[0x38]	765	1			T6	1		T21	2		T83	5
valid_sources[0x39]	1174	1			T20	1		T86	5		T83	2
valid_sources[0x3a]	932	1			T15	4		T86	10		T83	2
valid_sources[0x3b]	1337	1			T6	3		T18	2		T83	2
valid_sources[0x3c]	736	1			T79	1		T7	3		T45	5
valid_sources[0x3d]	706	1			T6	4		T18	3		T79	1
valid_sources[0x3e]	1018	1			T21	6		T15	2		T3	2
valid_sources[0x3f]	865	1			T83	1		T45	6		T8	3
valid_sources[0x40]	2293	1			T83	4		T28	2		T7	2
valid_sources[0x41]	1453	1			T18	2		T83	3		T8	3
valid_sources[0x42]	985	1			T20	2		T86	1		T83	2
valid_sources[0x43]	1316	1			T6	1		T7	2		T45	5
valid_sources[0x44]	1260	1			T18	1		T83	1		T7	1
valid_sources[0x45]	1149	1			T6	1		T18	5		T20	1
valid_sources[0x46]	1178	1			T4	2		T6	3		T18	3
valid_sources[0x47]	2145	1			T5	8		T1	1348		T18	1
valid_sources[0x48]	981	1			T18	2		T20	1		T79	2
valid_sources[0x49]	761	1			T15	6		T18	1		T83	6
valid_sources[0x4a]	822	1			T2	1		T18	2		T86	3
valid_sources[0x4b]	777	1			T6	1		T86	5		T83	2
valid_sources[0x4c]	865	1			T21	1		T18	1		T83	1
valid_sources[0x4d]	1412	1			T83	6		T45	4		T8	9
valid_sources[0x4e]	1158	1			T21	6		T20	1		T86	1
valid_sources[0x4f]	870	1			T6	1		T18	4		T86	1
valid_sources[0x50]	1066	1			T15	1		T18	2		T20	2
valid_sources[0x51]	775	1			T6	1		T18	9		T83	3
valid_sources[0x52]	1044	1			T83	2		T7	1		T45	3
valid_sources[0x53]	944	1			T15	5		T18	3		T20	2
valid_sources[0x54]	854	1			T20	1		T86	1		T83	1
valid_sources[0x55]	830	1			T15	4		T86	1		T83	2
valid_sources[0x56]	1291	1			T15	3		T86	12		T83	4
valid_sources[0x57]	901	1			T5	20		T15	5		T20	1
valid_sources[0x58]	1321	1			T6	1		T83	1		T79	1
valid_sources[0x59]	982	1			T18	4		T20	1		T83	2
valid_sources[0x5a]	1014	1			T18	1		T83	3		T28	4
valid_sources[0x5b]	879	1			T6	2		T18	2		T86	1
valid_sources[0x5c]	893	1			T18	1		T20	1		T83	1
valid_sources[0x5d]	1140	1			T6	1		T83	2		T79	1
valid_sources[0x5e]	1204	1			T2	1		T83	4		T45	2
valid_sources[0x5f]	1104	1			T6	1		T20	1		T83	1
valid_sources[0x60]	966	1			T16	1		T18	4		T20	2
valid_sources[0x61]	870	1			T18	3		T83	5		T45	2
valid_sources[0x62]	996	1			T6	1		T18	2		T86	5
valid_sources[0x63]	696	1			T6	1		T18	3		T86	1
valid_sources[0x64]	858	1			T83	4		T79	1		T7	4
valid_sources[0x65]	2057	1			T18	4		T83	2		T7	4
valid_sources[0x66]	932	1			T5	20		T18	3		T83	1
valid_sources[0x67]	759	1			T15	1		T45	3		T8	1
valid_sources[0x68]	1181	1			T21	1		T20	1		T83	1
valid_sources[0x69]	886	1			T6	2		T2	1		T83	3
valid_sources[0x6a]	762	1			T3	2		T18	1		T20	3
valid_sources[0x6b]	1001	1			T18	9		T20	1		T83	1
valid_sources[0x6c]	807	1			T18	1		T20	1		T79	1
valid_sources[0x6d]	1000	1			T18	1		T83	4		T45	1
valid_sources[0x6e]	883	1			T15	1		T2	1		T83	3
valid_sources[0x6f]	742	1			T5	4		T6	2		T18	4
valid_sources[0x70]	1097	1			T5	20		T3	2		T83	3
valid_sources[0x71]	901	1			T6	2		T2	2		T18	3
valid_sources[0x72]	1019	1			T18	4		T86	1		T83	2
valid_sources[0x73]	799	1			T21	1		T83	3		T7	4
valid_sources[0x74]	893	1			T6	2		T83	3		T79	1
valid_sources[0x75]	999	1			T16	3		T18	4		T86	4
valid_sources[0x76]	749	1			T15	1		T83	2		T79	1
valid_sources[0x77]	898	1			T6	1		T18	17		T83	4
valid_sources[0x78]	1133	1			T18	1		T83	3		T45	2
valid_sources[0x79]	778	1			T18	5		T83	1		T79	1
valid_sources[0x7a]	821	1			T20	2		T83	1		T7	8
valid_sources[0x7b]	1127	1			T5	48		T6	2		T18	1
valid_sources[0x7c]	1036	1			T20	2		T86	2		T83	1
valid_sources[0x7d]	1678	1			T3	1		T18	2		T20	1
valid_sources[0x7e]	776	1			T6	1		T18	1		T83	4
valid_sources[0x7f]	832	1			T85	1		T83	3		T79	2
valid_sources[0x80]	1017	1			T21	4		T15	7		T2	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64488

1

T4

2

T5

216

T6

31

values[0x0]

all_enables

biggest_size

30404

1

T4

1

T5

15

T6

10

values[0x1]

all_enables

biggest_size

21756

1

T4

1

T5

20

T6

5