Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T21,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T29,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T33,T29,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T29,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T33,T29,T49
1	0	Covered	T5,T6,T21
1	1	Covered	T33,T29,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T29,T49
0	1	Covered	T29,T50,T140
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T29,T49
0	1	Covered	T33,T29,T49
1	0	Covered	T117

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T29,T49
1	-	Covered	T33,T29,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T33,T29,T49
DetectSt	168	Covered	T33,T29,T49
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T33,T29,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T29,T49
DebounceSt->IdleSt	163	Covered	T33,T53,T125
DetectSt->IdleSt	186	Covered	T29,T50,T140
DetectSt->StableSt	191	Covered	T33,T29,T49
IdleSt->DebounceSt	148	Covered	T33,T29,T49
StableSt->IdleSt	206	Covered	T33,T29,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T33,T29,T49
0	1	Covered	T33,T29,T49
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T29,T49
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T33,T29,T49
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T59
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T29,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T53,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T33,T29,T49
DetectSt	-	-	-	-	1	-	-	Covered	T29,T50,T140
DetectSt	-	-	-	-	0	1	-	Covered	T33,T29,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T29,T49
StableSt	-	-	-	-	-	-	0	Covered	T33,T29,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	213	0	0
CntIncr_A	5928678	34127	0	0
CntNoWrap_A	5928678	5454239	0	0
DetectStDropOut_A	5928678	3	0	0
DetectedOut_A	5928678	670	0	0
DetectedPulseOut_A	5928678	97	0	0
DisabledIdleSt_A	5928678	5415307	0	0
DisabledNoDetection_A	5928678	5417247	0	0
EnterDebounceSt_A	5928678	115	0	0
EnterDetectSt_A	5928678	100	0	0
EnterStableSt_A	5928678	97	0	0
PulseIsPulse_A	5928678	97	0	0
StayInStableSt	5928678	573	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5928678	5578	0	0
gen_low_level_sva.LowLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	96	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	213	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T27	0	2	0	0
T29	0	4	0	0
T30	0	6	0	0
T33	4193	3	0	0
T49	0	6	0	0
T50	0	4	0	0
T52	0	2	0	0
T53	0	3	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T69	713	0	0	0
T70	502	0	0	0
T126	0	4	0	0
T127	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	34127	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T27	0	11	0	0
T29	0	120	0	0
T30	0	173	0	0
T33	4193	41	0	0
T49	0	174	0	0
T50	0	117	0	0
T52	0	74	0	0
T53	0	168	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T69	713	0	0	0
T70	502	0	0	0
T126	0	106	0	0
T127	0	163	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454239	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	3	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	1	0	0
T51	627	0	0	0
T60	36357	0	0	0
T140	0	1	0	0
T142	541	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	670	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T27	0	3	0	0
T29	0	12	0	0
T30	0	19	0	0
T33	4193	6	0	0
T49	0	6	0	0
T50	0	8	0	0
T52	0	3	0	0
T53	0	12	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T69	713	0	0	0
T70	502	0	0	0
T126	0	8	0	0
T127	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	97	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T30	0	3	0	0
T33	4193	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T69	713	0	0	0
T70	502	0	0	0
T126	0	2	0	0
T127	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5415307	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5417247	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	115	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T30	0	3	0	0
T33	4193	2	0	0
T49	0	3	0	0
T50	0	2	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T69	713	0	0	0
T70	502	0	0	0
T126	0	2	0	0
T127	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	100	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T30	0	3	0	0
T33	4193	1	0	0
T49	0	3	0	0
T50	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T69	713	0	0	0
T70	502	0	0	0
T126	0	2	0	0
T127	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	97	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T30	0	3	0	0
T33	4193	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T69	713	0	0	0
T70	502	0	0	0
T126	0	2	0	0
T127	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	97	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T30	0	3	0	0
T33	4193	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T69	713	0	0	0
T70	502	0	0	0
T126	0	2	0	0
T127	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	573	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T27	0	2	0	0
T29	0	11	0	0
T30	0	16	0	0
T33	4193	5	0	0
T49	0	3	0	0
T50	0	7	0	0
T52	0	2	0	0
T53	0	11	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T69	713	0	0	0
T70	502	0	0	0
T126	0	6	0	0
T127	0	25	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5578	0	0
T1	46391	32	0	0
T2	673	1	0	0
T3	991	1	0	0
T6	502	4	0	0
T14	424	2	0	0
T15	501	4	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	36	0	0
T19	0	3	0	0
T20	0	3	0	0
T21	526	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	96	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T30	0	3	0	0
T33	4193	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T69	713	0	0	0
T70	502	0	0	0
T126	0	2	0	0
T127	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T21,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T26,T27
1	0	Covered	T5,T6,T21
1	1	Covered	T10,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T26,T27
0	1	Covered	T64,T124
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T26,T27
0	1	Unreachable
1	0	Covered	T10,T26,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T26,T27
DetectSt	168	Covered	T10,T26,T27
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T26,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T26,T27
DebounceSt->IdleSt	163	Covered	T64,T59,T152
DetectSt->IdleSt	186	Covered	T64,T124
DetectSt->StableSt	191	Covered	T10,T26,T27
IdleSt->DebounceSt	148	Covered	T10,T26,T27
StableSt->IdleSt	206	Covered	T10,T26,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T26,T27
0	1	Covered	T10,T26,T27
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T26,T27
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T152,T153
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T64,T124
DetectSt	-	-	-	-	0	1	-	Covered	T10,T26,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T26,T27
StableSt	-	-	-	-	-	-	0	Covered	T10,T26,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	133	0	0
CntIncr_A	5928678	54715	0	0
CntNoWrap_A	5928678	5454319	0	0
DetectStDropOut_A	5928678	3	0	0
DetectedOut_A	5928678	204059	0	0
DetectedPulseOut_A	5928678	55	0	0
DisabledIdleSt_A	5928678	4599481	0	0
DisabledNoDetection_A	5928678	4601457	0	0
EnterDebounceSt_A	5928678	75	0	0
EnterDetectSt_A	5928678	58	0	0
EnterStableSt_A	5928678	55	0	0
PulseIsPulse_A	5928678	55	0	0
StayInStableSt	5928678	204004	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5928678	5578	0	0
gen_low_level_sva.LowLevelEvent_A	5928678	5456428	0	0
gen_sticky_sva.StableStDropOut_A	5928678	593437	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	133	0	0
T10	329770	2	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	2	0	0
T27	0	2	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	4	0	0
T63	0	4	0	0
T64	0	5	0	0
T67	0	4	0	0
T68	0	2	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	2	0	0
T91	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	54715	0	0
T10	329770	89	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	23	0	0
T27	0	41	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	118	0	0
T63	0	180	0	0
T64	0	150	0	0
T67	0	78	0	0
T68	0	10	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	64	0	0
T91	0	104	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454319	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	3	0	0
T64	1027	2	0	0
T78	489	0	0	0
T124	0	1	0	0
T127	691	0	0	0
T128	18628	0	0	0
T143	744	0	0	0
T144	7098	0	0	0
T145	534	0	0	0
T146	422	0	0	0
T147	403	0	0	0
T154	636	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	204059	0	0
T10	329770	417	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	51	0	0
T27	0	6	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	440	0	0
T63	0	222	0	0
T67	0	223	0	0
T68	0	4	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	317	0	0
T91	0	514	0	0
T122	0	115	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	55	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	1	0	0
T91	0	2	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4599481	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4601457	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	75	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	3	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	1	0	0
T91	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	58	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	1	0	0
T91	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	55	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	1	0	0
T91	0	2	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	55	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	1	0	0
T91	0	2	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	204004	0	0
T10	329770	416	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	50	0	0
T27	0	5	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	438	0	0
T63	0	220	0	0
T67	0	221	0	0
T68	0	3	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	316	0	0
T91	0	512	0	0
T122	0	114	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5578	0	0
T1	46391	32	0	0
T2	673	1	0	0
T3	991	1	0	0
T6	502	4	0	0
T14	424	2	0	0
T15	501	4	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	36	0	0
T19	0	3	0	0
T20	0	3	0	0
T21	526	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	593437	0	0
T10	329770	326115	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	312	0	0
T27	0	84	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	519	0	0
T63	0	96	0	0
T67	0	250	0	0
T68	0	92	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	173	0	0
T91	0	597	0	0
T122	0	53	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T21,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T21,T14
1	1	Covered	T6,T21,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T26,T27
1	0	Covered	T6,T21,T14
1	1	Covered	T10,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T26,T27
0	1	Covered	T63,T122,T123
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T26,T27
0	1	Unreachable
1	0	Covered	T10,T26,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T26,T27
DetectSt	168	Covered	T10,T26,T27
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T26,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T26,T27
DebounceSt->IdleSt	163	Covered	T63,T90,T59
DetectSt->IdleSt	186	Covered	T63,T122,T123
DetectSt->StableSt	191	Covered	T10,T26,T27
IdleSt->DebounceSt	148	Covered	T10,T26,T27
StableSt->IdleSt	206	Covered	T10,T26,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T26,T27
0	1	Covered	T10,T26,T27
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T26,T27
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T6,T21,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T63,T90,T123
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T63,T122,T123
DetectSt	-	-	-	-	0	1	-	Covered	T10,T26,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T26,T27
StableSt	-	-	-	-	-	-	0	Covered	T10,T26,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	156	0	0
CntIncr_A	5928678	247048	0	0
CntNoWrap_A	5928678	5454296	0	0
DetectStDropOut_A	5928678	11	0	0
DetectedOut_A	5928678	303904	0	0
DetectedPulseOut_A	5928678	48	0	0
DisabledIdleSt_A	5928678	4599481	0	0
DisabledNoDetection_A	5928678	4601457	0	0
EnterDebounceSt_A	5928678	97	0	0
EnterDetectSt_A	5928678	59	0	0
EnterStableSt_A	5928678	48	0	0
PulseIsPulse_A	5928678	48	0	0
StayInStableSt	5928678	303856	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_sticky_sva.StableStDropOut_A	5928678	179835	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	156	0	0
T10	329770	2	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	2	0	0
T27	0	2	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	4	0	0
T63	0	5	0	0
T64	0	2	0	0
T67	0	4	0	0
T68	0	2	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	4	0	0
T91	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	247048	0	0
T10	329770	54745	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	55	0	0
T27	0	66	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	76	0	0
T63	0	276	0	0
T64	0	20	0	0
T67	0	148	0	0
T68	0	48	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	264	0	0
T91	0	140	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454296	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	11	0	0
T30	8666	0	0	0
T63	1092	1	0	0
T72	498	0	0	0
T122	0	2	0	0
T123	0	2	0	0
T126	627	0	0	0
T155	0	3	0	0
T156	0	3	0	0
T157	522	0	0	0
T158	430	0	0	0
T159	424	0	0	0
T160	439	0	0	0
T161	411	0	0	0
T162	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	303904	0	0
T10	329770	271799	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	228	0	0
T27	0	28	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	364	0	0
T63	0	94	0	0
T64	0	99	0	0
T67	0	218	0	0
T68	0	33	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	910	0	0
T148	0	187	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	48	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	2	0	0
T148	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4599481	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4601457	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	97	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	3	0	0
T64	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	4	0	0
T91	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	59	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	2	0	0
T122	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	48	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	2	0	0
T148	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	48	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	2	0	0
T148	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	303856	0	0
T10	329770	271798	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	227	0	0
T27	0	27	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	362	0	0
T63	0	93	0	0
T64	0	98	0	0
T67	0	216	0	0
T68	0	32	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	908	0	0
T148	0	186	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	179835	0	0
T10	329770	72	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	98	0	0
T27	0	26	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	641	0	0
T63	0	63	0	0
T64	0	119	0	0
T67	0	177	0	0
T68	0	28	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	159	0	0
T148	0	51	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T21,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T27,T62

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T26,T27
1	0	Covered	T6,T21,T1
1	1	Covered	T10,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T62,T63
0	1	Covered	T10,T27,T68
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T62,T63
0	1	Unreachable
1	0	Covered	T10,T62,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T26,T27
DetectSt	168	Covered	T10,T27,T62
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T62,T63

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T27,T62
DebounceSt->IdleSt	163	Covered	T26,T64,T90
DetectSt->IdleSt	186	Covered	T10,T27,T68
DetectSt->StableSt	191	Covered	T10,T62,T63
IdleSt->DebounceSt	148	Covered	T10,T26,T27
StableSt->IdleSt	206	Covered	T10,T62,T63

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T26,T27
0	1	Covered	T10,T26,T27
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T27,T62
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T6,T21,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T27,T62
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T64,T90
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T10,T27,T68
DetectSt	-	-	-	-	0	1	-	Covered	T10,T62,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T62,T63
StableSt	-	-	-	-	-	-	0	Covered	T10,T62,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	169	0	0
CntIncr_A	5928678	95885	0	0
CntNoWrap_A	5928678	5454283	0	0
DetectStDropOut_A	5928678	21	0	0
DetectedOut_A	5928678	20018	0	0
DetectedPulseOut_A	5928678	40	0	0
DisabledIdleSt_A	5928678	4599481	0	0
DisabledNoDetection_A	5928678	4601457	0	0
EnterDebounceSt_A	5928678	108	0	0
EnterDetectSt_A	5928678	61	0	0
EnterStableSt_A	5928678	40	0	0
PulseIsPulse_A	5928678	40	0	0
StayInStableSt	5928678	19978	0	0
gen_high_event_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_sticky_sva.StableStDropOut_A	5928678	641876	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	169	0	0
T10	329770	4	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	3	0	0
T27	0	2	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	4	0	0
T63	0	4	0	0
T64	0	3	0	0
T67	0	4	0	0
T68	0	2	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	7	0	0
T91	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	95885	0	0
T10	329770	170	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	198	0	0
T27	0	11	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	172	0	0
T63	0	104	0	0
T64	0	36	0	0
T67	0	200	0	0
T68	0	73	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	148	0	0
T91	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454283	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	21	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	3	0	0
T123	0	2	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	3	0	0
T167	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	20018	0	0
T10	329770	173	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	840	0	0
T63	0	205	0	0
T67	0	296	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	155	0	0
T122	0	99	0	0
T148	0	96	0	0
T149	0	1	0	0
T150	0	42	0	0
T151	0	226	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	40	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T67	0	2	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	2	0	0
T122	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4599481	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4601457	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	108	0	0
T10	329770	2	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T26	0	3	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	3	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	4	0	0
T91	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	61	0	0
T10	329770	2	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T27	0	1	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T90	0	3	0	0
T91	0	2	0	0
T122	0	1	0	0
T148	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	40	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T67	0	2	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	2	0	0
T122	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	40	0	0
T10	329770	1	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	2	0	0
T63	0	2	0	0
T67	0	2	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	2	0	0
T122	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	19978	0	0
T10	329770	172	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	838	0	0
T63	0	203	0	0
T67	0	294	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	153	0	0
T122	0	98	0	0
T148	0	95	0	0
T150	0	41	0	0
T151	0	225	0	0
T163	0	45	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	641876	0	0
T10	329770	244719	0	0
T11	12736	0	0	0
T12	18567	0	0	0
T13	21523	0	0	0
T46	8570	0	0	0
T57	517	0	0	0
T58	502	0	0	0
T62	0	85	0	0
T63	0	209	0	0
T67	0	81	0	0
T69	713	0	0	0
T70	502	0	0	0
T71	407	0	0	0
T91	0	1036	0	0
T122	0	38	0	0
T148	0	149	0	0
T149	0	28	0	0
T150	0	75	0	0
T151	0	82	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T38,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T38,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T38,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T38,T84
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T38,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T38,T41
0	1	Covered	T121
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T38,T41
0	1	Covered	T168,T169,T170
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T38,T41
1	-	Covered	T168,T169,T170

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T38,T41
DetectSt	168	Covered	T3,T38,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T38,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T38,T41
DebounceSt->IdleSt	163	Covered	T168,T171,T172
DetectSt->IdleSt	186	Covered	T121
DetectSt->StableSt	191	Covered	T3,T38,T41
IdleSt->DebounceSt	148	Covered	T3,T38,T41
StableSt->IdleSt	206	Covered	T168,T169,T170

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T38,T41
0	1	Covered	T3,T38,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T38,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T38,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T117
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T38,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T168,T171,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T38,T41
DetectSt	-	-	-	-	1	-	-	Covered	T121
DetectSt	-	-	-	-	0	1	-	Covered	T3,T38,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T168,T169,T170
StableSt	-	-	-	-	-	-	0	Covered	T3,T38,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	72	0	0
CntIncr_A	5928678	56294	0	0
CntNoWrap_A	5928678	5454380	0	0
DetectStDropOut_A	5928678	1	0	0
DetectedOut_A	5928678	4575	0	0
DetectedPulseOut_A	5928678	33	0	0
DisabledIdleSt_A	5928678	5207927	0	0
DisabledNoDetection_A	5928678	5209858	0	0
EnterDebounceSt_A	5928678	38	0	0
EnterDetectSt_A	5928678	34	0	0
EnterStableSt_A	5928678	33	0	0
PulseIsPulse_A	5928678	33	0	0
StayInStableSt	5928678	4521	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	72	0	0
T3	991	2	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T38	0	2	0	0
T41	0	2	0	0
T43	0	2	0	0
T59	0	2	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	4	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	408	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	56294	0	0
T3	991	99	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T38	0	76	0	0
T41	0	81	0	0
T43	0	24	0	0
T59	0	30	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	154	0	0
T169	0	65	0	0
T170	0	130	0	0
T173	0	31	0	0
T174	0	55	0	0
T175	408	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454380	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	588	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1	0	0
T121	3585	1	0	0
T123	2046	0	0	0
T172	658	0	0	0
T176	8822	0	0	0
T177	25650	0	0	0
T178	424	0	0	0
T179	5216	0	0	0
T180	402	0	0	0
T181	633	0	0	0
T182	501	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4575	0	0
T3	991	44	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T38	0	41	0	0
T41	0	39	0	0
T43	0	43	0	0
T59	0	15	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	40	0	0
T169	0	40	0	0
T170	0	236	0	0
T173	0	39	0	0
T174	0	46	0	0
T175	408	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	33	0	0
T3	991	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T59	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	408	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5207927	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	4	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5209858	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	4	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	38	0	0
T3	991	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T59	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	408	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	34	0	0
T3	991	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T59	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	408	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	33	0	0
T3	991	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T59	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	408	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	33	0	0
T3	991	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T59	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	408	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4521	0	0
T3	991	42	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T38	0	39	0	0
T41	0	37	0	0
T43	0	41	0	0
T59	0	14	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	39	0	0
T169	0	39	0	0
T170	0	233	0	0
T173	0	37	0	0
T174	0	44	0	0
T175	408	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	11	0	0
T68	564	0	0	0
T130	5716	0	0	0
T131	29836	0	0	0
T132	64206	0	0	0
T168	1033	1	0	0
T169	986	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T183	0	1	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	497	0	0	0
T190	453	0	0	0
T191	778	0	0	0
T192	646	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T12,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T29
1	0	Covered	T5,T6,T21
1	1	Covered	T3,T12,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T29
0	1	Covered	T40,T170
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T29,T39
0	1	Covered	T3,T39,T40
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T29,T39
1	-	Covered	T3,T39,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T12,T29
DetectSt	168	Covered	T3,T12,T29
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T12,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T12,T29
DebounceSt->IdleSt	163	Covered	T183,T184,T193
DetectSt->IdleSt	186	Covered	T40,T170
DetectSt->StableSt	191	Covered	T3,T12,T29
IdleSt->DebounceSt	148	Covered	T3,T12,T29
StableSt->IdleSt	206	Covered	T3,T29,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T12,T29
0	1	Covered	T3,T12,T29
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T29
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T12,T29
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T117
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T12,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T184,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T12,T29
DetectSt	-	-	-	-	1	-	-	Covered	T40,T170
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T12,T29,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	91	0	0
CntIncr_A	5928678	76284	0	0
CntNoWrap_A	5928678	5454361	0	0
DetectStDropOut_A	5928678	2	0	0
DetectedOut_A	5928678	51997	0	0
DetectedPulseOut_A	5928678	40	0	0
DisabledIdleSt_A	5928678	5252755	0	0
DisabledNoDetection_A	5928678	5254695	0	0
EnterDebounceSt_A	5928678	50	0	0
EnterDetectSt_A	5928678	42	0	0
EnterStableSt_A	5928678	40	0	0
PulseIsPulse_A	5928678	40	0	0
StayInStableSt	5928678	51940	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5928678	1591	0	0
gen_low_level_sva.LowLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	91	0	0
T3	991	2	0	0
T12	0	2	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T29	0	2	0	0
T39	0	4	0	0
T40	0	4	0	0
T41	0	2	0	0
T59	0	2	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	6	0	0
T170	0	4	0	0
T175	408	0	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	76284	0	0
T3	991	99	0	0
T12	0	87	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T29	0	52	0	0
T39	0	160	0	0
T40	0	88	0	0
T41	0	81	0	0
T59	0	30	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	231	0	0
T170	0	130	0	0
T175	408	0	0	0
T194	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454361	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	588	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	2	0	0
T26	823	0	0	0
T40	2390	1	0	0
T52	775	0	0	0
T107	1289	0	0	0
T110	406	0	0	0
T170	0	1	0	0
T195	693	0	0	0
T196	506	0	0	0
T197	443	0	0	0
T198	403	0	0	0
T199	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	51997	0	0
T3	991	1	0	0
T12	0	184	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T29	0	189	0	0
T39	0	318	0	0
T40	0	158	0	0
T41	0	24	0	0
T59	0	16	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	243	0	0
T170	0	60	0	0
T175	408	0	0	0
T194	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	40	0	0
T3	991	1	0	0
T12	0	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T29	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T59	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	3	0	0
T170	0	1	0	0
T175	408	0	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5252755	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	4	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5254695	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	4	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	50	0	0
T3	991	1	0	0
T12	0	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T29	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T59	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	3	0	0
T170	0	2	0	0
T175	408	0	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	42	0	0
T3	991	1	0	0
T12	0	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T29	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T59	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	3	0	0
T170	0	2	0	0
T175	408	0	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	40	0	0
T3	991	1	0	0
T12	0	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T29	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T59	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	3	0	0
T170	0	1	0	0
T175	408	0	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	40	0	0
T3	991	1	0	0
T12	0	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T29	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T59	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	3	0	0
T170	0	1	0	0
T175	408	0	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	51940	0	0
T12	18567	182	0	0
T13	21523	0	0	0
T29	2930	187	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	315	0	0
T40	0	157	0	0
T41	0	23	0	0
T46	8570	0	0	0
T48	11544	0	0	0
T59	0	15	0	0
T71	407	0	0	0
T142	541	0	0	0
T168	0	239	0	0
T170	0	59	0	0
T174	0	19	0	0
T194	0	3	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1591	0	0
T1	46391	0	0	0
T2	673	1	0	0
T3	991	1	0	0
T6	502	6	0	0
T14	424	3	0	0
T15	501	5	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	0	2	0	0
T20	0	7	0	0
T21	526	3	0	0
T83	0	10	0	0
T85	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	22	0	0
T3	991	1	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	2	0	0
T170	0	1	0	0
T174	0	1	0	0
T175	408	0	0	0
T183	0	1	0	0
T184	0	2	0	0
T194	0	1	0	0