Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.36	93.48	100.00		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.36	93.48	100.00		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T29
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T40
0	1	Covered	T84,T42,T168
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T40
1	-	Covered	T84,T42,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T40
DetectSt	168	Covered	T2,T3,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T40
DebounceSt->IdleSt	163	Covered	T117
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T3,T40
IdleSt->DebounceSt	148	Covered	T2,T3,T40
StableSt->IdleSt	206	Covered	T40,T84,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T40
0	1	Covered	T2,T3,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T117
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T84,T42,T168
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	69	0	0
CntIncr_A	5928678	55978	0	0
CntNoWrap_A	5928678	5454383	0	0
DetectStDropOut_A	5928678	0	0	0
DetectedOut_A	5928678	58844	0	0
DetectedPulseOut_A	5928678	34	0	0
DisabledIdleSt_A	5928678	5218457	0	0
DisabledNoDetection_A	5928678	5220383	0	0
EnterDebounceSt_A	5928678	35	0	0
EnterDetectSt_A	5928678	34	0	0
EnterStableSt_A	5928678	34	0	0
PulseIsPulse_A	5928678	34	0	0
StayInStableSt	5928678	58795	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	69	0	0
T2	673	2	0	0
T3	991	2	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T59	0	2	0	0
T84	0	2	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	2	0	0
T170	0	2	0	0
T171	0	6	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	55978	0	0
T2	673	36	0	0
T3	991	99	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T40	0	44	0	0
T42	0	10	0	0
T59	0	30	0	0
T84	0	98	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	77	0	0
T170	0	65	0	0
T171	0	249	0	0
T200	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454383	0	0
T1	46391	45968	0	0
T2	673	270	0	0
T3	991	588	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	58844	0	0
T2	673	91	0	0
T3	991	145	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T40	0	178	0	0
T42	0	8	0	0
T59	0	16	0	0
T84	0	44	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	27	0	0
T170	0	167	0	0
T171	0	125	0	0
T200	0	64	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	34	0	0
T2	673	1	0	0
T3	991	1	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5218457	0	0
T1	46391	45968	0	0
T2	673	4	0	0
T3	991	4	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5220383	0	0
T1	46391	45980	0	0
T2	673	4	0	0
T3	991	4	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	35	0	0
T2	673	1	0	0
T3	991	1	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	34	0	0
T2	673	1	0	0
T3	991	1	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	34	0	0
T2	673	1	0	0
T3	991	1	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	34	0	0
T2	673	1	0	0
T3	991	1	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	58795	0	0
T2	673	89	0	0
T3	991	143	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T40	0	176	0	0
T42	0	7	0	0
T59	0	15	0	0
T84	0	43	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T168	0	26	0	0
T170	0	165	0	0
T171	0	121	0	0
T200	0	63	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	18	0	0
T30	8666	0	0	0
T31	502	0	0	0
T41	636	0	0	0
T42	0	1	0	0
T53	3527	0	0	0
T63	1092	0	0	0
T84	3232	1	0	0
T120	0	1	0	0
T168	0	1	0	0
T171	0	2	0	0
T184	0	2	0	0
T193	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	778	0	0	0
T204	457	0	0	0
T205	454	0	0	0
T206	28004	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T29,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T12,T29,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T29,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T29,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T12,T29,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T29,T39
0	1	Covered	T202,T207
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T29,T39
0	1	Covered	T84,T43,T169
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T29,T39
1	-	Covered	T84,T43,T169

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T29,T39
DetectSt	168	Covered	T12,T29,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T29,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T29,T39
DebounceSt->IdleSt	163	Covered	T208,T184,T121
DetectSt->IdleSt	186	Covered	T202,T207
DetectSt->StableSt	191	Covered	T12,T29,T39
IdleSt->DebounceSt	148	Covered	T12,T29,T39
StableSt->IdleSt	206	Covered	T29,T44,T84

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T29,T39
0	1	Covered	T12,T29,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T29,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T29,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T117
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T29,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T208,T184,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T29,T39
DetectSt	-	-	-	-	1	-	-	Covered	T202,T207
DetectSt	-	-	-	-	0	1	-	Covered	T12,T29,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T84,T43,T169
StableSt	-	-	-	-	-	-	0	Covered	T12,T29,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	105	0	0
CntIncr_A	5928678	57188	0	0
CntNoWrap_A	5928678	5454347	0	0
DetectStDropOut_A	5928678	2	0	0
DetectedOut_A	5928678	58263	0	0
DetectedPulseOut_A	5928678	48	0	0
DisabledIdleSt_A	5928678	5220787	0	0
DisabledNoDetection_A	5928678	5222719	0	0
EnterDebounceSt_A	5928678	56	0	0
EnterDetectSt_A	5928678	50	0	0
EnterStableSt_A	5928678	48	0	0
PulseIsPulse_A	5928678	48	0	0
StayInStableSt	5928678	58189	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5928678	1818	0	0
gen_low_level_sva.LowLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	105	0	0
T12	18567	2	0	0
T13	21523	0	0	0
T29	2930	2	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	2	0	0
T41	0	2	0	0
T43	0	4	0	0
T44	0	2	0	0
T46	8570	0	0	0
T48	11544	0	0	0
T59	0	2	0	0
T71	407	0	0	0
T84	0	4	0	0
T142	541	0	0	0
T169	0	4	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	57188	0	0
T12	18567	87	0	0
T13	21523	0	0	0
T29	2930	52	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	80	0	0
T41	0	81	0	0
T43	0	48	0	0
T44	0	72	0	0
T46	8570	0	0	0
T48	11544	0	0	0
T59	0	30	0	0
T71	407	0	0	0
T84	0	196	0	0
T142	541	0	0	0
T169	0	130	0	0
T174	0	55	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454347	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	2	0	0
T163	67812	0	0	0
T202	594	1	0	0
T207	0	1	0	0
T209	424	0	0	0
T210	1525	0	0	0
T211	17065	0	0	0
T212	507	0	0	0
T213	522	0	0	0
T214	424	0	0	0
T215	402	0	0	0
T216	411	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	58263	0	0
T12	18567	51	0	0
T13	21523	0	0	0
T29	2930	42	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	246	0	0
T41	0	39	0	0
T43	0	123	0	0
T44	0	13	0	0
T46	8570	0	0	0
T48	11544	0	0	0
T59	0	15	0	0
T71	407	0	0	0
T84	0	236	0	0
T142	541	0	0	0
T169	0	117	0	0
T174	0	121	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	48	0	0
T12	18567	1	0	0
T13	21523	0	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	8570	0	0	0
T48	11544	0	0	0
T59	0	1	0	0
T71	407	0	0	0
T84	0	2	0	0
T142	541	0	0	0
T169	0	2	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5220787	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5222719	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	56	0	0
T12	18567	1	0	0
T13	21523	0	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	8570	0	0	0
T48	11544	0	0	0
T59	0	1	0	0
T71	407	0	0	0
T84	0	2	0	0
T142	541	0	0	0
T169	0	2	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	50	0	0
T12	18567	1	0	0
T13	21523	0	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	8570	0	0	0
T48	11544	0	0	0
T59	0	1	0	0
T71	407	0	0	0
T84	0	2	0	0
T142	541	0	0	0
T169	0	2	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	48	0	0
T12	18567	1	0	0
T13	21523	0	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	8570	0	0	0
T48	11544	0	0	0
T59	0	1	0	0
T71	407	0	0	0
T84	0	2	0	0
T142	541	0	0	0
T169	0	2	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	48	0	0
T12	18567	1	0	0
T13	21523	0	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	8570	0	0	0
T48	11544	0	0	0
T59	0	1	0	0
T71	407	0	0	0
T84	0	2	0	0
T142	541	0	0	0
T169	0	2	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	58189	0	0
T12	18567	49	0	0
T13	21523	0	0	0
T29	2930	40	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	244	0	0
T41	0	37	0	0
T43	0	121	0	0
T44	0	11	0	0
T46	8570	0	0	0
T48	11544	0	0	0
T59	0	14	0	0
T71	407	0	0	0
T84	0	233	0	0
T142	541	0	0	0
T169	0	114	0	0
T174	0	119	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1818	0	0
T1	46391	0	0	0
T2	673	1	0	0
T3	991	1	0	0
T4	559	3	0	0
T5	863	0	0	0
T6	502	6	0	0
T14	424	2	0	0
T15	501	6	0	0
T16	1062	5	0	0
T17	0	3	0	0
T19	0	1	0	0
T21	526	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	21	0	0
T30	8666	0	0	0
T31	502	0	0	0
T41	636	0	0	0
T43	0	2	0	0
T53	3527	0	0	0
T63	1092	0	0	0
T84	3232	1	0	0
T120	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T184	0	2	0	0
T185	0	2	0	0
T186	0	1	0	0
T193	0	1	0	0
T203	778	0	0	0
T204	457	0	0	0
T205	454	0	0	0
T206	28004	0	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T21,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T21,T1
1	1	Covered	T6,T21,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T38,T44,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T38,T44,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T38,T44,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T38
1	0	Covered	T6,T21,T1
1	1	Covered	T38,T44,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T44,T42
0	1	Covered	T218,T219
1	0	Covered	T117

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T44,T42
0	1	Covered	T38,T42,T43
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T44,T42
1	-	Covered	T38,T42,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T44,T42
DetectSt	168	Covered	T38,T44,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T38,T44,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T44,T42
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T117,T218,T219
DetectSt->StableSt	191	Covered	T38,T44,T42
IdleSt->DebounceSt	148	Covered	T38,T44,T42
StableSt->IdleSt	206	Covered	T38,T44,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T44,T42
0	1	Covered	T38,T44,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T44,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T44,T42
IdleSt	0	-	-	-	-	-	-	Covered	T6,T21,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T44,T42
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T44,T42
DetectSt	-	-	-	-	1	-	-	Covered	T117,T218,T219
DetectSt	-	-	-	-	0	1	-	Covered	T38,T44,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T38,T44,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	84	0	0
CntIncr_A	5928678	53275	0	0
CntNoWrap_A	5928678	5454368	0	0
DetectStDropOut_A	5928678	2	0	0
DetectedOut_A	5928678	39385	0	0
DetectedPulseOut_A	5928678	39	0	0
DisabledIdleSt_A	5928678	5255297	0	0
DisabledNoDetection_A	5928678	5257240	0	0
EnterDebounceSt_A	5928678	42	0	0
EnterDetectSt_A	5928678	42	0	0
EnterStableSt_A	5928678	39	0	0
PulseIsPulse_A	5928678	39	0	0
StayInStableSt	5928678	39326	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	84	0	0
T37	13410	0	0	0
T38	1637	4	0	0
T39	1126	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	1968	2	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	2	0	0
T60	36357	0	0	0
T106	3198	0	0	0
T170	0	2	0	0
T171	0	4	0	0
T174	0	2	0	0
T193	0	2	0	0
T194	0	2	0	0
T220	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	53275	0	0
T37	13410	0	0	0
T38	1637	152	0	0
T39	1126	0	0	0
T42	0	10	0	0
T43	0	48	0	0
T44	1968	72	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	30	0	0
T60	36357	0	0	0
T106	3198	0	0	0
T170	0	65	0	0
T171	0	166	0	0
T174	0	55	0	0
T193	0	55	0	0
T194	0	14	0	0
T220	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454368	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	2	0	0
T101	1059	0	0	0
T218	705	1	0	0
T219	0	1	0	0
T221	2892	0	0	0
T222	5218	0	0	0
T223	426	0	0	0
T224	701	0	0	0
T225	617	0	0	0
T226	30185	0	0	0
T227	502	0	0	0
T228	535	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	39385	0	0
T37	13410	0	0	0
T38	1637	137	0	0
T39	1126	0	0	0
T42	0	76	0	0
T43	0	63	0	0
T44	1968	64	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	16	0	0
T60	36357	0	0	0
T106	3198	0	0	0
T170	0	155	0	0
T171	0	242	0	0
T174	0	45	0	0
T193	0	232	0	0
T194	0	62	0	0
T220	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	39	0	0
T37	13410	0	0	0
T38	1637	2	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	1	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T106	3198	0	0	0
T170	0	1	0	0
T171	0	2	0	0
T174	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T220	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5255297	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	4	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5257240	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	4	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	42	0	0
T37	13410	0	0	0
T38	1637	2	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	1	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T106	3198	0	0	0
T170	0	1	0	0
T171	0	2	0	0
T174	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T220	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	42	0	0
T37	13410	0	0	0
T38	1637	2	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	1	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T106	3198	0	0	0
T170	0	1	0	0
T171	0	2	0	0
T174	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T220	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	39	0	0
T37	13410	0	0	0
T38	1637	2	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	1	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T106	3198	0	0	0
T170	0	1	0	0
T171	0	2	0	0
T174	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T220	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	39	0	0
T37	13410	0	0	0
T38	1637	2	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	1	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T106	3198	0	0	0
T170	0	1	0	0
T171	0	2	0	0
T174	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T220	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	39326	0	0
T37	13410	0	0	0
T38	1637	134	0	0
T39	1126	0	0	0
T42	0	75	0	0
T43	0	61	0	0
T44	1968	62	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	15	0	0
T60	36357	0	0	0
T106	3198	0	0	0
T170	0	154	0	0
T171	0	239	0	0
T174	0	43	0	0
T193	0	230	0	0
T194	0	60	0	0
T220	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	18	0	0
T37	13410	0	0	0
T38	1637	1	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T60	36357	0	0	0
T106	3198	0	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T202	0	1	0	0
T217	0	1	0	0
T220	422	0	0	0
T229	0	1	0	0
T230	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T21,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T40,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T40,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T40,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T5,T6,T21
1	1	Covered	T40,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Covered	T231
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Covered	T184,T185,T202
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T41,T42
1	-	Covered	T184,T185,T202

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T41,T42
DetectSt	168	Covered	T40,T41,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T40,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T41,T42
DebounceSt->IdleSt	163	Covered	T185,T117
DetectSt->IdleSt	186	Covered	T231
DetectSt->StableSt	191	Covered	T40,T41,T42
IdleSt->DebounceSt	148	Covered	T40,T41,T42
StableSt->IdleSt	206	Covered	T40,T59,T150

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T41,T42
0	1	Covered	T40,T41,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T117
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T185
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T231
DetectSt	-	-	-	-	0	1	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T59,T184,T185
StableSt	-	-	-	-	-	-	0	Covered	T40,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	50	0	0
CntIncr_A	5928678	1206	0	0
CntNoWrap_A	5928678	5454402	0	0
DetectStDropOut_A	5928678	1	0	0
DetectedOut_A	5928678	1373	0	0
DetectedPulseOut_A	5928678	23	0	0
DisabledIdleSt_A	5928678	5442106	0	0
DisabledNoDetection_A	5928678	5444041	0	0
EnterDebounceSt_A	5928678	26	0	0
EnterDetectSt_A	5928678	24	0	0
EnterStableSt_A	5928678	23	0	0
PulseIsPulse_A	5928678	23	0	0
StayInStableSt	5928678	1338	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5928678	5301	0	0
gen_low_level_sva.LowLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	50	0	0
T26	823	0	0	0
T40	2390	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T52	775	0	0	0
T59	0	2	0	0
T107	1289	0	0	0
T110	406	0	0	0
T150	0	2	0	0
T170	0	2	0	0
T184	0	4	0	0
T185	0	3	0	0
T195	693	0	0	0
T196	506	0	0	0
T197	443	0	0	0
T198	403	0	0	0
T199	522	0	0	0
T202	0	2	0	0
T232	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1206	0	0
T26	823	0	0	0
T40	2390	44	0	0
T41	0	81	0	0
T42	0	10	0	0
T52	775	0	0	0
T59	0	30	0	0
T107	1289	0	0	0
T110	406	0	0	0
T150	0	12	0	0
T170	0	65	0	0
T184	0	57	0	0
T185	0	128	0	0
T195	693	0	0	0
T196	506	0	0	0
T197	443	0	0	0
T198	403	0	0	0
T199	522	0	0	0
T202	0	25	0	0
T232	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454402	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1	0	0
T231	902	1	0	0
T233	424	0	0	0
T234	422	0	0	0
T235	501	0	0	0
T236	6775	0	0	0
T237	1221	0	0	0
T238	3032	0	0	0
T239	1701	0	0	0
T240	422	0	0	0
T241	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1373	0	0
T26	823	0	0	0
T40	2390	46	0	0
T41	0	39	0	0
T42	0	38	0	0
T52	775	0	0	0
T59	0	14	0	0
T107	1289	0	0	0
T110	406	0	0	0
T150	0	49	0	0
T170	0	273	0	0
T184	0	67	0	0
T185	0	24	0	0
T195	693	0	0	0
T196	506	0	0	0
T197	443	0	0	0
T198	403	0	0	0
T199	522	0	0	0
T202	0	1	0	0
T232	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	23	0	0
T26	823	0	0	0
T40	2390	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T52	775	0	0	0
T59	0	1	0	0
T107	1289	0	0	0
T110	406	0	0	0
T150	0	1	0	0
T170	0	1	0	0
T184	0	2	0	0
T185	0	1	0	0
T195	693	0	0	0
T196	506	0	0	0
T197	443	0	0	0
T198	403	0	0	0
T199	522	0	0	0
T202	0	1	0	0
T232	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5442106	0	0
T1	46391	45968	0	0
T2	673	4	0	0
T3	991	4	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5444041	0	0
T1	46391	45980	0	0
T2	673	4	0	0
T3	991	4	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	26	0	0
T26	823	0	0	0
T40	2390	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T52	775	0	0	0
T59	0	1	0	0
T107	1289	0	0	0
T110	406	0	0	0
T150	0	1	0	0
T170	0	1	0	0
T184	0	2	0	0
T185	0	2	0	0
T195	693	0	0	0
T196	506	0	0	0
T197	443	0	0	0
T198	403	0	0	0
T199	522	0	0	0
T202	0	1	0	0
T232	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	24	0	0
T26	823	0	0	0
T40	2390	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T52	775	0	0	0
T59	0	1	0	0
T107	1289	0	0	0
T110	406	0	0	0
T150	0	1	0	0
T170	0	1	0	0
T184	0	2	0	0
T185	0	1	0	0
T195	693	0	0	0
T196	506	0	0	0
T197	443	0	0	0
T198	403	0	0	0
T199	522	0	0	0
T202	0	1	0	0
T232	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	23	0	0
T26	823	0	0	0
T40	2390	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T52	775	0	0	0
T59	0	1	0	0
T107	1289	0	0	0
T110	406	0	0	0
T150	0	1	0	0
T170	0	1	0	0
T184	0	2	0	0
T185	0	1	0	0
T195	693	0	0	0
T196	506	0	0	0
T197	443	0	0	0
T198	403	0	0	0
T199	522	0	0	0
T202	0	1	0	0
T232	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	23	0	0
T26	823	0	0	0
T40	2390	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T52	775	0	0	0
T59	0	1	0	0
T107	1289	0	0	0
T110	406	0	0	0
T150	0	1	0	0
T170	0	1	0	0
T184	0	2	0	0
T185	0	1	0	0
T195	693	0	0	0
T196	506	0	0	0
T197	443	0	0	0
T198	403	0	0	0
T199	522	0	0	0
T202	0	1	0	0
T232	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1338	0	0
T26	823	0	0	0
T40	2390	44	0	0
T41	0	37	0	0
T42	0	36	0	0
T52	775	0	0	0
T59	0	13	0	0
T107	1289	0	0	0
T110	406	0	0	0
T120	0	75	0	0
T150	0	47	0	0
T170	0	271	0	0
T184	0	65	0	0
T185	0	23	0	0
T195	693	0	0	0
T196	506	0	0	0
T197	443	0	0	0
T198	403	0	0	0
T199	522	0	0	0
T232	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5301	0	0
T1	46391	35	0	0
T2	673	0	0	0
T3	991	0	0	0
T6	502	3	0	0
T14	424	3	0	0
T15	501	5	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	24	0	0
T19	0	3	0	0
T20	0	5	0	0
T21	526	5	0	0
T83	0	8	0	0
T85	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	10	0	0
T172	0	1	0	0
T184	2721	2	0	0
T185	0	1	0	0
T202	0	1	0	0
T242	0	1	0	0
T243	0	1	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	0	1	0	0
T247	442	0	0	0
T248	522	0	0	0
T249	14046	0	0	0
T250	524	0	0	0
T251	496	0	0	0
T252	788	0	0	0
T253	431	0	0	0
T254	523	0	0	0
T255	35633	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T21,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T21,T1
1	1	Covered	T6,T21,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T29,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T42,T43
1	0	Covered	T6,T21,T1
1	1	Covered	T29,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T42,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T42,T43
0	1	Covered	T29,T43,T256
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T42,T43
1	-	Covered	T29,T43,T256

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T42,T43
DetectSt	168	Covered	T29,T42,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T29,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T42,T43
DebounceSt->IdleSt	163	Covered	T170,T184,T117
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T29,T42,T43
IdleSt->DebounceSt	148	Covered	T29,T42,T43
StableSt->IdleSt	206	Covered	T29,T43,T256

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T42,T43
0	1	Covered	T29,T42,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T42,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T6,T21,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T117
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T42,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T170,T184,T257
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T42,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T29,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T43,T256
StableSt	-	-	-	-	-	-	0	Covered	T29,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	93	0	0
CntIncr_A	5928678	2960	0	0
CntNoWrap_A	5928678	5454359	0	0
DetectStDropOut_A	5928678	0	0	0
DetectedOut_A	5928678	3444	0	0
DetectedPulseOut_A	5928678	44	0	0
DisabledIdleSt_A	5928678	5440865	0	0
DisabledNoDetection_A	5928678	5442803	0	0
EnterDebounceSt_A	5928678	49	0	0
EnterDetectSt_A	5928678	44	0	0
EnterStableSt_A	5928678	44	0	0
PulseIsPulse_A	5928678	44	0	0
StayInStableSt	5928678	3382	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	93	0	0
T29	2930	4	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	2	0	0
T60	36357	0	0	0
T142	541	0	0	0
T169	0	2	0	0
T170	0	3	0	0
T171	0	4	0	0
T174	0	2	0	0
T184	0	5	0	0
T256	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	2960	0	0
T29	2930	104	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T42	0	10	0	0
T43	0	48	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	30	0	0
T60	36357	0	0	0
T142	541	0	0	0
T169	0	65	0	0
T170	0	130	0	0
T171	0	166	0	0
T174	0	55	0	0
T184	0	117	0	0
T256	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454359	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	3444	0	0
T29	2930	224	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T42	0	125	0	0
T43	0	127	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	16	0	0
T60	36357	0	0	0
T142	541	0	0	0
T169	0	220	0	0
T170	0	166	0	0
T171	0	138	0	0
T174	0	121	0	0
T184	0	32	0	0
T256	0	187	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	44	0	0
T29	2930	2	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T142	541	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T174	0	1	0	0
T184	0	2	0	0
T256	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5440865	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5442803	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	49	0	0
T29	2930	2	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T142	541	0	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	2	0	0
T174	0	1	0	0
T184	0	3	0	0
T256	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	44	0	0
T29	2930	2	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T142	541	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T174	0	1	0	0
T184	0	2	0	0
T256	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	44	0	0
T29	2930	2	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T142	541	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T174	0	1	0	0
T184	0	2	0	0
T256	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	44	0	0
T29	2930	2	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T142	541	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T174	0	1	0	0
T184	0	2	0	0
T256	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	3382	0	0
T29	2930	221	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T42	0	123	0	0
T43	0	124	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	15	0	0
T60	36357	0	0	0
T142	541	0	0	0
T169	0	218	0	0
T170	0	164	0	0
T171	0	135	0	0
T174	0	119	0	0
T184	0	30	0	0
T256	0	186	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	25	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T43	0	1	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T60	36357	0	0	0
T121	0	1	0	0
T142	541	0	0	0
T171	0	1	0	0
T184	0	2	0	0
T201	0	1	0	0
T231	0	1	0	0
T232	0	1	0	0
T256	0	1	0	0
T258	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T21,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T29,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T39,T40
1	0	Covered	T5,T6,T21
1	1	Covered	T29,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T39,T40
0	1	Covered	T259
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T39,T40
0	1	Covered	T29,T40,T200
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T39,T40
1	-	Covered	T29,T40,T200

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T39,T40
DetectSt	168	Covered	T29,T39,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T29,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T39,T40
DebounceSt->IdleSt	163	Covered	T117,T246
DetectSt->IdleSt	186	Covered	T259
DetectSt->StableSt	191	Covered	T29,T39,T40
IdleSt->DebounceSt	148	Covered	T29,T39,T40
StableSt->IdleSt	206	Covered	T29,T40,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T39,T40
0	1	Covered	T29,T39,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T39,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T117
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T246
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T259
DetectSt	-	-	-	-	0	1	-	Covered	T29,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T40,T59
StableSt	-	-	-	-	-	-	0	Covered	T29,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	50	0	0
CntIncr_A	5928678	1624	0	0
CntNoWrap_A	5928678	5454402	0	0
DetectStDropOut_A	5928678	1	0	0
DetectedOut_A	5928678	2772	0	0
DetectedPulseOut_A	5928678	23	0	0
DisabledIdleSt_A	5928678	5442690	0	0
DisabledNoDetection_A	5928678	5444632	0	0
EnterDebounceSt_A	5928678	26	0	0
EnterDetectSt_A	5928678	24	0	0
EnterStableSt_A	5928678	23	0	0
PulseIsPulse_A	5928678	23	0	0
StayInStableSt	5928678	2738	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5928678	4988	0	0
gen_low_level_sva.LowLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	50	0	0
T29	2930	2	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	2	0	0
T40	0	2	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	2	0	0
T60	36357	0	0	0
T142	541	0	0	0
T183	0	4	0	0
T184	0	4	0	0
T200	0	4	0	0
T202	0	2	0	0
T232	0	2	0	0
T256	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1624	0	0
T29	2930	52	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	80	0	0
T40	0	44	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	30	0	0
T60	36357	0	0	0
T142	541	0	0	0
T183	0	136	0	0
T184	0	36	0	0
T200	0	148	0	0
T202	0	25	0	0
T232	0	51	0	0
T256	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5454402	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1	0	0
T259	706	1	0	0
T260	656	0	0	0
T261	505	0	0	0
T262	12180	0	0	0
T263	403	0	0	0
T264	624	0	0	0
T265	523	0	0	0
T266	20980	0	0	0
T267	24342	0	0	0
T268	4401	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	2772	0	0
T29	2930	40	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	124	0	0
T40	0	116	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	15	0	0
T60	36357	0	0	0
T142	541	0	0	0
T183	0	83	0	0
T184	0	46	0	0
T200	0	79	0	0
T202	0	40	0	0
T232	0	41	0	0
T256	0	201	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	23	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	1	0	0
T40	0	1	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T142	541	0	0	0
T183	0	2	0	0
T184	0	2	0	0
T200	0	2	0	0
T202	0	1	0	0
T232	0	1	0	0
T256	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5442690	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5444632	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	26	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	1	0	0
T40	0	1	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T142	541	0	0	0
T183	0	2	0	0
T184	0	2	0	0
T200	0	2	0	0
T202	0	1	0	0
T232	0	1	0	0
T256	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	24	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	1	0	0
T40	0	1	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T142	541	0	0	0
T183	0	2	0	0
T184	0	2	0	0
T200	0	2	0	0
T202	0	1	0	0
T232	0	1	0	0
T256	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	23	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	1	0	0
T40	0	1	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T142	541	0	0	0
T183	0	2	0	0
T184	0	2	0	0
T200	0	2	0	0
T202	0	1	0	0
T232	0	1	0	0
T256	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	23	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	1	0	0
T40	0	1	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	1	0	0
T60	36357	0	0	0
T142	541	0	0	0
T183	0	2	0	0
T184	0	2	0	0
T200	0	2	0	0
T202	0	1	0	0
T232	0	1	0	0
T256	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	2738	0	0
T29	2930	39	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	122	0	0
T40	0	115	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T59	0	14	0	0
T60	36357	0	0	0
T142	541	0	0	0
T183	0	81	0	0
T184	0	44	0	0
T200	0	77	0	0
T202	0	39	0	0
T232	0	39	0	0
T256	0	199	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4988	0	0
T1	46391	30	0	0
T2	673	1	0	0
T3	991	1	0	0
T6	502	6	0	0
T14	424	1	0	0
T15	501	3	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	27	0	0
T19	0	3	0	0
T20	0	5	0	0
T21	526	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	11	0	0
T29	2930	1	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T40	0	1	0	0
T44	1968	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T51	627	0	0	0
T60	36357	0	0	0
T142	541	0	0	0
T183	0	2	0	0
T184	0	2	0	0
T200	0	2	0	0
T202	0	1	0	0
T217	0	1	0	0
T244	0	1	0	0