Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T21,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T21,T1
1	1	Covered	T6,T21,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T6,T21,T1
1	1	Covered	T2,T3,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T38
0	1	Not Covered
1	0	Covered	T117

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T38
0	1	Covered	T40,T84,T43
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T38
1	-	Covered	T40,T84,T43

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T38
DetectSt	168	Covered	T2,T3,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T38
DebounceSt->IdleSt	163	Covered	T38,T184
DetectSt->IdleSt	186	Covered	T117
DetectSt->StableSt	191	Covered	T2,T3,T38
IdleSt->DebounceSt	148	Covered	T2,T3,T38
StableSt->IdleSt	206	Covered	T40,T84,T43

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T38
0	1	Covered	T2,T3,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T38
IdleSt	0	-	-	-	-	-	-	Covered	T6,T21,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T38
DetectSt	-	-	-	-	1	-	-	Covered	T117
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T84,T43
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	84	0	0
CntIncr_A	5928678	2230	0	0
CntNoWrap_A	5928678	5454368	0	0
DetectStDropOut_A	5928678	0	0	0
DetectedOut_A	5928678	4008	0	0
DetectedPulseOut_A	5928678	40	0	0
DisabledIdleSt_A	5928678	5442585	0	0
DisabledNoDetection_A	5928678	5444522	0	0
EnterDebounceSt_A	5928678	43	0	0
EnterDetectSt_A	5928678	41	0	0
EnterStableSt_A	5928678	40	0	0
PulseIsPulse_A	5928678	40	0	0
StayInStableSt	5928678	3943	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	14	0	0

CntClr_A

Name	Attempts	Real Successes
Total	5928678	84
T2	673	2
T3	991	2
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T38	0	3
T40	0	2
T43	0	4
T59	0	2
T84	0	4
T85	437	0
T86	910	0
T87	405	0
T168	0	4
T170	0	2
T200	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	5928678	2230
T2	673	36
T3	991	99
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T38	0	152
T40	0	44
T43	0	48
T59	0	30
T84	0	196
T85	437	0
T86	910	0
T87	405	0
T168	0	154
T170	0	65
T200	0	148

CntNoWrap_A

Name	Attempts	Real Successes
Total	5928678	5454368
T1	46391	45968
T2	673	270
T3	991	588
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	5928678	4008
T2	673	171
T3	991	287
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T38	0	176
T40	0	247
T43	0	127
T59	0	16
T84	0	227
T85	437	0
T86	910	0
T87	405	0
T168	0	219
T170	0	273
T200	0	437

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	5928678	40
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T38	0	1
T40	0	1
T43	0	2
T59	0	1
T84	0	2
T85	437	0
T86	910	0
T87	405	0
T168	0	2
T170	0	1
T200	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	5928678	5442585
T1	46391	45968
T2	673	4
T3	991	4
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	5928678	5444522
T1	46391	45980
T2	673	4
T3	991	4
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	5928678	43
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T38	0	2
T40	0	1
T43	0	2
T59	0	1
T84	0	2
T85	437	0
T86	910	0
T87	405	0
T168	0	2
T170	0	1
T200	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	5928678	41
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T38	0	1
T40	0	1
T43	0	2
T59	0	1
T84	0	2
T85	437	0
T86	910	0
T87	405	0
T168	0	2
T170	0	1
T200	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	5928678	40
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T38	0	1
T40	0	1
T43	0	2
T59	0	1
T84	0	2
T85	437	0
T86	910	0
T87	405	0
T168	0	2
T170	0	1
T200	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	5928678	40
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T38	0	1
T40	0	1
T43	0	2
T59	0	1
T84	0	2
T85	437	0
T86	910	0
T87	405	0
T168	0	2
T170	0	1
T200	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	5928678	3943
T2	673	169
T3	991	285
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T38	0	174
T40	0	246
T43	0	124
T59	0	15
T84	0	224
T85	437	0
T86	910	0
T87	405	0
T168	0	216
T170	0	271
T200	0	434

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	5928678	5456428
T1	46391	45980
T2	673	273
T3	991	591
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	5928678	14
T26	823	0
T40	2390	1
T43	0	1
T52	775	0
T84	0	1
T107	1289	0
T110	406	0
T168	0	1
T171	0	1
T172	0	1
T195	693	0
T196	506	0
T197	443	0
T198	403	0
T199	522	0
T200	0	1
T201	0	1
T217	0	1
T232	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T21,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T38,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T38,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T38,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T29
1	0	Covered	T5,T6,T21
1	1	Covered	T38,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Covered	T38,T39,T43
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T39,T40
1	-	Covered	T38,T39,T43

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T39,T40
DetectSt	168	Covered	T38,T39,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T38,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T39,T40
DebounceSt->IdleSt	163	Covered	T117
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T38,T39,T40
IdleSt->DebounceSt	148	Covered	T38,T39,T40
StableSt->IdleSt	206	Covered	T38,T39,T40

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T39,T40
0	1	Covered	T38,T39,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T117
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T39,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T39,T43
StableSt	-	-	-	-	-	-	0	Covered	T38,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	61	0	0
CntIncr_A	5928678	1834	0	0
CntNoWrap_A	5928678	5454391	0	0
DetectStDropOut_A	5928678	0	0	0
DetectedOut_A	5928678	2858	0	0
DetectedPulseOut_A	5928678	30	0	0
DisabledIdleSt_A	5928678	5439718	0	0
DisabledNoDetection_A	5928678	5441652	0	0
EnterDebounceSt_A	5928678	31	0	0
EnterDetectSt_A	5928678	30	0	0
EnterStableSt_A	5928678	30	0	0
PulseIsPulse_A	5928678	30	0	0
StayInStableSt	5928678	2813	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5928678	5138	0	0
gen_low_level_sva.LowLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	14	0	0

CntClr_A

Name	Attempts	Real Successes
Total	5928678	61
T37	13410	0
T38	1637	2
T39	1126	4
T40	0	2
T43	0	2
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T59	0	2
T60	36357	0
T106	3198	0
T171	0	2
T184	0	2
T185	0	2
T201	0	2
T220	422	0
T256	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	5928678	1834
T37	13410	0
T38	1637	76
T39	1126	160
T40	0	44
T43	0	24
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T59	0	30
T60	36357	0
T106	3198	0
T171	0	83
T184	0	18
T185	0	64
T201	0	28
T220	422	0
T256	0	176

CntNoWrap_A

Name	Attempts	Real Successes
Total	5928678	5454391
T1	46391	45968
T2	673	272
T3	991	590
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	5928678	2858
T37	13410	0
T38	1637	41
T39	1126	288
T40	0	45
T43	0	72
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T59	0	14
T60	36357	0
T106	3198	0
T171	0	507
T184	0	145
T185	0	168
T201	0	87
T220	422	0
T256	0	86

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	5928678	30
T37	13410	0
T38	1637	1
T39	1126	2
T40	0	1
T43	0	1
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T59	0	1
T60	36357	0
T106	3198	0
T171	0	1
T184	0	1
T185	0	1
T201	0	1
T220	422	0
T256	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	5928678	5439718
T1	46391	45968
T2	673	4
T3	991	4
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	5928678	5441652
T1	46391	45980
T2	673	4
T3	991	4
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	5928678	31
T37	13410	0
T38	1637	1
T39	1126	2
T40	0	1
T43	0	1
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T59	0	1
T60	36357	0
T106	3198	0
T171	0	1
T184	0	1
T185	0	1
T201	0	1
T220	422	0
T256	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	5928678	30
T37	13410	0
T38	1637	1
T39	1126	2
T40	0	1
T43	0	1
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T59	0	1
T60	36357	0
T106	3198	0
T171	0	1
T184	0	1
T185	0	1
T201	0	1
T220	422	0
T256	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	5928678	30
T37	13410	0
T38	1637	1
T39	1126	2
T40	0	1
T43	0	1
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T59	0	1
T60	36357	0
T106	3198	0
T171	0	1
T184	0	1
T185	0	1
T201	0	1
T220	422	0
T256	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	5928678	30
T37	13410	0
T38	1637	1
T39	1126	2
T40	0	1
T43	0	1
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T59	0	1
T60	36357	0
T106	3198	0
T171	0	1
T184	0	1
T185	0	1
T201	0	1
T220	422	0
T256	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	5928678	2813
T37	13410	0
T38	1637	40
T39	1126	285
T40	0	43
T43	0	71
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T59	0	13
T60	36357	0
T106	3198	0
T171	0	505
T184	0	144
T185	0	167
T201	0	86
T220	422	0
T256	0	83

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	5928678	5138
T1	46391	32
T2	673	0
T3	991	0
T6	502	6
T14	424	3
T15	501	4
T16	1062	0
T17	667	0
T18	4367	24
T19	0	2
T20	0	7
T21	526	6
T83	0	11
T85	0	1

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	5928678	5456428
T1	46391	45980
T2	673	273
T3	991	591
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	5928678	14
T37	13410	0
T38	1637	1
T39	1126	1
T43	0	1
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T60	36357	0
T106	3198	0
T184	0	1
T185	0	1
T201	0	1
T220	422	0
T242	0	2
T256	0	1
T269	0	1
T270	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T21,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T21,T1
1	1	Covered	T6,T21,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T12,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T39
1	0	Covered	T6,T21,T1
1	1	Covered	T3,T12,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T39
0	1	Covered	T43,T120,T270
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T39
0	1	Covered	T3,T12,T39
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T12,T39
1	-	Covered	T3,T12,T39

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T12,T39
DetectSt	168	Covered	T3,T12,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T12,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T12,T39
DebounceSt->IdleSt	163	Covered	T170,T185,T120
DetectSt->IdleSt	186	Covered	T43,T120,T270
DetectSt->StableSt	191	Covered	T3,T12,T39
IdleSt->DebounceSt	148	Covered	T3,T12,T39
StableSt->IdleSt	206	Covered	T3,T12,T39

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T12,T39
0	1	Covered	T3,T12,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T39
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T12,T39
IdleSt	0	-	-	-	-	-	-	Covered	T6,T21,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T117
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T12,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T170,T185,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T12,T39
DetectSt	-	-	-	-	1	-	-	Covered	T43,T120,T270
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T12,T39
StableSt	-	-	-	-	-	-	0	Covered	T3,T12,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	100	0	0
CntIncr_A	5928678	25608	0	0
CntNoWrap_A	5928678	5454352	0	0
DetectStDropOut_A	5928678	5	0	0
DetectedOut_A	5928678	103993	0	0
DetectedPulseOut_A	5928678	43	0	0
DisabledIdleSt_A	5928678	5263043	0	0
DisabledNoDetection_A	5928678	5264983	0	0
EnterDebounceSt_A	5928678	52	0	0
EnterDetectSt_A	5928678	48	0	0
EnterStableSt_A	5928678	43	0	0
PulseIsPulse_A	5928678	43	0	0
StayInStableSt	5928678	103928	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	20	0	0

CntClr_A

Name	Attempts	Real Successes
Total	5928678	100
T3	991	4
T12	0	2
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T39	0	2
T42	0	2
T43	0	4
T59	0	2
T83	3556	0
T84	0	2
T85	437	0
T86	910	0
T87	405	0
T168	0	4
T169	0	2
T170	0	3
T175	408	0

CntIncr_A

Name	Attempts	Real Successes
Total	5928678	25608
T3	991	198
T12	0	87
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T39	0	80
T42	0	10
T43	0	48
T59	0	30
T83	3556	0
T84	0	98
T85	437	0
T86	910	0
T87	405	0
T168	0	154
T169	0	65
T170	0	130
T175	408	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	5928678	5454352
T1	46391	45968
T2	673	272
T3	991	586
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DetectStDropOut_A

Name	Attempts	Real Successes
Total	5928678	5
T43	683	1
T120	0	1
T167	0	1
T246	0	1
T256	975	0
T270	0	1
T271	423	0
T272	422	0
T273	593	0
T274	492	0
T275	19217	0
T276	601	0
T277	506	0
T278	451	0

DetectedOut_A

Name	Attempts	Real Successes
Total	5928678	103993
T3	991	281
T12	0	46
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T39	0	242
T42	0	57
T43	0	83
T59	0	16
T83	3556	0
T84	0	43
T85	437	0
T86	910	0
T87	405	0
T168	0	71
T169	0	289
T170	0	40
T175	408	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	5928678	43
T3	991	2
T12	0	1
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T39	0	1
T42	0	1
T43	0	1
T59	0	1
T83	3556	0
T84	0	1
T85	437	0
T86	910	0
T87	405	0
T168	0	2
T169	0	1
T170	0	1
T175	408	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	5928678	5263043
T1	46391	45968
T2	673	272
T3	991	4
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	5928678	5264983
T1	46391	45980
T2	673	273
T3	991	4
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	5928678	52
T3	991	2
T12	0	1
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T39	0	1
T42	0	1
T43	0	2
T59	0	1
T83	3556	0
T84	0	1
T85	437	0
T86	910	0
T87	405	0
T168	0	2
T169	0	1
T170	0	2
T175	408	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	5928678	48
T3	991	2
T12	0	1
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T39	0	1
T42	0	1
T43	0	2
T59	0	1
T83	3556	0
T84	0	1
T85	437	0
T86	910	0
T87	405	0
T168	0	2
T169	0	1
T170	0	1
T175	408	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	5928678	43
T3	991	2
T12	0	1
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T39	0	1
T42	0	1
T43	0	1
T59	0	1
T83	3556	0
T84	0	1
T85	437	0
T86	910	0
T87	405	0
T168	0	2
T169	0	1
T170	0	1
T175	408	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	5928678	43
T3	991	2
T12	0	1
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T39	0	1
T42	0	1
T43	0	1
T59	0	1
T83	3556	0
T84	0	1
T85	437	0
T86	910	0
T87	405	0
T168	0	2
T169	0	1
T170	0	1
T175	408	0

StayInStableSt

Name	Attempts	Real Successes
Total	5928678	103928
T3	991	278
T12	0	45
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T39	0	241
T42	0	55
T43	0	82
T59	0	15
T83	3556	0
T84	0	41
T85	437	0
T86	910	0
T87	405	0
T168	0	68
T169	0	287
T170	0	38
T175	408	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	5928678	5456428
T1	46391	45980
T2	673	273
T3	991	591
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	5928678	20
T3	991	1
T12	0	1
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T39	0	1
T43	0	1
T83	3556	0
T85	437	0
T86	910	0
T87	405	0
T168	0	1
T171	0	2
T175	408	0
T185	0	1
T201	0	1
T231	0	1
T269	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T21,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T29,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T29,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T29,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T29,T38
1	0	Covered	T5,T6,T21
1	1	Covered	T2,T29,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T29,T38
0	1	Not Covered
1	0	Covered	T117

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T29,T38
0	1	Covered	T2,T29,T38
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T29,T38
1	-	Covered	T2,T29,T38

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T29,T38
DetectSt	168	Covered	T2,T29,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T29,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T29,T38
DebounceSt->IdleSt	163	Covered	T167
DetectSt->IdleSt	186	Covered	T117
DetectSt->StableSt	191	Covered	T2,T29,T38
IdleSt->DebounceSt	148	Covered	T2,T29,T38
StableSt->IdleSt	206	Covered	T2,T29,T38

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T29,T38
0	1	Covered	T2,T29,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T29,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T29,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T29,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T167
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T29,T38
DetectSt	-	-	-	-	1	-	-	Covered	T117
DetectSt	-	-	-	-	0	1	-	Covered	T2,T29,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T29,T38
StableSt	-	-	-	-	-	-	0	Covered	T2,T29,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	59	0	0
CntIncr_A	5928678	1739	0	0
CntNoWrap_A	5928678	5454393	0	0
DetectStDropOut_A	5928678	0	0	0
DetectedOut_A	5928678	1934	0	0
DetectedPulseOut_A	5928678	28	0	0
DisabledIdleSt_A	5928678	5429134	0	0
DisabledNoDetection_A	5928678	5431069	0	0
EnterDebounceSt_A	5928678	30	0	0
EnterDetectSt_A	5928678	29	0	0
EnterStableSt_A	5928678	28	0	0
PulseIsPulse_A	5928678	28	0	0
StayInStableSt	5928678	1892	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5928678	5087	0	0
gen_low_level_sva.LowLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	13	0	0

CntClr_A

Name	Attempts	Real Successes
Total	5928678	59
T2	673	2
T3	991	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	2
T38	0	4
T39	0	2
T40	0	2
T43	0	4
T59	0	2
T85	437	0
T86	910	0
T87	405	0
T170	0	2
T171	0	4
T256	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	5928678	1739
T2	673	36
T3	991	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	52
T38	0	152
T39	0	80
T40	0	44
T43	0	48
T59	0	30
T85	437	0
T86	910	0
T87	405	0
T170	0	65
T171	0	166
T256	0	176

CntNoWrap_A

Name	Attempts	Real Successes
Total	5928678	5454393
T1	46391	45968
T2	673	270
T3	991	590
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	5928678	1934
T2	673	11
T3	991	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	220
T38	0	81
T39	0	38
T40	0	179
T43	0	92
T59	0	15
T85	437	0
T86	910	0
T87	405	0
T170	0	167
T171	0	115
T256	0	84

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	5928678	28
T2	673	1
T3	991	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T38	0	2
T39	0	1
T40	0	1
T43	0	2
T59	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	1
T171	0	2
T256	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	5928678	5429134
T1	46391	45968
T2	673	4
T3	991	590
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	5928678	5431069
T1	46391	45980
T2	673	4
T3	991	591
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	5928678	30
T2	673	1
T3	991	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T38	0	2
T39	0	1
T40	0	1
T43	0	2
T59	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	1
T171	0	2
T256	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	5928678	29
T2	673	1
T3	991	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T38	0	2
T39	0	1
T40	0	1
T43	0	2
T59	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	1
T171	0	2
T256	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	5928678	28
T2	673	1
T3	991	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T38	0	2
T39	0	1
T40	0	1
T43	0	2
T59	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	1
T171	0	2
T256	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	5928678	28
T2	673	1
T3	991	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T38	0	2
T39	0	1
T40	0	1
T43	0	2
T59	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	1
T171	0	2
T256	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	5928678	1892
T2	673	10
T3	991	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	219
T38	0	78
T39	0	36
T40	0	177
T43	0	89
T59	0	14
T85	437	0
T86	910	0
T87	405	0
T170	0	166
T171	0	113
T256	0	81

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	5928678	5087
T1	46391	39
T2	673	1
T3	991	1
T6	502	3
T14	424	3
T15	501	5
T16	1062	0
T17	667	0
T18	4367	26
T19	0	2
T20	0	5
T21	526	4

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	5928678	5456428
T1	46391	45980
T2	673	273
T3	991	591
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	5928678	13
T2	673	1
T3	991	0
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T38	0	1
T43	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	1
T171	0	2
T172	0	1
T185	0	2
T242	0	1
T256	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T21,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T21,T1
1	1	Covered	T6,T21,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T29
1	0	Covered	T6,T21,T1
1	1	Covered	T2,T3,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T29
0	1	Not Covered
1	0	Covered	T117

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T29
0	1	Covered	T2,T3,T29
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T29
1	-	Covered	T2,T3,T29

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T29
DetectSt	168	Covered	T2,T3,T29
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T29
DebounceSt->IdleSt	163	Covered	T120,T279,T280
DetectSt->IdleSt	186	Covered	T117
DetectSt->StableSt	191	Covered	T2,T3,T29
IdleSt->DebounceSt	148	Covered	T2,T3,T29
StableSt->IdleSt	206	Covered	T2,T3,T29

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T29
0	1	Covered	T2,T3,T29
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T29
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T29
IdleSt	0	-	-	-	-	-	-	Covered	T6,T21,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T120,T279
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T29
DetectSt	-	-	-	-	1	-	-	Covered	T117
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T29
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	82	0	0
CntIncr_A	5928678	132962	0	0
CntNoWrap_A	5928678	5454370	0	0
DetectStDropOut_A	5928678	0	0	0
DetectedOut_A	5928678	193581	0	0
DetectedPulseOut_A	5928678	39	0	0
DisabledIdleSt_A	5928678	5045381	0	0
DisabledNoDetection_A	5928678	5047319	0	0
EnterDebounceSt_A	5928678	43	0	0
EnterDetectSt_A	5928678	40	0	0
EnterStableSt_A	5928678	39	0	0
PulseIsPulse_A	5928678	39	0	0
StayInStableSt	5928678	193523	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	19	0	0

CntClr_A

Name	Attempts	Real Successes
Total	5928678	82
T2	673	2
T3	991	2
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	4
T38	0	2
T43	0	2
T44	0	2
T59	0	2
T85	437	0
T86	910	0
T87	405	0
T170	0	4
T173	0	2
T256	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	5928678	132962
T2	673	36
T3	991	99
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	104
T38	0	76
T43	0	24
T44	0	72
T59	0	30
T85	437	0
T86	910	0
T87	405	0
T170	0	130
T173	0	31
T256	0	176

CntNoWrap_A

Name	Attempts	Real Successes
Total	5928678	5454370
T1	46391	45968
T2	673	270
T3	991	588
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	5928678	193581
T2	673	90
T3	991	338
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	299
T38	0	294
T43	0	40
T44	0	63
T59	0	15
T85	437	0
T86	910	0
T87	405	0
T170	0	104
T173	0	38
T256	0	257

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	5928678	39
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	2
T38	0	1
T43	0	1
T44	0	1
T59	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	2
T173	0	1
T256	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	5928678	5045381
T1	46391	45968
T2	673	4
T3	991	4
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	5928678	5047319
T1	46391	45980
T2	673	4
T3	991	4
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	5928678	43
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	2
T38	0	1
T43	0	1
T44	0	1
T59	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	2
T173	0	1
T256	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	5928678	40
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	2
T38	0	1
T43	0	1
T44	0	1
T59	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	2
T173	0	1
T256	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	5928678	39
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	2
T38	0	1
T43	0	1
T44	0	1
T59	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	2
T173	0	1
T256	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	5928678	39
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	2
T38	0	1
T43	0	1
T44	0	1
T59	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	2
T173	0	1
T256	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	5928678	193523
T2	673	89
T3	991	337
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	296
T38	0	292
T43	0	39
T44	0	61
T59	0	14
T85	437	0
T86	910	0
T87	405	0
T170	0	102
T173	0	36
T256	0	254

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	5928678	5456428
T1	46391	45980
T2	673	273
T3	991	591
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	5928678	19
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T43	0	1
T85	437	0
T86	910	0
T87	405	0
T170	0	2
T183	0	1
T184	0	1
T201	0	1
T217	0	1
T256	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T21,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T21,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T29
1	0	Covered	T5,T6,T21
1	1	Covered	T2,T3,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T29
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T29
0	1	Covered	T29,T84,T256
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T29
1	-	Covered	T29,T84,T256

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T29
DetectSt	168	Covered	T2,T3,T29
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T29
DebounceSt->IdleSt	163	Covered	T117
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T3,T29
IdleSt->DebounceSt	148	Covered	T2,T3,T29
StableSt->IdleSt	206	Covered	T29,T84,T256

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T29
0	1	Covered	T2,T3,T29
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T29
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T29
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T117
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T29
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T29
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T84,T256
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	51	0	0
CntIncr_A	5928678	23994	0	0
CntNoWrap_A	5928678	5454401	0	0
DetectStDropOut_A	5928678	0	0	0
DetectedOut_A	5928678	1649	0	0
DetectedPulseOut_A	5928678	25	0	0
DisabledIdleSt_A	5928678	5265477	0	0
DisabledNoDetection_A	5928678	5267417	0	0
EnterDebounceSt_A	5928678	26	0	0
EnterDetectSt_A	5928678	25	0	0
EnterStableSt_A	5928678	25	0	0
PulseIsPulse_A	5928678	25	0	0
StayInStableSt	5928678	1609	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5928678	5578	0	0
gen_low_level_sva.LowLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	9	0	0

CntClr_A

Name	Attempts	Real Successes
Total	5928678	51
T2	673	2
T3	991	2
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	2
T59	0	2
T84	0	2
T85	437	0
T86	910	0
T87	405	0
T171	0	4
T184	0	4
T217	0	2
T256	0	2
T281	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	5928678	23994
T2	673	36
T3	991	99
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	52
T59	0	30
T84	0	98
T85	437	0
T86	910	0
T87	405	0
T171	0	166
T184	0	57
T217	0	94
T256	0	88
T281	0	90

CntNoWrap_A

Name	Attempts	Real Successes
Total	5928678	5454401
T1	46391	45968
T2	673	270
T3	991	588
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	5928678	1649
T2	673	45
T3	991	44
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	36
T59	0	15
T84	0	205
T85	437	0
T86	910	0
T87	405	0
T171	0	85
T184	0	123
T217	0	43
T256	0	42
T281	0	38

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	5928678	25
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T59	0	1
T84	0	1
T85	437	0
T86	910	0
T87	405	0
T171	0	2
T184	0	2
T217	0	1
T256	0	1
T281	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	5928678	5265477
T1	46391	45968
T2	673	4
T3	991	4
T4	559	158
T5	863	2
T6	502	101
T14	424	23
T15	501	100
T16	1062	661
T21	526	125

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	5928678	5267417
T1	46391	45980
T2	673	4
T3	991	4
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	5928678	26
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T59	0	1
T84	0	1
T85	437	0
T86	910	0
T87	405	0
T171	0	2
T184	0	2
T217	0	1
T256	0	1
T281	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	5928678	25
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T59	0	1
T84	0	1
T85	437	0
T86	910	0
T87	405	0
T171	0	2
T184	0	2
T217	0	1
T256	0	1
T281	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	5928678	25
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T59	0	1
T84	0	1
T85	437	0
T86	910	0
T87	405	0
T171	0	2
T184	0	2
T217	0	1
T256	0	1
T281	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	5928678	25
T2	673	1
T3	991	1
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	1
T59	0	1
T84	0	1
T85	437	0
T86	910	0
T87	405	0
T171	0	2
T184	0	2
T217	0	1
T256	0	1
T281	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	5928678	1609
T2	673	43
T3	991	42
T16	1062	0
T17	667	0
T18	4367	0
T19	423	0
T20	503	0
T29	0	35
T59	0	14
T84	0	204
T85	437	0
T86	910	0
T87	405	0
T171	0	82
T184	0	119
T217	0	41
T256	0	41
T281	0	36

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	5928678	5578
T1	46391	32
T2	673	1
T3	991	1
T6	502	4
T14	424	2
T15	501	4
T16	1062	0
T17	667	0
T18	4367	36
T19	0	3
T20	0	3
T21	526	5

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	5928678	5456428
T1	46391	45980
T2	673	273
T3	991	591
T4	559	159
T5	863	8
T6	502	102
T14	424	24
T15	501	101
T16	1062	662
T21	526	126

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	5928678	9
T29	2930	1
T37	13410	0
T38	1637	0
T39	1126	0
T44	1968	0
T49	691	0
T50	738	0
T51	627	0
T60	36357	0
T84	0	1
T142	541	0
T167	0	1
T171	0	1
T187	0	1
T207	0	1
T230	0	1
T245	0	1
T256	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr