Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T8
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T18,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T8
0	1	Covered	T18,T11,T89
1	0	Covered	T11,T118,T134

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T9
1	-	Covered	T1,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T8
DetectSt	168	Covered	T1,T18,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T8
DebounceSt->IdleSt	163	Covered	T59,T282,T117
DetectSt->IdleSt	186	Covered	T18,T11,T89
DetectSt->StableSt	191	Covered	T1,T8,T9
IdleSt->DebounceSt	148	Covered	T1,T18,T8
StableSt->IdleSt	206	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T18,T8
0	1	Covered	T1,T18,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T18,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T59,T282,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T8
DetectSt	-	-	-	-	1	-	-	Covered	T18,T11,T89
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T18,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	2973	0	0
CntIncr_A	5928678	108107	0	0
CntNoWrap_A	5928678	5451479	0	0
DetectStDropOut_A	5928678	468	0	0
DetectedOut_A	5928678	81807	0	0
DetectedPulseOut_A	5928678	841	0	0
DisabledIdleSt_A	5928678	4964197	0	0
DisabledNoDetection_A	5928678	4965958	0	0
EnterDebounceSt_A	5928678	1500	0	0
EnterDetectSt_A	5928678	1473	0	0
EnterStableSt_A	5928678	841	0	0
PulseIsPulse_A	5928678	841	0	0
StayInStableSt	5928678	80842	0	0
gen_high_event_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	716	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	2973	0	0
T1	46391	32	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	28	0	0
T9	0	46	0	0
T11	0	52	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	22	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	20	0	0
T48	0	20	0	0
T60	0	30	0	0
T88	0	14	0	0
T89	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	108107	0	0
T1	46391	4192	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	840	0	0
T9	0	1518	0	0
T11	0	2145	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	382	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	560	0	0
T48	0	750	0	0
T60	0	4440	0	0
T88	0	525	0	0
T89	0	1564	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5451479	0	0
T1	46391	45936	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	468	0	0
T11	0	14	0	0
T18	4367	11	0	0
T19	423	0	0	0
T20	503	0	0	0
T28	497	0	0	0
T59	0	1	0	0
T79	508	0	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T89	0	22	0	0
T130	0	22	0	0
T133	0	24	0	0
T134	0	16	0	0
T136	0	29	0	0
T175	408	0	0	0
T283	0	9	0	0
T284	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	81807	0	0
T1	46391	4435	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	1279	0	0
T9	0	2849	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	337	0	0
T48	0	451	0	0
T60	0	3209	0	0
T88	0	226	0	0
T285	0	52	0	0
T286	0	43	0	0
T287	0	75	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	841	0	0
T1	46391	16	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	14	0	0
T9	0	23	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	10	0	0
T48	0	10	0	0
T60	0	15	0	0
T88	0	7	0	0
T285	0	5	0	0
T286	0	1	0	0
T287	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4964197	0	0
T1	46391	27192	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4965958	0	0
T1	46391	27199	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1500	0	0
T1	46391	16	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	14	0	0
T9	0	23	0	0
T11	0	26	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	11	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	10	0	0
T48	0	10	0	0
T60	0	15	0	0
T88	0	7	0	0
T89	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1473	0	0
T1	46391	16	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	14	0	0
T9	0	23	0	0
T11	0	26	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	11	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	10	0	0
T48	0	10	0	0
T60	0	15	0	0
T88	0	7	0	0
T89	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	841	0	0
T1	46391	16	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	14	0	0
T9	0	23	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	10	0	0
T48	0	10	0	0
T60	0	15	0	0
T88	0	7	0	0
T285	0	5	0	0
T286	0	1	0	0
T287	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	841	0	0
T1	46391	16	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	14	0	0
T9	0	23	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	10	0	0
T48	0	10	0	0
T60	0	15	0	0
T88	0	7	0	0
T285	0	5	0	0
T286	0	1	0	0
T287	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	80842	0	0
T1	46391	4415	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	1264	0	0
T9	0	2823	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	327	0	0
T48	0	440	0	0
T60	0	3192	0	0
T88	0	219	0	0
T285	0	47	0	0
T286	0	41	0	0
T287	0	73	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	716	0	0
T1	46391	12	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	13	0	0
T9	0	20	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	10	0	0
T48	0	9	0	0
T60	0	13	0	0
T88	0	7	0	0
T285	0	5	0	0
T288	0	9	0	0
T289	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T7,T45

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T45
1	0	Covered	T5,T1,T18
1	1	Covered	T1,T7,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T45
0	1	Covered	T116,T128,T129
1	0	Covered	T59,T117

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T45
0	1	Covered	T1,T7,T45
1	0	Covered	T59,T117

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T45
1	-	Covered	T1,T7,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T45
DetectSt	168	Covered	T1,T7,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T45
DebounceSt->IdleSt	163	Covered	T45,T33,T37
DetectSt->IdleSt	186	Covered	T116,T128,T129
DetectSt->StableSt	191	Covered	T1,T7,T45
IdleSt->DebounceSt	148	Covered	T1,T7,T45
StableSt->IdleSt	206	Covered	T1,T7,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T45
0	1	Covered	T1,T7,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T33,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T45
DetectSt	-	-	-	-	1	-	-	Covered	T116,T128,T129
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T45
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T45
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T45
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	780	0	0
CntIncr_A	5928678	44216	0	0
CntNoWrap_A	5928678	5453672	0	0
DetectStDropOut_A	5928678	47	0	0
DetectedOut_A	5928678	13973	0	0
DetectedPulseOut_A	5928678	308	0	0
DisabledIdleSt_A	5928678	5082813	0	0
DisabledNoDetection_A	5928678	5084127	0	0
EnterDebounceSt_A	5928678	421	0	0
EnterDetectSt_A	5928678	359	0	0
EnterStableSt_A	5928678	308	0	0
PulseIsPulse_A	5928678	308	0	0
StayInStableSt	5928678	13647	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	287	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	780	0	0
T1	46391	8	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	20	0	0
T8	0	2	0	0
T9	0	4	0	0
T12	0	4	0	0
T13	0	8	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T33	0	1	0	0
T45	0	21	0	0
T47	0	6	0	0
T48	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	44216	0	0
T1	46391	1068	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	1720	0	0
T8	0	85	0	0
T9	0	144	0	0
T12	0	360	0	0
T13	0	564	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T33	0	20	0	0
T45	0	1104	0	0
T47	0	348	0	0
T48	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5453672	0	0
T1	46391	45960	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	47	0	0
T64	1027	0	0	0
T78	489	0	0	0
T116	15682	3	0	0
T127	691	0	0	0
T128	18628	3	0	0
T129	0	7	0	0
T131	0	2	0	0
T132	0	3	0	0
T135	0	10	0	0
T137	0	1	0	0
T138	0	5	0	0
T139	0	7	0	0
T141	0	2	0	0
T143	744	0	0	0
T144	7098	0	0	0
T145	534	0	0	0
T146	422	0	0	0
T147	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	13973	0	0
T1	46391	222	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	58	0	0
T8	0	54	0	0
T9	0	141	0	0
T12	0	10	0	0
T13	0	102	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	156	0	0
T45	0	350	0	0
T47	0	91	0	0
T48	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	308	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	10	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	10	0	0
T47	0	3	0	0
T48	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5082813	0	0
T1	46391	41537	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5084127	0	0
T1	46391	41545	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	421	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	10	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T33	0	1	0	0
T45	0	11	0	0
T47	0	3	0	0
T48	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	359	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	10	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	10	0	0
T47	0	3	0	0
T48	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	308	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	10	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	10	0	0
T47	0	3	0	0
T48	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	308	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	10	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	10	0	0
T47	0	3	0	0
T48	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	13647	0	0
T1	46391	218	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	48	0	0
T8	0	53	0	0
T9	0	139	0	0
T12	0	8	0	0
T13	0	98	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	154	0	0
T45	0	340	0	0
T47	0	88	0	0
T48	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	287	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	10	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	10	0	0
T47	0	3	0	0
T60	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T8
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T18,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T8
0	1	Covered	T18,T11,T89
1	0	Covered	T11,T290,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
1	0	Covered	T59,T119,T291

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T9
1	-	Covered	T1,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T8
DetectSt	168	Covered	T1,T18,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T8
DebounceSt->IdleSt	163	Covered	T59,T282,T117
DetectSt->IdleSt	186	Covered	T18,T11,T89
DetectSt->StableSt	191	Covered	T1,T8,T9
IdleSt->DebounceSt	148	Covered	T1,T18,T8
StableSt->IdleSt	206	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T18,T8
0	1	Covered	T1,T18,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T18,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T59,T282,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T8
DetectSt	-	-	-	-	1	-	-	Covered	T18,T11,T89
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T18,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	3217	0	0
CntIncr_A	5928678	115775	0	0
CntNoWrap_A	5928678	5451235	0	0
DetectStDropOut_A	5928678	456	0	0
DetectedOut_A	5928678	82201	0	0
DetectedPulseOut_A	5928678	943	0	0
DisabledIdleSt_A	5928678	4962356	0	0
DisabledNoDetection_A	5928678	4964104	0	0
EnterDebounceSt_A	5928678	1624	0	0
EnterDetectSt_A	5928678	1594	0	0
EnterStableSt_A	5928678	943	0	0
PulseIsPulse_A	5928678	943	0	0
StayInStableSt	5928678	81121	0	0
gen_high_event_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	791	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	3217	0	0
T1	46391	32	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	56	0	0
T9	0	24	0	0
T11	0	60	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	26	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	54	0	0
T48	0	44	0	0
T60	0	54	0	0
T88	0	26	0	0
T89	0	42	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	115775	0	0
T1	46391	4256	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	1792	0	0
T9	0	1140	0	0
T11	0	2474	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	448	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	1863	0	0
T48	0	1540	0	0
T60	0	8478	0	0
T88	0	780	0	0
T89	0	1491	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5451235	0	0
T1	46391	45936	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	456	0	0
T11	0	17	0	0
T18	4367	13	0	0
T19	423	0	0	0
T20	503	0	0	0
T28	497	0	0	0
T59	0	1	0	0
T79	508	0	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T89	0	21	0	0
T130	0	17	0	0
T133	0	24	0	0
T136	0	31	0	0
T175	408	0	0	0
T284	0	6	0	0
T290	0	16	0	0
T292	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	82201	0	0
T1	46391	2751	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	2289	0	0
T9	0	725	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	2001	0	0
T48	0	945	0	0
T60	0	5002	0	0
T88	0	618	0	0
T118	0	323	0	0
T285	0	180	0	0
T288	0	261	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	943	0	0
T1	46391	16	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	28	0	0
T9	0	12	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	27	0	0
T48	0	22	0	0
T60	0	27	0	0
T88	0	13	0	0
T118	0	10	0	0
T285	0	20	0	0
T288	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4962356	0	0
T1	46391	28818	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4964104	0	0
T1	46391	28825	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1624	0	0
T1	46391	16	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	28	0	0
T9	0	12	0	0
T11	0	30	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	13	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	27	0	0
T48	0	22	0	0
T60	0	27	0	0
T88	0	13	0	0
T89	0	21	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1594	0	0
T1	46391	16	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	28	0	0
T9	0	12	0	0
T11	0	30	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	13	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	27	0	0
T48	0	22	0	0
T60	0	27	0	0
T88	0	13	0	0
T89	0	21	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	943	0	0
T1	46391	16	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	28	0	0
T9	0	12	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	27	0	0
T48	0	22	0	0
T60	0	27	0	0
T88	0	13	0	0
T118	0	10	0	0
T285	0	20	0	0
T288	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	943	0	0
T1	46391	16	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	28	0	0
T9	0	12	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	27	0	0
T48	0	22	0	0
T60	0	27	0	0
T88	0	13	0	0
T118	0	10	0	0
T285	0	20	0	0
T288	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	81121	0	0
T1	46391	2731	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	2252	0	0
T9	0	711	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	1974	0	0
T48	0	922	0	0
T60	0	4972	0	0
T88	0	605	0	0
T118	0	313	0	0
T285	0	160	0	0
T288	0	256	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	791	0	0
T1	46391	12	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	19	0	0
T9	0	10	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	27	0	0
T48	0	21	0	0
T60	0	24	0	0
T88	0	13	0	0
T118	0	10	0	0
T285	0	20	0	0
T288	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T7,T45

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T45
1	0	Covered	T5,T1,T18
1	1	Covered	T1,T7,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T45
0	1	Covered	T45,T293,T294
1	0	Covered	T59,T117

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T47
1	0	Covered	T117

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T8
1	-	Covered	T1,T7,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T45
DetectSt	168	Covered	T1,T7,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T45
DebounceSt->IdleSt	163	Covered	T7,T37,T116
DetectSt->IdleSt	186	Covered	T45,T293,T294
DetectSt->StableSt	191	Covered	T1,T7,T8
IdleSt->DebounceSt	148	Covered	T1,T7,T45
StableSt->IdleSt	206	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T45
0	1	Covered	T1,T7,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T37,T116
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T45
DetectSt	-	-	-	-	1	-	-	Covered	T45,T293,T294
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T45
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T47
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	771	0	0
CntIncr_A	5928678	42584	0	0
CntNoWrap_A	5928678	5453681	0	0
DetectStDropOut_A	5928678	31	0	0
DetectedOut_A	5928678	16142	0	0
DetectedPulseOut_A	5928678	333	0	0
DisabledIdleSt_A	5928678	5096508	0	0
DisabledNoDetection_A	5928678	5097854	0	0
EnterDebounceSt_A	5928678	404	0	0
EnterDetectSt_A	5928678	367	0	0
EnterStableSt_A	5928678	333	0	0
PulseIsPulse_A	5928678	333	0	0
StayInStableSt	5928678	15758	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	281	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	771	0	0
T1	46391	8	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	6	0	0
T8	0	14	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	0	8	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	5	0	0
T45	0	6	0	0
T47	0	4	0	0
T48	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	42584	0	0
T1	46391	1024	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	398	0	0
T8	0	504	0	0
T9	0	66	0	0
T12	0	131	0	0
T13	0	648	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	425	0	0
T45	0	419	0	0
T47	0	274	0	0
T48	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5453681	0	0
T1	46391	45960	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	31	0	0
T8	27461	0	0	0
T9	18041	0	0	0
T10	329770	0	0	0
T32	704	0	0	0
T33	4193	0	0	0
T45	22192	3	0	0
T47	38445	0	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T59	0	1	0	0
T262	0	1	0	0
T293	0	1	0	0
T294	0	2	0	0
T295	0	9	0	0
T296	0	8	0	0
T297	0	1	0	0
T298	0	1	0	0
T299	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	16142	0	0
T1	46391	270	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	140	0	0
T8	0	457	0	0
T9	0	75	0	0
T12	0	54	0	0
T13	0	21	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	14	0	0
T47	0	19	0	0
T48	0	66	0	0
T60	0	428	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	333	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	2	0	0
T8	0	7	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T60	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5096508	0	0
T1	46391	43221	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5097854	0	0
T1	46391	43229	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	404	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	4	0	0
T8	0	7	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	3	0	0
T45	0	3	0	0
T47	0	2	0	0
T48	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	367	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	2	0	0
T8	0	7	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	3	0	0
T47	0	2	0	0
T48	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	333	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	2	0	0
T8	0	7	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T60	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	333	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	2	0	0
T8	0	7	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T60	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	15758	0	0
T1	46391	266	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	138	0	0
T8	0	443	0	0
T9	0	73	0	0
T12	0	53	0	0
T13	0	17	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	12	0	0
T47	0	17	0	0
T48	0	64	0	0
T60	0	427	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	281	0	0
T1	46391	4	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	2	0	0
T12	0	1	0	0
T13	0	4	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T47	0	2	0	0
T60	0	1	0	0
T116	0	5	0	0
T128	0	7	0	0
T144	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T8
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T18,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T8
0	1	Covered	T18,T89,T130
1	0	Covered	T59,T300,T301

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
1	0	Covered	T117

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T9
1	-	Covered	T1,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T8
DetectSt	168	Covered	T1,T18,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T8
DebounceSt->IdleSt	163	Covered	T59,T282,T117
DetectSt->IdleSt	186	Covered	T18,T89,T130
DetectSt->StableSt	191	Covered	T1,T8,T9
IdleSt->DebounceSt	148	Covered	T1,T18,T8
StableSt->IdleSt	206	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T18,T8
0	1	Covered	T1,T18,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T18,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T59,T282,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T8
DetectSt	-	-	-	-	1	-	-	Covered	T18,T89,T130
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T18,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	3036	0	0
CntIncr_A	5928678	110233	0	0
CntNoWrap_A	5928678	5451416	0	0
DetectStDropOut_A	5928678	440	0	0
DetectedOut_A	5928678	84414	0	0
DetectedPulseOut_A	5928678	928	0	0
DisabledIdleSt_A	5928678	4960458	0	0
DisabledNoDetection_A	5928678	4962215	0	0
EnterDebounceSt_A	5928678	1527	0	0
EnterDetectSt_A	5928678	1510	0	0
EnterStableSt_A	5928678	928	0	0
PulseIsPulse_A	5928678	928	0	0
StayInStableSt	5928678	83359	0	0
gen_high_event_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	800	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	3036	0	0
T1	46391	36	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	10	0	0
T9	0	14	0	0
T11	0	48	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	72	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	60	0	0
T48	0	46	0	0
T60	0	40	0	0
T88	0	20	0	0
T89	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	110233	0	0
T1	46391	4788	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	380	0	0
T9	0	448	0	0
T11	0	1728	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	1256	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	2400	0	0
T48	0	1955	0	0
T60	0	6380	0	0
T88	0	690	0	0
T89	0	991	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5451416	0	0
T1	46391	45932	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	440	0	0
T18	4367	36	0	0
T19	423	0	0	0
T20	503	0	0	0
T28	497	0	0	0
T59	0	1	0	0
T79	508	0	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T89	0	14	0	0
T130	0	34	0	0
T133	0	21	0	0
T136	0	22	0	0
T175	408	0	0	0
T301	0	19	0	0
T302	0	6	0	0
T303	0	9	0	0
T304	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	84414	0	0
T1	46391	3471	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	167	0	0
T9	0	593	0	0
T11	0	2207	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	294	0	0
T48	0	644	0	0
T60	0	7528	0	0
T88	0	385	0	0
T118	0	495	0	0
T285	0	1635	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	928	0	0
T1	46391	18	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	5	0	0
T9	0	7	0	0
T11	0	24	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	30	0	0
T48	0	23	0	0
T60	0	20	0	0
T88	0	10	0	0
T118	0	31	0	0
T285	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4960458	0	0
T1	46391	28152	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4962215	0	0
T1	46391	28157	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1527	0	0
T1	46391	18	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	5	0	0
T9	0	7	0	0
T11	0	24	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	36	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	30	0	0
T48	0	23	0	0
T60	0	20	0	0
T88	0	10	0	0
T89	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1510	0	0
T1	46391	18	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	5	0	0
T9	0	7	0	0
T11	0	24	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	36	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	30	0	0
T48	0	23	0	0
T60	0	20	0	0
T88	0	10	0	0
T89	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	928	0	0
T1	46391	18	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	5	0	0
T9	0	7	0	0
T11	0	24	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	30	0	0
T48	0	23	0	0
T60	0	20	0	0
T88	0	10	0	0
T118	0	31	0	0
T285	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	928	0	0
T1	46391	18	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	5	0	0
T9	0	7	0	0
T11	0	24	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	30	0	0
T48	0	23	0	0
T60	0	20	0	0
T88	0	10	0	0
T118	0	31	0	0
T285	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	83359	0	0
T1	46391	3447	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	161	0	0
T9	0	584	0	0
T11	0	2181	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	264	0	0
T48	0	620	0	0
T60	0	7507	0	0
T88	0	375	0	0
T118	0	464	0	0
T285	0	1610	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	800	0	0
T1	46391	12	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	4	0	0
T9	0	5	0	0
T11	0	22	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	30	0	0
T48	0	22	0	0
T60	0	19	0	0
T88	0	10	0	0
T118	0	31	0	0
T285	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T7,T45

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T45
1	0	Covered	T5,T1,T18
1	1	Covered	T1,T7,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T45
0	1	Covered	T13,T144,T132
1	0	Covered	T59,T117

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T45
0	1	Covered	T1,T7,T45
1	0	Covered	T59,T117

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T45
1	-	Covered	T1,T7,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T45
DetectSt	168	Covered	T1,T7,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T45
DebounceSt->IdleSt	163	Covered	T13,T206,T144
DetectSt->IdleSt	186	Covered	T13,T144,T132
DetectSt->StableSt	191	Covered	T1,T7,T45
IdleSt->DebounceSt	148	Covered	T1,T7,T45
StableSt->IdleSt	206	Covered	T1,T7,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T45
0	1	Covered	T1,T7,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T206,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T45
DetectSt	-	-	-	-	1	-	-	Covered	T13,T144,T132
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T45
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T45
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T45
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	846	0	0
CntIncr_A	5928678	45235	0	0
CntNoWrap_A	5928678	5453606	0	0
DetectStDropOut_A	5928678	42	0	0
DetectedOut_A	5928678	15800	0	0
DetectedPulseOut_A	5928678	358	0	0
DisabledIdleSt_A	5928678	5078962	0	0
DisabledNoDetection_A	5928678	5080293	0	0
EnterDebounceSt_A	5928678	442	0	0
EnterDetectSt_A	5928678	404	0	0
EnterStableSt_A	5928678	358	0	0
PulseIsPulse_A	5928678	358	0	0
StayInStableSt	5928678	15417	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	330	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	846	0	0
T1	46391	12	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	12	0	0
T8	0	2	0	0
T9	0	2	0	0
T11	0	4	0	0
T12	0	10	0	0
T13	0	17	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	4	0	0
T45	0	2	0	0
T47	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	45235	0	0
T1	46391	1482	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	888	0	0
T8	0	47	0	0
T9	0	56	0	0
T11	0	188	0	0
T12	0	620	0	0
T13	0	1431	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	212	0	0
T45	0	125	0	0
T47	0	1204	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5453606	0	0
T1	46391	45956	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	42	0	0
T13	21523	8	0	0
T29	2930	0	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T44	1968	0	0	0
T48	11544	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T132	0	4	0	0
T142	541	0	0	0
T144	0	2	0	0
T236	0	2	0	0
T297	0	1	0	0
T298	0	9	0	0
T305	0	2	0	0
T306	0	1	0	0
T307	0	6	0	0
T308	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	15800	0	0
T1	46391	460	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	177	0	0
T8	0	92	0	0
T9	0	85	0	0
T11	0	120	0	0
T12	0	307	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	150	0	0
T45	0	15	0	0
T47	0	862	0	0
T60	0	417	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	358	0	0
T1	46391	6	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	6	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T12	0	5	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T47	0	14	0	0
T60	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5078962	0	0
T1	46391	42503	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5080293	0	0
T1	46391	42509	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	442	0	0
T1	46391	6	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	6	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T12	0	5	0	0
T13	0	9	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T47	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	404	0	0
T1	46391	6	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	6	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T12	0	5	0	0
T13	0	8	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T47	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	358	0	0
T1	46391	6	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	6	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T12	0	5	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T47	0	14	0	0
T60	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	358	0	0
T1	46391	6	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	6	0	0
T8	0	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T12	0	5	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T47	0	14	0	0
T60	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	15417	0	0
T1	46391	454	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	171	0	0
T8	0	91	0	0
T9	0	83	0	0
T11	0	118	0	0
T12	0	302	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	148	0	0
T45	0	14	0	0
T47	0	847	0	0
T60	0	416	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	330	0	0
T1	46391	6	0	0
T2	673	0	0	0
T3	991	0	0	0
T7	0	6	0	0
T8	0	1	0	0
T11	0	2	0	0
T12	0	5	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	0	0	0
T19	423	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T47	0	12	0	0
T60	0	1	0	0
T206	0	2	0	0