Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T8
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T18,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T8
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T18,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T8
0	1	Covered	T18,T11,T89
1	0	Covered	T1,T11,T285

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T46
0	1	Covered	T8,T9,T46
1	0	Covered	T117

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T46
1	-	Covered	T8,T9,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T8
DetectSt	168	Covered	T1,T18,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T9,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T8
DebounceSt->IdleSt	163	Covered	T59,T282,T117
DetectSt->IdleSt	186	Covered	T1,T18,T11
DetectSt->StableSt	191	Covered	T8,T9,T46
IdleSt->DebounceSt	148	Covered	T1,T18,T8
StableSt->IdleSt	206	Covered	T8,T9,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T18,T8
0	1	Covered	T1,T18,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T18,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T59,T282,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T8
DetectSt	-	-	-	-	1	-	-	Covered	T1,T18,T11
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T46
DetectSt	-	-	-	-	0	0	-	Covered	T1,T18,T8
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T46
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	2799	0	0
CntIncr_A	5928678	103501	0	0
CntNoWrap_A	5928678	5451653	0	0
DetectStDropOut_A	5928678	319	0	0
DetectedOut_A	5928678	85413	0	0
DetectedPulseOut_A	5928678	906	0	0
DisabledIdleSt_A	5928678	4964155	0	0
DisabledNoDetection_A	5928678	4965907	0	0
EnterDebounceSt_A	5928678	1409	0	0
EnterDetectSt_A	5928678	1390	0	0
EnterStableSt_A	5928678	906	0	0
PulseIsPulse_A	5928678	906	0	0
StayInStableSt	5928678	84375	0	0
gen_high_event_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	772	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	2799	0	0
T1	46391	14	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	30	0	0
T9	0	26	0	0
T11	0	54	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	42	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	16	0	0
T48	0	44	0	0
T60	0	14	0	0
T88	0	20	0	0
T89	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	103501	0	0
T1	46391	2040	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	705	0	0
T9	0	949	0	0
T11	0	2228	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	723	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	416	0	0
T48	0	1980	0	0
T60	0	2065	0	0
T88	0	720	0	0
T89	0	281	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5451653	0	0
T1	46391	45954	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	319	0	0
T11	0	12	0	0
T18	4367	21	0	0
T19	423	0	0	0
T20	503	0	0	0
T28	497	0	0	0
T59	0	1	0	0
T79	508	0	0	0
T83	3556	0	0	0
T85	437	0	0	0
T86	910	0	0	0
T87	405	0	0	0
T89	0	4	0	0
T130	0	10	0	0
T133	0	14	0	0
T134	0	10	0	0
T136	0	13	0	0
T175	408	0	0	0
T290	0	11	0	0
T309	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	85413	0	0
T8	27461	1625	0	0
T9	18041	1031	0	0
T10	329770	0	0	0
T32	704	0	0	0
T33	4193	0	0	0
T46	0	299	0	0
T47	38445	0	0	0
T48	0	1772	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T60	0	458	0	0
T88	0	1408	0	0
T118	0	1766	0	0
T288	0	1265	0	0
T289	0	305	0	0
T310	0	2206	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	906	0	0
T8	27461	15	0	0
T9	18041	13	0	0
T10	329770	0	0	0
T32	704	0	0	0
T33	4193	0	0	0
T46	0	8	0	0
T47	38445	0	0	0
T48	0	22	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T60	0	7	0	0
T88	0	10	0	0
T118	0	30	0	0
T288	0	22	0	0
T289	0	9	0	0
T310	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4964155	0	0
T1	46391	31179	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	4965907	0	0
T1	46391	31190	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1409	0	0
T1	46391	7	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	15	0	0
T9	0	13	0	0
T11	0	27	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	21	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	8	0	0
T48	0	22	0	0
T60	0	7	0	0
T88	0	10	0	0
T89	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	1390	0	0
T1	46391	7	0	0
T2	673	0	0	0
T3	991	0	0	0
T8	0	15	0	0
T9	0	13	0	0
T11	0	27	0	0
T14	424	0	0	0
T15	501	0	0	0
T16	1062	0	0	0
T17	667	0	0	0
T18	4367	21	0	0
T19	423	0	0	0
T20	503	0	0	0
T46	0	8	0	0
T48	0	22	0	0
T60	0	7	0	0
T88	0	10	0	0
T89	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	906	0	0
T8	27461	15	0	0
T9	18041	13	0	0
T10	329770	0	0	0
T32	704	0	0	0
T33	4193	0	0	0
T46	0	8	0	0
T47	38445	0	0	0
T48	0	22	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T60	0	7	0	0
T88	0	10	0	0
T118	0	30	0	0
T288	0	22	0	0
T289	0	9	0	0
T310	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	906	0	0
T8	27461	15	0	0
T9	18041	13	0	0
T10	329770	0	0	0
T32	704	0	0	0
T33	4193	0	0	0
T46	0	8	0	0
T47	38445	0	0	0
T48	0	22	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T60	0	7	0	0
T88	0	10	0	0
T118	0	30	0	0
T288	0	22	0	0
T289	0	9	0	0
T310	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	84375	0	0
T8	27461	1605	0	0
T9	18041	1016	0	0
T10	329770	0	0	0
T32	704	0	0	0
T33	4193	0	0	0
T46	0	291	0	0
T47	38445	0	0	0
T48	0	1750	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T60	0	451	0	0
T88	0	1398	0	0
T118	0	1736	0	0
T288	0	1240	0	0
T289	0	296	0	0
T310	0	2182	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	772	0	0
T8	27461	10	0	0
T9	18041	11	0	0
T10	329770	0	0	0
T32	704	0	0	0
T33	4193	0	0	0
T46	0	8	0	0
T47	38445	0	0	0
T48	0	22	0	0
T54	823	0	0	0
T55	408	0	0	0
T56	763	0	0	0
T57	517	0	0	0
T60	0	7	0	0
T88	0	10	0	0
T118	0	30	0	0
T288	0	19	0	0
T289	0	9	0	0
T310	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T18,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T45,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T45,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T45,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T45,T8
1	0	Covered	T5,T1,T18
1	1	Covered	T7,T45,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T8
0	1	Covered	T13,T116,T144
1	0	Covered	T59,T117

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T8
0	1	Covered	T7,T45,T8
1	0	Covered	T59,T117

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T45,T8
1	-	Covered	T7,T45,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T45,T8
DetectSt	168	Covered	T7,T45,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T45,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T45,T8
DebounceSt->IdleSt	163	Covered	T7,T45,T8
DetectSt->IdleSt	186	Covered	T13,T116,T144
DetectSt->StableSt	191	Covered	T7,T45,T8
IdleSt->DebounceSt	148	Covered	T7,T45,T8
StableSt->IdleSt	206	Covered	T7,T45,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T45,T8
0	1	Covered	T7,T45,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T45,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T45,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T59,T117
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T45,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T45,T8
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T45,T8
DetectSt	-	-	-	-	1	-	-	Covered	T13,T116,T144
DetectSt	-	-	-	-	0	1	-	Covered	T7,T45,T8
DetectSt	-	-	-	-	0	0	-	Covered	T7,T45,T8
StableSt	-	-	-	-	-	-	1	Covered	T7,T45,T8
StableSt	-	-	-	-	-	-	0	Covered	T7,T45,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5928678	911	0	0
CntIncr_A	5928678	53732	0	0
CntNoWrap_A	5928678	5453541	0	0
DetectStDropOut_A	5928678	37	0	0
DetectedOut_A	5928678	18071	0	0
DetectedPulseOut_A	5928678	393	0	0
DisabledIdleSt_A	5928678	5082399	0	0
DisabledNoDetection_A	5928678	5083730	0	0
EnterDebounceSt_A	5928678	477	0	0
EnterDetectSt_A	5928678	434	0	0
EnterStableSt_A	5928678	393	0	0
PulseIsPulse_A	5928678	393	0	0
StayInStableSt	5928678	17644	0	0
gen_high_level_sva.HighLevelEvent_A	5928678	5456428	0	0
gen_not_sticky_sva.StableStDropOut_A	5928678	356	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	911	0	0
T7	39016	25	0	0
T8	27461	9	0	0
T9	0	4	0	0
T12	0	4	0	0
T13	0	17	0	0
T32	704	0	0	0
T33	4193	0	0	0
T37	0	5	0	0
T45	22192	17	0	0
T47	38445	4	0	0
T48	0	6	0	0
T61	607	0	0	0
T80	504	0	0	0
T81	427	0	0	0
T82	422	0	0	0
T206	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	53732	0	0
T7	39016	1484	0	0
T8	27461	349	0	0
T9	0	182	0	0
T12	0	198	0	0
T13	0	1432	0	0
T32	704	0	0	0
T33	4193	0	0	0
T37	0	383	0	0
T45	22192	630	0	0
T47	38445	206	0	0
T48	0	183	0	0
T61	607	0	0	0
T80	504	0	0	0
T81	427	0	0	0
T82	422	0	0	0
T206	0	1278	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5453541	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	37	0	0
T13	21523	8	0	0
T29	2930	0	0	0
T37	13410	0	0	0
T38	1637	0	0	0
T39	1126	0	0	0
T44	1968	0	0	0
T48	11544	0	0	0
T49	691	0	0	0
T50	738	0	0	0
T116	0	1	0	0
T129	0	1	0	0
T132	0	3	0	0
T138	0	1	0	0
T142	541	0	0	0
T144	0	2	0	0
T275	0	5	0	0
T311	0	1	0	0
T312	0	2	0	0
T313	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	18071	0	0
T7	39016	745	0	0
T8	27461	238	0	0
T9	0	103	0	0
T12	0	172	0	0
T32	704	0	0	0
T33	4193	0	0	0
T37	0	56	0	0
T45	22192	544	0	0
T47	38445	86	0	0
T48	0	227	0	0
T61	607	0	0	0
T80	504	0	0	0
T81	427	0	0	0
T82	422	0	0	0
T128	0	14	0	0
T206	0	551	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	393	0	0
T7	39016	12	0	0
T8	27461	4	0	0
T9	0	2	0	0
T12	0	2	0	0
T32	704	0	0	0
T33	4193	0	0	0
T37	0	2	0	0
T45	22192	8	0	0
T47	38445	2	0	0
T48	0	3	0	0
T61	607	0	0	0
T80	504	0	0	0
T81	427	0	0	0
T82	422	0	0	0
T128	0	3	0	0
T206	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5082399	0	0
T1	46391	45968	0	0
T2	673	272	0	0
T3	991	590	0	0
T4	559	158	0	0
T5	863	2	0	0
T6	502	101	0	0
T14	424	23	0	0
T15	501	100	0	0
T16	1062	661	0	0
T21	526	125	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5083730	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	477	0	0
T7	39016	13	0	0
T8	27461	5	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	0	9	0	0
T32	704	0	0	0
T33	4193	0	0	0
T37	0	3	0	0
T45	22192	9	0	0
T47	38445	2	0	0
T48	0	3	0	0
T61	607	0	0	0
T80	504	0	0	0
T81	427	0	0	0
T82	422	0	0	0
T206	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	434	0	0
T7	39016	12	0	0
T8	27461	4	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	0	8	0	0
T32	704	0	0	0
T33	4193	0	0	0
T37	0	2	0	0
T45	22192	8	0	0
T47	38445	2	0	0
T48	0	3	0	0
T61	607	0	0	0
T80	504	0	0	0
T81	427	0	0	0
T82	422	0	0	0
T206	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	393	0	0
T7	39016	12	0	0
T8	27461	4	0	0
T9	0	2	0	0
T12	0	2	0	0
T32	704	0	0	0
T33	4193	0	0	0
T37	0	2	0	0
T45	22192	8	0	0
T47	38445	2	0	0
T48	0	3	0	0
T61	607	0	0	0
T80	504	0	0	0
T81	427	0	0	0
T82	422	0	0	0
T128	0	3	0	0
T206	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	393	0	0
T7	39016	12	0	0
T8	27461	4	0	0
T9	0	2	0	0
T12	0	2	0	0
T32	704	0	0	0
T33	4193	0	0	0
T37	0	2	0	0
T45	22192	8	0	0
T47	38445	2	0	0
T48	0	3	0	0
T61	607	0	0	0
T80	504	0	0	0
T81	427	0	0	0
T82	422	0	0	0
T128	0	3	0	0
T206	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	17644	0	0
T7	39016	733	0	0
T8	27461	231	0	0
T9	0	101	0	0
T12	0	170	0	0
T32	704	0	0	0
T33	4193	0	0	0
T37	0	54	0	0
T45	22192	536	0	0
T47	38445	84	0	0
T48	0	224	0	0
T61	607	0	0	0
T80	504	0	0	0
T81	427	0	0	0
T82	422	0	0	0
T128	0	11	0	0
T206	0	541	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	5456428	0	0
T1	46391	45980	0	0
T2	673	273	0	0
T3	991	591	0	0
T4	559	159	0	0
T5	863	8	0	0
T6	502	102	0	0
T14	424	24	0	0
T15	501	101	0	0
T16	1062	662	0	0
T21	526	126	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5928678	356	0	0
T7	39016	12	0	0
T8	27461	1	0	0
T9	0	2	0	0
T12	0	2	0	0
T32	704	0	0	0
T33	4193	0	0	0
T37	0	2	0	0
T45	22192	8	0	0
T47	38445	2	0	0
T48	0	3	0	0
T61	607	0	0	0
T80	504	0	0	0
T81	427	0	0	0
T82	422	0	0	0
T128	0	3	0	0
T206	0	8	0	0